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[ORC][MIPS] Fill delay-slot after jr instruction

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MIPS `jr` instruction uses a delay-slot. To escape execution of
arbitrary instruction we should either fill the delay-slot by `nop`
instruction or swap `jr` instruction and logically preceding
instruction. This fix implements the second method to generate a bit
more effective code.

llvm-svn: 351001
This commit is contained in:
Simon Atanasyan 2019-01-12 11:12:08 +00:00
parent f33f561baa
commit 27ba728e62
1 changed files with 5 additions and 5 deletions
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10
lib/ExecutionEngine/Orc/OrcABISupport.cpp
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@ -610,13 +610,13 @@ void OrcMips32_Base::writeResolverCode(uint8_t *ResolverMem,
0x8fa40008, // 0xe8: lw $a0,8($sp)
0x27bd0068, // 0xec: addiu $sp,$sp,104
0x0300f825, // 0xf0: move $ra, $t8
0x00000000, // 0xf4: move $t9, $v0/v1
0x03200008 // 0xf8: jr $t9
0x03200008, // 0xf4: jr $t9
0x00000000, // 0xf8: move $t9, $v0/v1
};
const unsigned ReentryFnAddrOffset = 0x7c; // JIT re-entry fn addr lui
const unsigned CallbackMgrAddrOffset = 0x6c; // Callback manager addr lui
const unsigned Offsett = 0xf4;
const unsigned Offsett = 0xf8;
memcpy(ResolverMem, ResolverCode, sizeof(ResolverCode));
@ -810,8 +810,8 @@ void OrcMips64::writeResolverCode(uint8_t *ResolverMem, JITReentryFn ReentryFn,
0xdfa30008, // 0x10c: ld v1, 8(sp)
0x67bd00d0, // 0x110: daddiu $sp,$sp,208
0x0300f825, // 0x114: move $ra, $t8
0x0040c825, // 0x118: move $t9, $v0
0x03200008 // 0x11c: jr $t9
0x03200008, // 0x118: jr $t9
0x0040c825, // 0x11c: move $t9, $v0
};
const unsigned ReentryFnAddrOffset = 0x8c; // JIT re-entry fn addr lui