RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 04:22:57 +02:00
Code Issues Projects Releases Wiki Activity

Adjust to CopyFromREg changes.

Browse Source 
llvm-svn: 19561
This commit is contained in:
Chris Lattner 2005-01-14 22:37:41 +00:00
parent 3df2651c81
commit 27c91fac94
1 changed files with 14 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/X86/X86ISelPattern.cpp
View File

@ -181,7 +181,8 @@ X86TargetLowering::LowerCallTo(SDOperand Chain,
// Arguments go on the stack in reverse order, as specified by the ABI.
unsigned ArgOffset = 0;
SDOperand StackPtr = DAG.getCopyFromReg(X86::ESP, MVT::i32);
SDOperand StackPtr = DAG.getCopyFromReg(X86::ESP, MVT::i32,
DAG.getEntryNode());
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
unsigned ArgReg;
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
@ -934,6 +935,14 @@ void ISel::EmitCMP(SDOperand LHS, SDOperand RHS) {
BuildMI(BB, Opc, 2).addReg(Tmp1).addImm(CN->getValue());
return;
}
} else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(RHS)) {
if (CN->isExactlyValue(+0.0) ||
CN->isExactlyValue(-0.0)) {
unsigned Reg = SelectExpr(LHS);
BuildMI(BB, X86::FTST, 1).addReg(Reg);
BuildMI(BB, X86::FNSTSW8r, 0);
BuildMI(BB, X86::SAHF, 1);
}
}
Opc = 0;
@ -1021,9 +1030,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
SDNode *Node = N.Val;
SDOperand Op0, Op1;
if (Node->getOpcode() == ISD::CopyFromReg)
if (Node->getOpcode() == ISD::CopyFromReg) {
// FIXME: Handle copy from physregs!
// Just use the specified register as our input.
return dyn_cast<RegSDNode>(Node)->getReg();
}
unsigned &Reg = ExprMap[N];
if (Reg) return Reg;