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https://github.com/RPCS3/llvm-mirror.git
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[AMDGPU] Define AGPR subregs
These are only needed as VGPR counterpart. Differential Revision: https://reviews.llvm.org/D78597
This commit is contained in:
Stanislav Mekhanoshin
parent
efe846883c
commit
27ecf176b1
@ -776,7 +776,8 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
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AMDGPU::VGPR_HI16RegClass.contains(Reg)) {
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IsSGPR = false;
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Width = 1;
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} else if (AMDGPU::AGPR_32RegClass.contains(Reg)) {
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} else if (AMDGPU::AGPR_32RegClass.contains(Reg) ||
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AMDGPU::AGPR_LO16RegClass.contains(Reg)) {
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IsSGPR = false;
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IsAGPR = true;
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Width = 1;
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@ -18,5 +18,5 @@ def VGPRRegBank : RegisterBank<"VGPR",
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def VCCRegBank : RegisterBank <"VCC", [SReg_1]>;
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def AGPRRegBank : RegisterBank <"AGPR",
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[AGPR_32, AReg_64, AReg_96, AReg_128, AReg_160, AReg_192, AReg_256, AReg_512, AReg_1024]
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[AGPR_LO16, AGPR_32, AReg_64, AReg_96, AReg_128, AReg_160, AReg_192, AReg_256, AReg_512, AReg_1024]
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>;
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@ -423,7 +423,8 @@ SIMCCodeEmitter::getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
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MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) ||
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MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) ||
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MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) ||
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MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg))
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MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) ||
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MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg))
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Enc |= 512;
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return Enc;
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@ -681,17 +681,24 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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if (RI.getRegSizeInBits(*RC) == 16) {
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assert(AMDGPU::VGPR_LO16RegClass.contains(SrcReg) ||
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AMDGPU::VGPR_HI16RegClass.contains(SrcReg) ||
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AMDGPU::SReg_LO16RegClass.contains(SrcReg));
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AMDGPU::SReg_LO16RegClass.contains(SrcReg) ||
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AMDGPU::AGPR_LO16RegClass.contains(SrcReg));
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bool IsSGPRDst = AMDGPU::SReg_LO16RegClass.contains(DestReg);
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bool IsSGPRSrc = AMDGPU::SReg_LO16RegClass.contains(SrcReg);
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bool IsAGPRDst = AMDGPU::AGPR_LO16RegClass.contains(DestReg);
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bool IsAGPRSrc = AMDGPU::AGPR_LO16RegClass.contains(SrcReg);
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bool DstLow = AMDGPU::VGPR_LO16RegClass.contains(DestReg) ||
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AMDGPU::SReg_LO16RegClass.contains(DestReg);
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AMDGPU::SReg_LO16RegClass.contains(DestReg) ||
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AMDGPU::AGPR_LO16RegClass.contains(DestReg);
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bool SrcLow = AMDGPU::VGPR_LO16RegClass.contains(SrcReg) ||
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AMDGPU::SReg_LO16RegClass.contains(SrcReg);
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const TargetRegisterClass *DstRC = IsSGPRDst ? &AMDGPU::SReg_32RegClass
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AMDGPU::SReg_LO16RegClass.contains(SrcReg) ||
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AMDGPU::AGPR_LO16RegClass.contains(SrcReg);
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const TargetRegisterClass *DstRC = IsSGPRDst ? &AMDGPU::SGPR_32RegClass
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: IsAGPRDst ? &AMDGPU::AGPR_32RegClass
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: &AMDGPU::VGPR_32RegClass;
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const TargetRegisterClass *SrcRC = IsSGPRSrc ? &AMDGPU::SReg_32RegClass
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const TargetRegisterClass *SrcRC = IsSGPRSrc ? &AMDGPU::SGPR_32RegClass
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: IsAGPRSrc ? &AMDGPU::AGPR_32RegClass
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: &AMDGPU::VGPR_32RegClass;
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MCRegister NewDestReg =
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RI.getMatchingSuperReg(DestReg, DstLow ? AMDGPU::lo16 : AMDGPU::hi16,
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@ -711,6 +718,16 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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return;
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}
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if (IsAGPRDst || IsAGPRSrc) {
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if (!DstLow || !SrcLow) {
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reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
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"Cannot use hi16 subreg with an AGPR!");
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}
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copyPhysReg(MBB, MI, DL, NewDestReg, NewSrcReg, KillSrc);
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return;
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}
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if (IsSGPRSrc && !ST.hasSDWAScalar()) {
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if (!DstLow || !SrcLow) {
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reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
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@ -271,6 +271,10 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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Reserved.set(Low);
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}
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for (auto Reg : AMDGPU::AGPR_32RegClass) {
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Reserved.set(getSubReg(Reg, AMDGPU::hi16));
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}
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// Reserve all the rest AGPRs if there are no instructions to use it.
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if (!ST.hasMAIInsts()) {
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for (unsigned i = 0; i < MaxNumVGPRs; ++i) {
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@ -1315,6 +1319,8 @@ SIRegisterInfo::getVGPRClassForBitWidth(unsigned BitWidth) {
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const TargetRegisterClass *
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SIRegisterInfo::getAGPRClassForBitWidth(unsigned BitWidth) {
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switch (BitWidth) {
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case 16:
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return &AMDGPU::AGPR_LO16RegClass;
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case 32:
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return &AMDGPU::AGPR_32RegClass;
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case 64:
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@ -1374,6 +1380,7 @@ SIRegisterInfo::getPhysRegClass(MCRegister Reg) const {
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&AMDGPU::VGPR_LO16RegClass,
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&AMDGPU::VGPR_HI16RegClass,
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&AMDGPU::SReg_LO16RegClass,
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&AMDGPU::AGPR_LO16RegClass,
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&AMDGPU::VGPR_32RegClass,
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&AMDGPU::SReg_32RegClass,
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&AMDGPU::AGPR_32RegClass,
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@ -1432,7 +1439,7 @@ bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
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bool SIRegisterInfo::hasAGPRs(const TargetRegisterClass *RC) const {
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unsigned Size = getRegSizeInBits(*RC);
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if (Size < 32)
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if (Size < 16)
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return false;
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const TargetRegisterClass *ARC = getAGPRClassForBitWidth(Size);
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if (!ARC) {
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@ -287,11 +287,9 @@ foreach Index = 0-255 in {
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// AccVGPR registers
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foreach Index = 0-255 in {
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def AGPR#Index :
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SIReg <"a"#Index, Index>,
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DwarfRegNum<[!add(Index, 3072), !add(Index, 2048)]> {
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let HWEncoding{8} = 1;
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}
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defm AGPR#Index :
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SIRegLoHi16 <"a"#Index, Index, 1, 1>,
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DwarfRegNum<[!add(Index, 3072), !add(Index, 2048)]>;
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}
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//===----------------------------------------------------------------------===//
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@ -518,6 +516,13 @@ def VGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, VGPR_32, 255, 1, 16, "v">;
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// VGPR 1024-bit registers
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def VGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, VGPR_32, 255, 1, 32, "v">;
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def AGPR_LO16 : RegisterClass<"AMDGPU", Reg16Types.types, 16,
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(add (sequence "AGPR%u_LO16", 0, 255))> {
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let isAllocatable = 0;
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let Size = 16;
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let GeneratePressureSet = 0;
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}
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// AccVGPR 32-bit registers
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def AGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
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(add (sequence "AGPR%u", 0, 255))> {
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@ -1083,6 +1083,11 @@ bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
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// (move from MC* level to Target* level). Return size in bits.
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unsigned getRegBitWidth(unsigned RCID) {
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switch (RCID) {
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case AMDGPU::VGPR_LO16RegClassID:
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case AMDGPU::VGPR_HI16RegClassID:
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case AMDGPU::SGPR_LO16RegClassID:
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case AMDGPU::AGPR_LO16RegClassID:
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return 16;
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case AMDGPU::SGPR_32RegClassID:
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case AMDGPU::VGPR_32RegClassID:
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case AMDGPU::VRegOrLds_32RegClassID:
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@ -29,3 +29,27 @@ body: |
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$vgpr1_hi16 = COPY killed $sgpr0_lo16
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S_ENDPGM 0
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...
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# GCN-LABEL: {{^}}lo_to_lo_illegal_agpr_to_sgpr:
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# GCN: ; illegal copy a0.l to s1.l
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# ERR: error: <unknown>:0:0: in function lo_to_lo_illegal_agpr_to_sgpr void (): illegal SGPR to VGPR copy
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name: lo_to_lo_illegal_agpr_to_sgpr
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tracksRegLiveness: true
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body: |
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bb.0:
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$agpr0 = IMPLICIT_DEF
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$sgpr1_lo16 = COPY $agpr0_lo16
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S_ENDPGM 0
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...
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# GCN-LABEL: {{^}}lo_to_hi_vgpr_to_agpr:
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# GCN: ; illegal copy v0.h to a1.l
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# ERR: error: <unknown>:0:0: in function lo_to_hi_vgpr_to_agpr void (): Cannot use hi16 subreg with an AGPR!
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name: lo_to_hi_vgpr_to_agpr
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tracksRegLiveness: true
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body: |
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bb.0:
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$vgpr0 = IMPLICIT_DEF
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$agpr1_lo16 = COPY killed $vgpr0_hi16
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S_ENDPGM 0
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...
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52
test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-agpr.mir
Normal file
52
test/CodeGen/AMDGPU/lo16-lo16-physreg-copy-agpr.mir
Normal file
@ -0,0 +1,52 @@
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# RUN: llc -march=amdgcn -mcpu=gfx908 -start-before postrapseudos -asm-verbose=0 -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: {{^}}lo_to_lo_agpr_to_agpr:
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# GCN: v_accvgpr_read_b32 [[TMP:v[0-9]+]], a0
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# GCN-NEXT: s_nop 1
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# GCN-NEXT: v_accvgpr_write_b32 a1, [[TMP]]
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name: lo_to_lo_agpr_to_agpr
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tracksRegLiveness: true
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body: |
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bb.0:
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$agpr0 = IMPLICIT_DEF
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$agpr1_lo16 = COPY $agpr0_lo16
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S_ENDPGM 0
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...
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# GCN-LABEL: {{^}}lo_to_lo_samereg:
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# GCN: s_waitcnt
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# GCN-NEXT: s_endpgm
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name: lo_to_lo_samereg
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tracksRegLiveness: true
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body: |
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bb.0:
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$agpr0 = IMPLICIT_DEF
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$agpr0_lo16 = COPY $agpr0_lo16
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S_ENDPGM 0
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...
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# GCN-LABEL: {{^}}lo_to_lo_undef_agpr_to_agpr:
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# GCN: v_accvgpr_read_b32 [[TMP:v[0-9]+]], a1
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# GCN-NEXT: s_nop 1
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# GCN-NEXT: v_accvgpr_write_b32 a2, [[TMP]]
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name: lo_to_lo_undef_agpr_to_agpr
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tracksRegLiveness: true
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body: |
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bb.0:
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$agpr1_lo16 = COPY undef $agpr0_lo16
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$agpr2 = COPY killed $agpr1
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S_ENDPGM 0
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...
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# GCN-LABEL: {{^}}lo_to_lo_sgpr_to_agpr:
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# GCN: v_mov_b32_e32 [[TMP:v[0-9]+]], s0
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# GCN-NEXT: s_nop 1
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# GCN-NEXT: v_accvgpr_write_b32 a1, [[TMP]]
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name: lo_to_lo_sgpr_to_agpr
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tracksRegLiveness: true
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body: |
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bb.0:
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$sgpr0 = IMPLICIT_DEF
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$agpr1_lo16 = COPY $sgpr0_lo16
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S_ENDPGM 0
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...
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@ -33,7 +33,7 @@ body: |
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; CHECK: dead %9:vreg_128 = DS_READ_B128_gfx9 [[V_ADD_U32_e32_]], 0, 0, implicit $exec
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; CHECK: undef %11.sub1:vreg_512 = COPY [[COPY]].sub1
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def dead [[COPY1]], 851978 /* regdef:SReg_LO16 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def dead [[COPY1]], 851978 /* regdef:VGPR_LO16 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1
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; CHECK: %11.sub0:vreg_512 = COPY [[COPY]].sub0
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; CHECK: %11.sub3:vreg_512 = COPY [[COPY]].sub3
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; CHECK: dead %10:vgpr_32 = V_ADD_I32_e32 4, [[V_MOV_B32_e32_1]], implicit-def dead $vcc, implicit $exec
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@ -36,18 +36,18 @@ body: |
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; CHECK: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: bb.1:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def dead %11
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def dead %11
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; CHECK: GLOBAL_STORE_DWORD undef %12:vreg_64, [[BUFFER_LOAD_DWORD_OFFEN]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
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; CHECK: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: [[DS_READ_B64_gfx9_:%[0-9]+]]:vreg_64 = DS_READ_B64_gfx9 undef %14:vgpr_32, 0, 0, implicit $exec :: (load 8, addrspace 3)
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; CHECK: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def %15, 851978 /* regdef:SReg_LO16 */, def %16
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; CHECK: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def %15, 851978 /* regdef:VGPR_LO16 */, def %16
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; CHECK: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec
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; CHECK: [[DS_READ_B32_gfx9_1:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
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; CHECK: [[DS_READ_B32_gfx9_2:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 undef %20:vgpr_32, 0, 0, implicit $exec
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; CHECK: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def %21, 851978 /* regdef:SReg_LO16 */, def %22
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; CHECK: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def %21, 851978 /* regdef:VGPR_LO16 */, def %22
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; CHECK: [[DS_READ_B32_gfx9_3:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def dead [[V_MOV_B32_e32_2]], 851978 /* regdef:SReg_LO16 */, def dead [[V_MOV_B32_e32_3]], 851977 /* reguse:SReg_LO16 */, [[DS_READ_B64_gfx9_]].sub0, 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_2]](tied-def 3), 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_3]](tied-def 5), 851977 /* reguse:SReg_LO16 */, %15, 851977 /* reguse:SReg_LO16 */, %16, 851977 /* reguse:SReg_LO16 */, [[DS_READ_B32_gfx9_1]], 851977 /* reguse:SReg_LO16 */, [[DS_READ_B32_gfx9_]], 851977 /* reguse:SReg_LO16 */, [[DS_READ_B32_gfx9_3]], 851977 /* reguse:SReg_LO16 */, [[DS_READ_B32_gfx9_2]]
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def dead [[V_MOV_B32_e32_2]], 851978 /* regdef:VGPR_LO16 */, def dead [[V_MOV_B32_e32_3]], 851977 /* reguse:VGPR_LO16 */, [[DS_READ_B64_gfx9_]].sub0, 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_2]](tied-def 3), 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_3]](tied-def 5), 851977 /* reguse:VGPR_LO16 */, %15, 851977 /* reguse:VGPR_LO16 */, %16, 851977 /* reguse:VGPR_LO16 */, [[DS_READ_B32_gfx9_1]], 851977 /* reguse:VGPR_LO16 */, [[DS_READ_B32_gfx9_]], 851977 /* reguse:VGPR_LO16 */, [[DS_READ_B32_gfx9_3]], 851977 /* reguse:VGPR_LO16 */, [[DS_READ_B32_gfx9_2]]
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; CHECK: %5.sub1:vreg_64 = COPY [[V_MOV_B32_e32_]]
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; CHECK: DS_WRITE_B32_gfx9 undef %28:vgpr_32, %21, 0, 0, implicit $exec :: (store 4, addrspace 3)
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; CHECK: DS_WRITE_B32_gfx9 undef %29:vgpr_32, %22, 0, 0, implicit $exec :: (store 4, addrspace 3)
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@ -25,9 +25,9 @@ body: |
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; CHECK: bb.1:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 3)
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:SReg_LO16 */, [[DS_READ_B32_gfx9_]]
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def undef %0.sub0, 851978 /* regdef:SReg_LO16 */, def undef %0.sub1
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:VGPR_LO16 */, [[DS_READ_B32_gfx9_]]
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; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def undef %0.sub0, 851978 /* regdef:VGPR_LO16 */, def undef %0.sub1
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; CHECK: S_NOP 0, implicit %0.sub1
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; CHECK: $sgpr10 = S_MOV_B32 -1
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; CHECK: S_BRANCH %bb.1
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@ -63,9 +63,9 @@ body: |
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; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 3)
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:SReg_LO16 */, [[DS_READ_B32_gfx9_]]
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:SReg_LO16 */, def undef %0.sub1, 851978 /* regdef:SReg_LO16 */, def undef %0.sub0
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:VGPR_LO16 */, [[DS_READ_B32_gfx9_]]
|
||||
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def undef %0.sub1, 851978 /* regdef:VGPR_LO16 */, def undef %0.sub0
|
||||
; CHECK: S_NOP 0, implicit %0.sub1
|
||||
; CHECK: $sgpr10 = S_MOV_B32 -1
|
||||
; CHECK: S_BRANCH %bb.1
|
||||
|
||||
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Reference in New Issue
Block a user