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[ARM] One-off identity shuffle
A One-Off Identity mask is a shuffle that is mostly an identity mask from as single source but contains a single element out-of-place, either from a different vector or from another position in the same vector. As opposed to lowering this via a ARMISD::BUILD_VECTOR we can generate an extract/insert pair directly. Under ARM with individually accessible lane elements this often becomes a simple lane move. This also alters the LowerVECTOR_SHUFFLEUsingMovs code to use v4f32 (not v4i32), a more natural type for lane moves. Differential Revision: https://reviews.llvm.org/D95551
This commit is contained in:
David Green
parent
f22bd23bc0
commit
283d18e632
@ -8194,8 +8194,8 @@ static SDValue LowerVECTOR_SHUFFLEUsingMovs(SDValue Op,
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Input = Op->getOperand(1);
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Elt -= 4;
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}
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SDValue BitCast = DAG.getBitcast(MVT::v4i32, Input);
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Parts[Part] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, BitCast,
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SDValue BitCast = DAG.getBitcast(MVT::v4f32, Input);
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Parts[Part] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, BitCast,
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DAG.getConstant(Elt, dl, MVT::i32));
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}
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}
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@ -8214,19 +8214,70 @@ static SDValue LowerVECTOR_SHUFFLEUsingMovs(SDValue Op,
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Parts[Part] ? -1 : ShuffleMask[Part * QuarterSize + i]);
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SDValue NewShuffle = DAG.getVectorShuffle(
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VT, dl, Op->getOperand(0), Op->getOperand(1), NewShuffleMask);
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SDValue BitCast = DAG.getBitcast(MVT::v4i32, NewShuffle);
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SDValue BitCast = DAG.getBitcast(MVT::v4f32, NewShuffle);
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for (int Part = 0; Part < 4; ++Part)
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if (!Parts[Part])
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Parts[Part] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
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Parts[Part] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32,
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BitCast, DAG.getConstant(Part, dl, MVT::i32));
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}
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// Build a vector out of the various parts and bitcast it back to the original
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// type.
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SDValue NewVec = DAG.getBuildVector(MVT::v4i32, dl, Parts);
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SDValue NewVec = DAG.getNode(ARMISD::BUILD_VECTOR, dl, MVT::v4f32, Parts);
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return DAG.getBitcast(VT, NewVec);
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}
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static SDValue LowerVECTOR_SHUFFLEUsingOneOff(SDValue Op,
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ArrayRef<int> ShuffleMask,
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SelectionDAG &DAG) {
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SDValue V1 = Op.getOperand(0);
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SDValue V2 = Op.getOperand(1);
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EVT VT = Op.getValueType();
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unsigned NumElts = VT.getVectorNumElements();
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// An One-Off Identity mask is one that is mostly an identity mask from as
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// single source but contains a single element out-of-place, either from a
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// different vector or from another position in the same vector. As opposed to
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// lowering this via a ARMISD::BUILD_VECTOR we can generate an extract/insert
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// pair directly.
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auto isOneOffIdentityMask = [](ArrayRef<int> Mask, EVT VT, int BaseOffset,
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int &OffElement) {
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OffElement = -1;
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int NonUndef = 0;
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for (int i = 0, NumMaskElts = Mask.size(); i < NumMaskElts; ++i) {
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if (Mask[i] == -1)
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continue;
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NonUndef++;
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if (Mask[i] != i + BaseOffset) {
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if (OffElement == -1)
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OffElement = i;
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else
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return false;
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}
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}
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return NonUndef > 2 && OffElement != -1;
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};
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int OffElement;
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SDValue VInput;
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if (isOneOffIdentityMask(ShuffleMask, VT, 0, OffElement))
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VInput = V1;
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else if (isOneOffIdentityMask(ShuffleMask, VT, NumElts, OffElement))
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VInput = V2;
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else
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return SDValue();
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SDLoc dl(Op);
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EVT SVT = VT.getScalarType() == MVT::i8 || VT.getScalarType() == MVT::i16
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? MVT::i32
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: VT.getScalarType();
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SDValue Elt = DAG.getNode(
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ISD::EXTRACT_VECTOR_ELT, dl, SVT,
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ShuffleMask[OffElement] < (int)NumElts ? V1 : V2,
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DAG.getVectorIdxConstant(ShuffleMask[OffElement] % NumElts, dl));
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return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, VInput, Elt,
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DAG.getVectorIdxConstant(OffElement % NumElts, dl));
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}
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static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
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const ARMSubtarget *ST) {
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SDValue V1 = Op.getOperand(0);
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@ -8360,6 +8411,10 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
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}
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}
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if (ST->hasMVEIntegerOps() && EltSize <= 32)
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if (SDValue V = LowerVECTOR_SHUFFLEUsingOneOff(Op, ShuffleMask, DAG))
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return V;
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// If the shuffle is not directly supported and it has 4 elements, use
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// the PerfectShuffle-generated table to synthesize it from other shuffles.
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unsigned NumElts = VT.getVectorNumElements();
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@ -1481,15 +1481,11 @@ define void @arm_biquad_cascade_df2T_f16(%struct.arm_biquad_cascade_df2T_instanc
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; CHECK-NEXT: vmovx.f16 s6, s12
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; CHECK-NEXT: vfma.f16 q3, q6, r4
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; CHECK-NEXT: vstr.16 s6, [r5, #2]
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; CHECK-NEXT: vmov.f32 s12, s13
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; CHECK-NEXT: vmovx.f16 s6, s13
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; CHECK-NEXT: vmov q7, q3
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; CHECK-NEXT: vmov.f32 s12, s13
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; CHECK-NEXT: vins.f16 s12, s6
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; CHECK-NEXT: vmov.16 q7[2], r7
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; CHECK-NEXT: adds r5, #4
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; CHECK-NEXT: vmov.f32 s13, s29
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; CHECK-NEXT: vmov.f32 s14, s30
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; CHECK-NEXT: vmov.f32 s15, s31
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; CHECK-NEXT: vmov.16 q3[2], r7
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; CHECK-NEXT: vmov q7, q3
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; CHECK-NEXT: le lr, .LBB17_5
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; CHECK-NEXT: .LBB17_6: @ %while.end
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@ -72,10 +72,7 @@ entry:
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define arm_aapcs_vfpcc <4 x i32> @oneoff12_i32(<4 x i32> %src1, <4 x i32> %src2) {
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; CHECK-LABEL: oneoff12_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f32 s5, s1
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; CHECK-NEXT: vmov.f32 s6, s2
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; CHECK-NEXT: vmov.f32 s7, s3
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: vmov.f32 s0, s4
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
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@ -104,6 +101,16 @@ entry:
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <4 x i32> @oneoffundef_i32(<4 x i32> %src1, <4 x i32> %src2) {
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; CHECK-LABEL: oneoffundef_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f32 s1, s4
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <4 x i32> %src1, <4 x i32> %src2, <4 x i32> <i32 0, i32 4, i32 undef, i32 3>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <4 x i32> @shuffle2step_i32(<8 x i32> %src) {
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; CHECK-LABEL: shuffle2step_i32:
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; CHECK: @ %bb.0: @ %entry
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@ -126,27 +133,22 @@ entry:
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define arm_aapcs_vfpcc <4 x i32> @shuffle3step_i32(<16 x i32> %src) {
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; CHECK-LABEL: shuffle3step_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9, d10, d11}
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; CHECK-NEXT: vpush {d8, d9, d10, d11}
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; CHECK-NEXT: vmov.f32 s12, s1
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; CHECK-NEXT: vmov.f32 s13, s4
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; CHECK-NEXT: vmov r0, s10
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; CHECK-NEXT: vdup.32 q4, r0
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; CHECK-NEXT: vmov.f32 s14, s7
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; CHECK-NEXT: vmov.f32 s15, s19
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; CHECK-NEXT: vmov.f32 s16, s0
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; CHECK-NEXT: vmov.f32 s17, s3
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; CHECK-NEXT: vmov r0, s9
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; CHECK-NEXT: vmov.f32 s18, s6
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; CHECK-NEXT: vdup.32 q5, r0
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; CHECK-NEXT: vmov.f32 s4, s2
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; CHECK-NEXT: vmov.f32 s19, s23
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; CHECK-NEXT: vmov.f32 s10, s8
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; CHECK-NEXT: vadd.i32 q3, q4, q3
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; CHECK-NEXT: vmov.f32 s6, s8
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; CHECK-NEXT: vmov.f32 s7, s11
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; CHECK-NEXT: vadd.i32 q0, q3, q1
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; CHECK-NEXT: vpop {d8, d9, d10, d11}
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; CHECK-NEXT: .vsave {d8, d9}
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; CHECK-NEXT: vpush {d8, d9}
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; CHECK-NEXT: vmov.f32 s14, s8
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; CHECK-NEXT: vmov.f32 s15, s11
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; CHECK-NEXT: vmov.f32 s16, s1
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; CHECK-NEXT: vmov.f32 s12, s2
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; CHECK-NEXT: vmov.f32 s17, s4
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; CHECK-NEXT: vmov.f32 s1, s3
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; CHECK-NEXT: vmov.f32 s18, s7
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; CHECK-NEXT: vmov.f32 s2, s6
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; CHECK-NEXT: vmov.f32 s19, s10
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; CHECK-NEXT: vmov.f32 s3, s9
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; CHECK-NEXT: vmov.f32 s13, s5
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; CHECK-NEXT: vadd.i32 q0, q0, q4
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; CHECK-NEXT: vadd.i32 q0, q0, q3
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; CHECK-NEXT: vpop {d8, d9}
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; CHECK-NEXT: bx lr
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entry:
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%s1 = shufflevector <16 x i32> %src, <16 x i32> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
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@ -267,10 +269,7 @@ define arm_aapcs_vfpcc <8 x i16> @oneoff11_i16(<8 x i16> %src1, <8 x i16> %src2)
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; CHECK-LABEL: oneoff11_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u16 r0, q0[1]
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; CHECK-NEXT: vmov.16 q1[2], r0
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; CHECK-NEXT: vmov.u16 r0, q0[3]
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; CHECK-NEXT: vmov.16 q1[3], r0
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; CHECK-NEXT: vmov.f32 s1, s5
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; CHECK-NEXT: vmov.16 q0[2], r0
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7>
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@ -280,12 +279,8 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @oneoff12_i16(<8 x i16> %src1, <8 x i16> %src2) {
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; CHECK-LABEL: oneoff12_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q2, q0
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; CHECK-NEXT: vmovnb.i32 q2, q1
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; CHECK-NEXT: vmov.f32 s9, s1
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; CHECK-NEXT: vmov.f32 s10, s2
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; CHECK-NEXT: vmov.f32 s11, s3
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; CHECK-NEXT: vmov q0, q2
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; CHECK-NEXT: vmov.u16 r0, q1[0]
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; CHECK-NEXT: vmov.16 q0[0], r0
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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@ -306,19 +301,27 @@ entry:
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define arm_aapcs_vfpcc <8 x i16> @oneoff22_i16(<8 x i16> %src1, <8 x i16> %src2) {
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; CHECK-LABEL: oneoff22_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: vmov.u16 r0, q1[6]
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; CHECK-NEXT: vmov.16 q0[0], r0
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; CHECK-NEXT: vmov.u16 r0, q1[1]
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; CHECK-NEXT: vmov.16 q0[1], r0
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; CHECK-NEXT: vmov.f32 s1, s5
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; CHECK-NEXT: vmov.f32 s2, s6
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; CHECK-NEXT: vmov.f32 s3, s7
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 14, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @oneoffundef_i16(<8 x i16> %src1, <8 x i16> %src2) {
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; CHECK-LABEL: oneoffundef_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u16 r0, q0[3]
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; CHECK-NEXT: vmov.16 q1[5], r0
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x i16> %src1, <8 x i16> %src2, <8 x i32> <i32 8, i32 9, i32 undef, i32 undef, i32 12, i32 3, i32 14, i32 15>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @shuffle2step_i16(<16 x i16> %src) {
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; CHECK-LABEL: shuffle2step_i16:
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; CHECK: @ %bb.0: @ %entry
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@ -379,44 +382,36 @@ define arm_aapcs_vfpcc <8 x i16> @shuffle3step_i16(<32 x i16> %src) {
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; CHECK-NEXT: vmov.u16 r0, q2[4]
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; CHECK-NEXT: vmov.16 q5[6], r0
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; CHECK-NEXT: vmov.u16 r0, q0[2]
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; CHECK-NEXT: vmov.16 q6[0], r0
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; CHECK-NEXT: vmov.f32 s15, s19
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; CHECK-NEXT: vmov.16 q4[0], r0
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; CHECK-NEXT: vmov.u16 r0, q0[5]
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; CHECK-NEXT: vmov.16 q6[1], r0
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; CHECK-NEXT: vmov.16 q4[1], r0
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; CHECK-NEXT: vmov.u16 r0, q1[0]
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; CHECK-NEXT: vmov.16 q6[2], r0
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; CHECK-NEXT: vmov.16 q4[2], r0
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; CHECK-NEXT: vmov.u16 r0, q1[3]
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; CHECK-NEXT: vmov.16 q6[3], r0
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; CHECK-NEXT: vmov.16 q4[3], r0
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; CHECK-NEXT: vmov.u16 r0, q2[7]
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; CHECK-NEXT: vmov.16 q5[7], r0
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; CHECK-NEXT: vmov.f32 s26, s7
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; CHECK-NEXT: vmov.f32 s18, s7
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; CHECK-NEXT: vmov.f32 s22, s8
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; CHECK-NEXT: vmov.f32 s15, s19
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; CHECK-NEXT: vmov q4, q5
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; CHECK-NEXT: vmovnb.i32 q4, q6
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; CHECK-NEXT: vmov r1, s24
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; CHECK-NEXT: vmov r0, s18
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; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
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; CHECK-NEXT: vmov r0, s23
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; CHECK-NEXT: vmov.u16 r0, q1[5]
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; CHECK-NEXT: vmov q6, q5
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; CHECK-NEXT: vmovnb.i32 q6, q4
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; CHECK-NEXT: vmov.f32 s18, s26
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; CHECK-NEXT: vmov.f32 s19, s23
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; CHECK-NEXT: vins.f16 s22, s8
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; CHECK-NEXT: vmov r1, s25
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; CHECK-NEXT: vmovx.f16 s23, s9
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; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
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; CHECK-NEXT: vins.f16 s23, s11
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; CHECK-NEXT: vmovx.f16 s8, s0
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; CHECK-NEXT: vins.f16 s8, s2
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; CHECK-NEXT: vmov.u16 r0, q1[5]
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; CHECK-NEXT: vmovx.f16 s9, s3
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; CHECK-NEXT: vmov q0, q5
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; CHECK-NEXT: vins.f16 s9, s5
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; CHECK-NEXT: vmov.16 q2[4], r0
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; CHECK-NEXT: vmovnb.i32 q0, q2
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; CHECK-NEXT: vmov r1, s8
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
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; CHECK-NEXT: vmov r0, s23
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; CHECK-NEXT: vmov r1, s9
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; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
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; CHECK-NEXT: vadd.i16 q0, q3, q0
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; CHECK-NEXT: vmov.f32 s10, s2
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; CHECK-NEXT: vmov.f32 s11, s23
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; CHECK-NEXT: vadd.i16 q0, q3, q2
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; CHECK-NEXT: vadd.i16 q0, q0, q4
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
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; CHECK-NEXT: bx lr
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@ -631,17 +626,8 @@ entry:
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define arm_aapcs_vfpcc <16 x i8> @oneoff11_i8(<16 x i8> %src1, <16 x i8> %src2) {
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; CHECK-LABEL: oneoff11_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u8 r0, q0[0]
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; CHECK-NEXT: vmov.8 q1[0], r0
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; CHECK-NEXT: vmov.u8 r0, q0[1]
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; CHECK-NEXT: vmov.8 q1[1], r0
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; CHECK-NEXT: vmov.8 q1[2], r0
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; CHECK-NEXT: vmov.u8 r0, q0[3]
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; CHECK-NEXT: vmov.8 q1[3], r0
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; CHECK-NEXT: vmov.f32 s5, s1
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; CHECK-NEXT: vmov.f32 s6, s2
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; CHECK-NEXT: vmov.f32 s7, s3
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: vmov.8 q0[2], r0
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; CHECK-NEXT: bx lr
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entry:
|
||||
%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
@ -652,17 +638,7 @@ define arm_aapcs_vfpcc <16 x i8> @oneoff12_i8(<16 x i8> %src1, <16 x i8> %src2)
|
||||
; CHECK-LABEL: oneoff12_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[4]
|
||||
; CHECK-NEXT: vmov.8 q1[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[1]
|
||||
; CHECK-NEXT: vmov.8 q1[1], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[2]
|
||||
; CHECK-NEXT: vmov.8 q1[2], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[3]
|
||||
; CHECK-NEXT: vmov.8 q1[3], r0
|
||||
; CHECK-NEXT: vmov.f32 s5, s1
|
||||
; CHECK-NEXT: vmov.f32 s6, s2
|
||||
; CHECK-NEXT: vmov.f32 s7, s3
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: vmov.8 q0[0], r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 20, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
@ -672,18 +648,9 @@ entry:
|
||||
define arm_aapcs_vfpcc <16 x i8> @oneoff21_i8(<16 x i8> %src1, <16 x i8> %src2) {
|
||||
; CHECK-LABEL: oneoff21_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[0]
|
||||
; CHECK-NEXT: vmov q2, q0
|
||||
; CHECK-NEXT: vmov.8 q0[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[1]
|
||||
; CHECK-NEXT: vmov.8 q0[1], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[2]
|
||||
; CHECK-NEXT: vmov.8 q0[2], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[0]
|
||||
; CHECK-NEXT: vmov.8 q0[3], r0
|
||||
; CHECK-NEXT: vmov.f32 s1, s5
|
||||
; CHECK-NEXT: vmov.f32 s2, s6
|
||||
; CHECK-NEXT: vmov.f32 s3, s7
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[0]
|
||||
; CHECK-NEXT: vmov.8 q1[3], r0
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 17, i32 18, i32 0, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
|
||||
@ -694,21 +661,25 @@ define arm_aapcs_vfpcc <16 x i8> @oneoff22_i8(<16 x i8> %src1, <16 x i8> %src2)
|
||||
; CHECK-LABEL: oneoff22_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[8]
|
||||
; CHECK-NEXT: vmov.8 q1[8], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[15]
|
||||
; CHECK-NEXT: vmov.8 q1[9], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[10]
|
||||
; CHECK-NEXT: vmov.8 q1[10], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[11]
|
||||
; CHECK-NEXT: vmov.8 q1[11], r0
|
||||
; CHECK-NEXT: vmov.f32 s2, s6
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[15]
|
||||
; CHECK-NEXT: vmov.8 q0[9], r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 31, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
|
||||
ret <16 x i8> %out
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <16 x i8> @oneoffundef_i8(<16 x i8> %src1, <16 x i8> %src2) {
|
||||
; CHECK-LABEL: oneoffundef_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[2]
|
||||
; CHECK-NEXT: vmov.8 q0[1], r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <16 x i8> %src1, <16 x i8> %src2, <16 x i32> <i32 undef, i32 2, i32 2, i32 3, i32 undef, i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 undef, i32 13, i32 14, i32 15>
|
||||
ret <16 x i8> %out
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <16 x i8> @shuffle2step_i8(<32 x i8> %src) {
|
||||
; CHECK-LABEL: shuffle2step_i8:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
@ -790,83 +761,78 @@ define arm_aapcs_vfpcc <16 x i8> @shuffle3step_i8(<64 x i8> %src) {
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
|
||||
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[1]
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[1]
|
||||
; CHECK-NEXT: vmov.8 q3[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[4]
|
||||
; CHECK-NEXT: vmov.8 q3[1], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[7]
|
||||
; CHECK-NEXT: vmov.8 q3[2], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[10]
|
||||
; CHECK-NEXT: vmov.8 q3[3], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[13]
|
||||
; CHECK-NEXT: vmov.8 q3[4], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[0]
|
||||
; CHECK-NEXT: vmov.8 q3[5], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[3]
|
||||
; CHECK-NEXT: vmov.8 q3[6], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[6]
|
||||
; CHECK-NEXT: vmov.8 q3[7], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[9]
|
||||
; CHECK-NEXT: vmov.8 q4[0], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[4]
|
||||
; CHECK-NEXT: vmov.8 q4[1], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[7]
|
||||
; CHECK-NEXT: vmov.8 q4[2], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[10]
|
||||
; CHECK-NEXT: vmov.8 q4[3], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[13]
|
||||
; CHECK-NEXT: vmov.8 q3[8], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[12]
|
||||
; CHECK-NEXT: vmov.8 q4[4], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q1[0]
|
||||
; CHECK-NEXT: vmov.8 q3[9], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[15]
|
||||
; CHECK-NEXT: vmov.8 q4[5], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q1[3]
|
||||
; CHECK-NEXT: vmov.8 q3[10], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[2]
|
||||
; CHECK-NEXT: vmov.8 q4[6], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q1[6]
|
||||
; CHECK-NEXT: vmov.8 q3[11], r0
|
||||
; CHECK-NEXT: vmov.8 q4[7], r1
|
||||
; CHECK-NEXT: vmov r0, s14
|
||||
; CHECK-NEXT: vmov r1, s16
|
||||
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[5]
|
||||
; CHECK-NEXT: vmov.8 q5[12], r0
|
||||
; CHECK-NEXT: vmov.8 q4[12], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[8]
|
||||
; CHECK-NEXT: vmov.8 q5[13], r0
|
||||
; CHECK-NEXT: vmov.8 q4[13], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[11]
|
||||
; CHECK-NEXT: vmov.8 q5[14], r0
|
||||
; CHECK-NEXT: vmov.8 q4[14], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[14]
|
||||
; CHECK-NEXT: vmov.8 q5[15], r0
|
||||
; CHECK-NEXT: vmov r1, s17
|
||||
; CHECK-NEXT: vmov r0, s23
|
||||
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
|
||||
; CHECK-NEXT: vmov.8 q4[15], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[2]
|
||||
; CHECK-NEXT: vmov q5, q3
|
||||
; CHECK-NEXT: vmov.8 q5[11], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[0]
|
||||
; CHECK-NEXT: vmov.f32 s14, s22
|
||||
; CHECK-NEXT: vmov.f32 s15, s19
|
||||
; CHECK-NEXT: vmov.8 q4[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[3]
|
||||
; CHECK-NEXT: vmov.8 q4[1], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[6]
|
||||
; CHECK-NEXT: vmov.8 q4[2], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[9]
|
||||
; CHECK-NEXT: vmov.8 q4[3], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[12]
|
||||
; CHECK-NEXT: vmov.8 q4[4], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[15]
|
||||
; CHECK-NEXT: vmov.8 q4[5], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[2]
|
||||
; CHECK-NEXT: vmov.8 q4[6], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[5]
|
||||
; CHECK-NEXT: vmov.8 q4[7], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[8]
|
||||
; CHECK-NEXT: vmov.8 q4[8], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[11]
|
||||
; CHECK-NEXT: vmov.8 q4[9], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[14]
|
||||
; CHECK-NEXT: vmov.8 q4[10], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[1]
|
||||
; CHECK-NEXT: vmov.8 q4[11], r0
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[0]
|
||||
; CHECK-NEXT: vmov r0, s18
|
||||
; CHECK-NEXT: vmov.8 q4[0], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[3]
|
||||
; CHECK-NEXT: vmov.8 q4[1], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[6]
|
||||
; CHECK-NEXT: vmov.8 q4[2], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[9]
|
||||
; CHECK-NEXT: vmov.8 q4[3], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[12]
|
||||
; CHECK-NEXT: vmov.8 q4[4], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q0[15]
|
||||
; CHECK-NEXT: vmov.8 q4[5], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q1[2]
|
||||
; CHECK-NEXT: vmov.8 q4[6], r1
|
||||
; CHECK-NEXT: vmov.u8 r1, q1[5]
|
||||
; CHECK-NEXT: vmov.8 q4[7], r1
|
||||
; CHECK-NEXT: vmov r1, s16
|
||||
; CHECK-NEXT: vmov q5[2], q5[0], r1, r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[4]
|
||||
; CHECK-NEXT: vmov.8 q6[12], r0
|
||||
; CHECK-NEXT: vmov.8 q5[12], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[7]
|
||||
; CHECK-NEXT: vmov.8 q6[13], r0
|
||||
; CHECK-NEXT: vmov.8 q5[13], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[10]
|
||||
; CHECK-NEXT: vmov.8 q6[14], r0
|
||||
; CHECK-NEXT: vmov.8 q5[14], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[13]
|
||||
; CHECK-NEXT: vmov.8 q6[15], r0
|
||||
; CHECK-NEXT: vmov r1, s17
|
||||
; CHECK-NEXT: vmov r0, s27
|
||||
; CHECK-NEXT: vmov q5[3], q5[1], r1, r0
|
||||
; CHECK-NEXT: vmov.8 q5[15], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[1]
|
||||
; CHECK-NEXT: vmov q6, q4
|
||||
; CHECK-NEXT: vmov.8 q6[11], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[2]
|
||||
; CHECK-NEXT: vmov.f32 s18, s26
|
||||
; CHECK-NEXT: vmov.f32 s19, s23
|
||||
; CHECK-NEXT: vadd.i8 q3, q4, q3
|
||||
; CHECK-NEXT: vmov.8 q4[0], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q0[5]
|
||||
; CHECK-NEXT: vmov.8 q4[1], r0
|
||||
@ -880,32 +846,27 @@ define arm_aapcs_vfpcc <16 x i8> @shuffle3step_i8(<64 x i8> %src) {
|
||||
; CHECK-NEXT: vmov.8 q4[5], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[4]
|
||||
; CHECK-NEXT: vmov.8 q4[6], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[6]
|
||||
; CHECK-NEXT: vmov.8 q0[12], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[9]
|
||||
; CHECK-NEXT: vmov.8 q0[13], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[12]
|
||||
; CHECK-NEXT: vmov.8 q0[14], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[15]
|
||||
; CHECK-NEXT: vmov.8 q0[15], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[10]
|
||||
; CHECK-NEXT: vmov.8 q0[8], r0
|
||||
; CHECK-NEXT: vmov.8 q5[8], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[13]
|
||||
; CHECK-NEXT: vmov.8 q0[9], r0
|
||||
; CHECK-NEXT: vmov.8 q5[9], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[0]
|
||||
; CHECK-NEXT: vmov.8 q0[10], r0
|
||||
; CHECK-NEXT: vmov.8 q5[10], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[3]
|
||||
; CHECK-NEXT: vmov.8 q0[11], r0
|
||||
; CHECK-NEXT: vmov.8 q5[11], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q1[7]
|
||||
; CHECK-NEXT: vmov.8 q4[7], r0
|
||||
; CHECK-NEXT: vmov r0, s2
|
||||
; CHECK-NEXT: vmov r1, s16
|
||||
; CHECK-NEXT: vadd.i8 q3, q5, q3
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[6]
|
||||
; CHECK-NEXT: vmov.8 q1[12], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[9]
|
||||
; CHECK-NEXT: vmov.8 q1[13], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[12]
|
||||
; CHECK-NEXT: vmov.8 q1[14], r0
|
||||
; CHECK-NEXT: vmov.u8 r0, q2[15]
|
||||
; CHECK-NEXT: vmov.8 q1[15], r0
|
||||
; CHECK-NEXT: vmov r1, s17
|
||||
; CHECK-NEXT: vmov r0, s7
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
|
||||
; CHECK-NEXT: vadd.i8 q0, q3, q0
|
||||
; CHECK-NEXT: vmov.f32 s18, s22
|
||||
; CHECK-NEXT: vmov.f32 s19, s3
|
||||
; CHECK-NEXT: vadd.i8 q0, q3, q4
|
||||
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -1171,10 +1132,7 @@ entry:
|
||||
define arm_aapcs_vfpcc <4 x float> @oneoff12_f32(<4 x float> %src1, <4 x float> %src2) {
|
||||
; CHECK-LABEL: oneoff12_f32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov.f32 s5, s1
|
||||
; CHECK-NEXT: vmov.f32 s6, s2
|
||||
; CHECK-NEXT: vmov.f32 s7, s3
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: vmov.f32 s0, s4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <4 x float> %src1, <4 x float> %src2, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
|
||||
@ -1227,20 +1185,19 @@ define arm_aapcs_vfpcc <4 x float> @shuffle3step_f32(<16 x float> %src) {
|
||||
; CHECKFP: @ %bb.0: @ %entry
|
||||
; CHECKFP-NEXT: .vsave {d8, d9}
|
||||
; CHECKFP-NEXT: vpush {d8, d9}
|
||||
; CHECKFP-NEXT: vmov.f32 s12, s1
|
||||
; CHECKFP-NEXT: vmov.f32 s16, s0
|
||||
; CHECKFP-NEXT: vmov.f32 s13, s4
|
||||
; CHECKFP-NEXT: vmov.f32 s17, s3
|
||||
; CHECKFP-NEXT: vmov.f32 s14, s7
|
||||
; CHECKFP-NEXT: vmov.f32 s18, s6
|
||||
; CHECKFP-NEXT: vmov.f32 s4, s2
|
||||
; CHECKFP-NEXT: vmov.f32 s15, s10
|
||||
; CHECKFP-NEXT: vmov.f32 s19, s9
|
||||
; CHECKFP-NEXT: vmov.f32 s10, s8
|
||||
; CHECKFP-NEXT: vadd.f32 q3, q4, q3
|
||||
; CHECKFP-NEXT: vmov.f32 s6, s8
|
||||
; CHECKFP-NEXT: vmov.f32 s7, s11
|
||||
; CHECKFP-NEXT: vadd.f32 q0, q3, q1
|
||||
; CHECKFP-NEXT: vmov.f32 s14, s8
|
||||
; CHECKFP-NEXT: vmov.f32 s15, s11
|
||||
; CHECKFP-NEXT: vmov.f32 s16, s1
|
||||
; CHECKFP-NEXT: vmov.f32 s12, s2
|
||||
; CHECKFP-NEXT: vmov.f32 s17, s4
|
||||
; CHECKFP-NEXT: vmov.f32 s1, s3
|
||||
; CHECKFP-NEXT: vmov.f32 s18, s7
|
||||
; CHECKFP-NEXT: vmov.f32 s2, s6
|
||||
; CHECKFP-NEXT: vmov.f32 s19, s10
|
||||
; CHECKFP-NEXT: vmov.f32 s3, s9
|
||||
; CHECKFP-NEXT: vmov.f32 s13, s5
|
||||
; CHECKFP-NEXT: vadd.f32 q0, q0, q4
|
||||
; CHECKFP-NEXT: vadd.f32 q0, q0, q3
|
||||
; CHECKFP-NEXT: vpop {d8, d9}
|
||||
; CHECKFP-NEXT: bx lr
|
||||
entry:
|
||||
@ -1360,9 +1317,9 @@ entry:
|
||||
define arm_aapcs_vfpcc <8 x half> @oneoff11_f16(<8 x half> %src1, <8 x half> %src2) {
|
||||
; CHECK-LABEL: oneoff11_f16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmovx.f16 s4, s1
|
||||
; CHECK-NEXT: vmovx.f16 s1, s0
|
||||
; CHECK-NEXT: vins.f16 s1, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s0
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q0[2], r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
@ -1372,12 +1329,8 @@ entry:
|
||||
define arm_aapcs_vfpcc <8 x half> @oneoff12_f16(<8 x half> %src1, <8 x half> %src2) {
|
||||
; CHECK-LABEL: oneoff12_f16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmovx.f16 s8, s0
|
||||
; CHECK-NEXT: vins.f16 s4, s8
|
||||
; CHECK-NEXT: vmov.f32 s5, s1
|
||||
; CHECK-NEXT: vmov.f32 s6, s2
|
||||
; CHECK-NEXT: vmov.f32 s7, s3
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: vmov r0, s4
|
||||
; CHECK-NEXT: vmov.16 q0[0], r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
@ -1387,7 +1340,8 @@ entry:
|
||||
define arm_aapcs_vfpcc <8 x half> @oneoff21_f16(<8 x half> %src1, <8 x half> %src2) {
|
||||
; CHECK-LABEL: oneoff21_f16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vins.f16 s5, s0
|
||||
; CHECK-NEXT: vmov r0, s0
|
||||
; CHECK-NEXT: vmov.16 q1[3], r0
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -1399,9 +1353,8 @@ define arm_aapcs_vfpcc <8 x half> @oneoff22_f16(<8 x half> %src1, <8 x half> %sr
|
||||
; CHECK-LABEL: oneoff22_f16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: vmovx.f16 s4, s0
|
||||
; CHECK-NEXT: vmov.f32 s0, s3
|
||||
; CHECK-NEXT: vins.f16 s0, s4
|
||||
; CHECK-NEXT: vmov r0, s3
|
||||
; CHECK-NEXT: vmov.16 q0[0], r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 14, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
@ -1446,8 +1399,6 @@ entry:
|
||||
define arm_aapcs_vfpcc <8 x half> @shuffle3step_f16(<32 x half> %src) {
|
||||
; CHECKFP-LABEL: shuffle3step_f16:
|
||||
; CHECKFP: @ %bb.0: @ %entry
|
||||
; CHECKFP-NEXT: .save {r4, lr}
|
||||
; CHECKFP-NEXT: push {r4, lr}
|
||||
; CHECKFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
|
||||
; CHECKFP-NEXT: vpush {d8, d9, d10, d11, d12, d13}
|
||||
; CHECKFP-NEXT: vmovx.f16 s16, s2
|
||||
@ -1475,30 +1426,19 @@ define arm_aapcs_vfpcc <8 x half> @shuffle3step_f16(<32 x half> %src) {
|
||||
; CHECKFP-NEXT: vins.f16 s24, s2
|
||||
; CHECKFP-NEXT: vmov.f32 s18, s8
|
||||
; CHECKFP-NEXT: vmovx.f16 s25, s3
|
||||
; CHECKFP-NEXT: vmovx.f16 s3, s9
|
||||
; CHECKFP-NEXT: vins.f16 s3, s11
|
||||
; CHECKFP-NEXT: vins.f16 s25, s5
|
||||
; CHECKFP-NEXT: vmov r3, s3
|
||||
; CHECKFP-NEXT: vmovx.f16 s0, s10
|
||||
; CHECKFP-NEXT: vins.f16 s25, s5
|
||||
; CHECKFP-NEXT: vmov.f32 s15, s19
|
||||
; CHECKFP-NEXT: vmovx.f16 s27, s9
|
||||
; CHECKFP-NEXT: vins.f16 s9, s0
|
||||
; CHECKFP-NEXT: vmovx.f16 s2, s6
|
||||
; CHECKFP-NEXT: vins.f16 s2, s8
|
||||
; CHECKFP-NEXT: vmov r4, s24
|
||||
; CHECKFP-NEXT: vmov r0, s2
|
||||
; CHECKFP-NEXT: vmov r12, s14
|
||||
; CHECKFP-NEXT: vmov q1[2], q1[0], r4, r0
|
||||
; CHECKFP-NEXT: vmov lr, s25
|
||||
; CHECKFP-NEXT: vmov r1, s12
|
||||
; CHECKFP-NEXT: vmov q1[3], q1[1], lr, r3
|
||||
; CHECKFP-NEXT: vins.f16 s27, s11
|
||||
; CHECKFP-NEXT: vmov.f32 s23, s9
|
||||
; CHECKFP-NEXT: vmov q0[2], q0[0], r1, r12
|
||||
; CHECKFP-NEXT: vmov r1, s13
|
||||
; CHECKFP-NEXT: vadd.f16 q1, q5, q1
|
||||
; CHECKFP-NEXT: vmov r2, s19
|
||||
; CHECKFP-NEXT: vmov q0[3], q0[1], r1, r2
|
||||
; CHECKFP-NEXT: vadd.f16 q0, q1, q0
|
||||
; CHECKFP-NEXT: vmovx.f16 s26, s6
|
||||
; CHECKFP-NEXT: vins.f16 s26, s8
|
||||
; CHECKFP-NEXT: vadd.f16 q0, q5, q6
|
||||
; CHECKFP-NEXT: vadd.f16 q0, q0, q3
|
||||
; CHECKFP-NEXT: vpop {d8, d9, d10, d11, d12, d13}
|
||||
; CHECKFP-NEXT: pop {r4, pc}
|
||||
; CHECKFP-NEXT: bx lr
|
||||
entry:
|
||||
%s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
|
||||
%s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
|
||||
@ -1681,20 +1621,17 @@ define arm_aapcs_vfpcc i64 @scalar_to_vector_i32(<8 x i16> %v) {
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .pad #8
|
||||
; CHECK-NEXT: sub sp, #8
|
||||
; CHECK-NEXT: adr r1, .LCPI73_0
|
||||
; CHECK-NEXT: adr r2, .LCPI76_0
|
||||
; CHECK-NEXT: vmov.u16 r0, q0[0]
|
||||
; CHECK-NEXT: vldrw.u32 q1, [r1]
|
||||
; CHECK-NEXT: vldrw.u32 q0, [r2]
|
||||
; CHECK-NEXT: mov r1, sp
|
||||
; CHECK-NEXT: vmov.32 q0[0], r0
|
||||
; CHECK-NEXT: mov r2, sp
|
||||
; CHECK-NEXT: vmov.f32 s1, s5
|
||||
; CHECK-NEXT: vmov.f32 s2, s6
|
||||
; CHECK-NEXT: vmov.f32 s3, s7
|
||||
; CHECK-NEXT: vstrh.32 q0, [r2]
|
||||
; CHECK-NEXT: vstrh.32 q0, [r1]
|
||||
; CHECK-NEXT: ldrd r0, r1, [sp], #8
|
||||
; CHECK-NEXT: bx lr
|
||||
; CHECK-NEXT: .p2align 4
|
||||
; CHECK-NEXT: @ %bb.1:
|
||||
; CHECK-NEXT: .LCPI73_0:
|
||||
; CHECK-NEXT: .LCPI76_0:
|
||||
; CHECK-NEXT: .zero 4
|
||||
; CHECK-NEXT: .long 7 @ 0x7
|
||||
; CHECK-NEXT: .long 1 @ 0x1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1045,19 +1045,21 @@ define void @vst4_v2f16(<2 x half> *%src, <8 x half> *%dst) {
|
||||
; CHECK-LABEL: vst4_v2f16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vldmia r0, {s4, s5}
|
||||
; CHECK-NEXT: vmovx.f16 s12, s5
|
||||
; CHECK-NEXT: ldr r0, [r0, #8]
|
||||
; CHECK-NEXT: vmov.f64 d0, d2
|
||||
; CHECK-NEXT: vdup.32 q2, r0
|
||||
; CHECK-NEXT: vins.f16 s0, s5
|
||||
; CHECK-NEXT: vmov.f32 s1, s8
|
||||
; CHECK-NEXT: vins.f16 s1, s9
|
||||
; CHECK-NEXT: vmovx.f16 s2, s4
|
||||
; CHECK-NEXT: vmovx.f16 s4, s9
|
||||
; CHECK-NEXT: vins.f16 s2, s12
|
||||
; CHECK-NEXT: vmovx.f16 s3, s8
|
||||
; CHECK-NEXT: vins.f16 s3, s4
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: vldr s0, [r0, #8]
|
||||
; CHECK-NEXT: vmovx.f16 s12, s4
|
||||
; CHECK-NEXT: vins.f16 s4, s5
|
||||
; CHECK-NEXT: vmov.f32 s1, s0
|
||||
; CHECK-NEXT: vmovx.f16 s14, s0
|
||||
; CHECK-NEXT: vmov q2, q1
|
||||
; CHECK-NEXT: vins.f16 s0, s1
|
||||
; CHECK-NEXT: vmovx.f16 s4, s5
|
||||
; CHECK-NEXT: vmov.f32 s9, s0
|
||||
; CHECK-NEXT: vins.f16 s12, s4
|
||||
; CHECK-NEXT: vmovx.f16 s0, s1
|
||||
; CHECK-NEXT: vmov.f32 s10, s12
|
||||
; CHECK-NEXT: vins.f16 s14, s0
|
||||
; CHECK-NEXT: vmov.f32 s11, s14
|
||||
; CHECK-NEXT: vstrh.16 q2, [r1]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%s1 = getelementptr <2 x half>, <2 x half>* %src, i32 0
|
||||
@ -1078,23 +1080,29 @@ entry:
|
||||
define void @vst4_v4f16(<4 x half> *%src, <16 x half> *%dst) {
|
||||
; CHECK-LABEL: vst4_v4f16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: .save {r7, lr}
|
||||
; CHECK-NEXT: push {r7, lr}
|
||||
; CHECK-NEXT: ldrd lr, r12, [r0]
|
||||
; CHECK-NEXT: ldrd r3, r2, [r0, #8]
|
||||
; CHECK-NEXT: ldrd r4, r0, [r0, #16]
|
||||
; CHECK-NEXT: vmov q0[2], q0[0], lr, r3
|
||||
; CHECK-NEXT: vmov q0[3], q0[1], r12, r2
|
||||
; CHECK-NEXT: vmov q1[2], q1[0], r4, r4
|
||||
; CHECK-NEXT: vmov.32 q0[0], lr
|
||||
; CHECK-NEXT: vmov.32 q1[0], r3
|
||||
; CHECK-NEXT: vmov.32 q0[1], r12
|
||||
; CHECK-NEXT: vmov.32 q1[1], r2
|
||||
; CHECK-NEXT: ldrd r2, r0, [r0, #16]
|
||||
; CHECK-NEXT: vmov.f32 s2, s4
|
||||
; CHECK-NEXT: vmov.f32 s3, s5
|
||||
; CHECK-NEXT: vmov.f32 s8, s1
|
||||
; CHECK-NEXT: vmov q1[3], q1[1], r0, r0
|
||||
; CHECK-NEXT: vins.f16 s8, s3
|
||||
; CHECK-NEXT: vmovx.f16 s12, s3
|
||||
; CHECK-NEXT: vins.f16 s8, s5
|
||||
; CHECK-NEXT: vmov.32 q1[0], r2
|
||||
; CHECK-NEXT: vmov.32 q1[1], r0
|
||||
; CHECK-NEXT: vmov.f32 s6, s4
|
||||
; CHECK-NEXT: vmov.f32 s7, s5
|
||||
; CHECK-NEXT: vmov.f32 s9, s5
|
||||
; CHECK-NEXT: vins.f16 s9, s7
|
||||
; CHECK-NEXT: vins.f16 s9, s5
|
||||
; CHECK-NEXT: vmovx.f16 s10, s1
|
||||
; CHECK-NEXT: vins.f16 s10, s12
|
||||
; CHECK-NEXT: vmovx.f16 s12, s7
|
||||
; CHECK-NEXT: vmovx.f16 s12, s5
|
||||
; CHECK-NEXT: vmovx.f16 s11, s5
|
||||
; CHECK-NEXT: vins.f16 s11, s12
|
||||
; CHECK-NEXT: vstrh.16 q2, [r1, #16]
|
||||
@ -1109,7 +1117,7 @@ define void @vst4_v4f16(<4 x half> *%src, <16 x half> *%dst) {
|
||||
; CHECK-NEXT: vmov.f32 s2, s8
|
||||
; CHECK-NEXT: vins.f16 s3, s4
|
||||
; CHECK-NEXT: vstrh.16 q0, [r1]
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: pop {r7, pc}
|
||||
entry:
|
||||
%s1 = getelementptr <4 x half>, <4 x half>* %src, i32 0
|
||||
%l1 = load <4 x half>, <4 x half>* %s1, align 4
|
||||
|
||||
Loading…
Reference in New Issue
Block a user