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[ARM GlobalISel] Fix selection of G_SELECT

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G_SELECT uses a 1-bit scalar for the condition, and is currently
implemented with a plain CMPri against 0. This means that values such as
0x1110 are interpreted as true, when instead the higher bits should be
treated as undefined and therefore ignored. Replace the CMPri with a
TSTri against 0x1, which performs an implicit AND, yielding the expected
result.

llvm-svn: 357153
This commit is contained in:
Diana Picus 2019-03-28 09:09:27 +00:00
parent 079fdb41d4
commit 284b4fed5e
4 changed files with 9 additions and 11 deletions
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8
lib/Target/ARM/ARMInstructionSelector.cpp
View File

@ -111,7 +111,6 @@ private:
unsigned MOVCCi;
// Used for G_SELECT
unsigned CMPri;
unsigned MOVCCr;
unsigned TSTri;
@ -319,7 +318,6 @@ ARMInstructionSelector::OpcodeCache::OpcodeCache(const ARMSubtarget &STI) {
STORE_OPCODE(MOVi, MOVi);
STORE_OPCODE(MOVCCi, MOVCCi);
STORE_OPCODE(CMPri, CMPri);
STORE_OPCODE(MOVCCr, MOVCCr);
STORE_OPCODE(TSTri, TSTri);
@ -767,13 +765,13 @@ bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
auto InsertBefore = std::next(MIB->getIterator());
auto &DbgLoc = MIB->getDebugLoc();
// Compare the condition to 0.
// Compare the condition to 1.
auto CondReg = MIB->getOperand(1).getReg();
assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
"Unsupported types for select operation");
auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.CMPri))
auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.TSTri))
.addUse(CondReg)
.addImm(0)
.addImm(1)
.add(predOps(ARMCC::AL));
if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
return false;

4
test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
View File

@ -881,7 +881,7 @@ body: |
%2(s1) = G_TRUNC %1(s32)
%3(s32) = G_SELECT %2(s1), %0, %1
; CHECK: CMPri [[VREGY]], 0, 14, $noreg, implicit-def $cpsr
; CHECK: TSTri [[VREGY]], 1, 14, $noreg, implicit-def $cpsr
; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
$r0 = COPY %3(s32)
@ -919,7 +919,7 @@ body: |
%3(s1) = G_TRUNC %2(s32)
%4(p0) = G_SELECT %3(s1), %0, %1
; CHECK: CMPri [[VREGC]], 0, 14, $noreg, implicit-def $cpsr
; CHECK: TSTri [[VREGC]], 1, 14, $noreg, implicit-def $cpsr
; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
$r0 = COPY %4(p0)

4
test/CodeGen/ARM/GlobalISel/arm-isel.ll
View File

@ -405,7 +405,7 @@ entry:
define arm_aapcscc i32 @test_select_i32(i32 %a, i32 %b, i1 %cond) {
; CHECK-LABEL: test_select_i32
; CHECK: cmp r2, #0
; CHECK: tst r2, #1
; CHECK: moveq r0, r1
; CHECK: bx lr
entry:
@ -415,7 +415,7 @@ entry:
define arm_aapcscc i32* @test_select_ptr(i32* %a, i32* %b, i1 %cond) {
; CHECK-LABEL: test_select_ptr
; CHECK: cmp r2, #0
; CHECK: tst r2, #1
; CHECK: moveq r0, r1
; CHECK: bx lr
entry:

4
test/CodeGen/ARM/GlobalISel/thumb-select-select.mir
View File

@ -29,7 +29,7 @@ body: |
; CHECK: [[VREGC:%[0-9]+]]:gprnopc = COPY [[VREGY]]
%3(s32) = G_SELECT %2(s1), %0, %1
; CHECK: t2CMPri [[VREGC]], 0, 14, $noreg, implicit-def $cpsr
; CHECK: t2TSTri [[VREGC]], 1, 14, $noreg, implicit-def $cpsr
; CHECK: [[RES:%[0-9]+]]:rgpr = t2MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
$r0 = COPY %3(s32)
@ -68,7 +68,7 @@ body: |
; CHECK: [[VREGC:%[0-9]+]]:gprnopc = COPY [[VREGC32]]
%4(p0) = G_SELECT %3(s1), %0, %1
; CHECK: t2CMPri [[VREGC]], 0, 14, $noreg, implicit-def $cpsr
; CHECK: t2TSTri [[VREGC]], 1, 14, $noreg, implicit-def $cpsr
; CHECK: [[RES:%[0-9]+]]:rgpr = t2MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr
$r0 = COPY %4(p0)