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AMDGPU/GlobalISel: Implement select() for 32-bit @llvm.minnun and @llvm.maxnum
Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D46172 llvm-svn: 337056
This commit is contained in:
Tom Stellard
parent
790008fff4
commit
28569c8fb0
@ -85,6 +85,18 @@ class GISelVop3Pat2CommutePat <
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(inst src0_vt:$src1, src1_vt:$src0)
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>;
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class GISelVop3Pat2ModsPat <
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SDPatternOperator node,
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Instruction inst,
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ValueType dst_vt,
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ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
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(dst_vt (node (src0_vt (VOP3Mods0 src0_vt:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omods)),
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(src1_vt (VOP3Mods src1_vt:$src1, i32:$src1_modifiers)))),
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(inst i32:$src0_modifiers, src0_vt:$src0,
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i32:$src1_modifiers, src1_vt:$src1, $clamp, $omods)
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>;
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multiclass GISelVop2IntrPat <
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SDPatternOperator node, Instruction inst,
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ValueType dst_vt, ValueType src_vt = dst_vt> {
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@ -119,3 +131,8 @@ def : GISelVop3Pat2CommutePat <sra, V_ASHRREV_I32_e64, i32>;
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// this is even supported yet.
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defm : GISelVop2IntrPat <
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int_amdgcn_cvt_pkrtz, V_CVT_PKRTZ_F16_F32_e32, v2f16, f32>;
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defm : GISelVop2IntrPat <int_maxnum, V_MAX_F32_e32, f32>;
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def : GISelVop3Pat2ModsPat <int_maxnum, V_MAX_F64, f64>;
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defm : GISelVop2IntrPat <int_minnum, V_MIN_F32_e32, f32>;
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def : GISelVop3Pat2ModsPat <int_minnum, V_MIN_F64, f64>;
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@ -186,6 +186,8 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I,
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switch (IntrinsicID) {
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default:
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break;
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case Intrinsic::maxnum:
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case Intrinsic::minnum:
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case Intrinsic::amdgcn_cvt_pkrtz:
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return selectImpl(I, CoverageInfo);
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66
test/CodeGen/AMDGPU/GlobalISel/inst-select-maxnum.mir
Normal file
66
test/CodeGen/AMDGPU/GlobalISel/inst-select-maxnum.mir
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@ -0,0 +1,66 @@
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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
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--- |
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define void @maxnum(i32 addrspace(1)* %global0) { ret void }
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...
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---
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name: maxnum
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legalized: true
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regBankSelected: true
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# GCN-LABEL: name: maxnum
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
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; GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[VGPR1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = COPY $vgpr1
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%3:vgpr(s64) = COPY $vgpr3_vgpr4
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; GCN: [[SGPR64_0:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
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; GCN: [[VGPR64_0:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
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; GCN: [[VGPR64_1:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
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%10:sgpr(s64) = COPY $sgpr10_sgpr11
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%11:vgpr(s64) = COPY $vgpr10_vgpr11
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%12:vgpr(s64) = COPY $vgpr12_vgpr13
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; maxnum vs
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; GCN: V_MAX_F32_e32 [[SGPR0]], [[VGPR0]]
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%4:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.maxnum.f32), %1, %0
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; maxnum sv
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; GCN: V_MAX_F32_e32 [[SGPR0]], [[VGPR0]]
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%5:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.maxnum.f32), %0, %1
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; maxnum vv
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; GCN: V_MAX_F32_e32 [[VGPR0]], [[VGPR1]]
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%6:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.maxnum.f32), %1, %2
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G_STORE %4, %3 :: (store 4 into %ir.global0)
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G_STORE %5, %3 :: (store 4 into %ir.global0)
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G_STORE %6, %3 :: (store 4 into %ir.global0)
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; 64-bit
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; maxnum vs
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; GCN: V_MAX_F64 0, [[SGPR64_0]], 0, [[VGPR64_0]], 0, 0
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%14:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.maxnum.f64), %10, %11
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; maxnum sv
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; GCN: V_MAX_F64 0, [[VGPR64_0]], 0, [[SGPR64_0]], 0, 0
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%15:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.maxnum.f64), %11, %10
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; maxnum vv
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; GCN: V_MAX_F64 0, [[VGPR64_0]], 0, [[VGPR64_1]], 0, 0
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%16:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.maxnum.f64), %11, %12
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G_STORE %14, %3 :: (store 8 into %ir.global0)
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G_STORE %15, %3 :: (store 8 into %ir.global0)
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G_STORE %16, %3 :: (store 8 into %ir.global0)
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...
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---
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65
test/CodeGen/AMDGPU/GlobalISel/inst-select-minnum.mir
Normal file
65
test/CodeGen/AMDGPU/GlobalISel/inst-select-minnum.mir
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@ -0,0 +1,65 @@
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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
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--- |
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define void @minnum(i32 addrspace(1)* %global0) { ret void }
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...
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---
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name: minnum
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legalized: true
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regBankSelected: true
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# GCN-LABEL: name: minnum
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4, $sgpr10_sgpr11, $vgpr10_vgpr11, $vgpr12_vgpr13
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; GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[VGPR1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = COPY $vgpr1
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%3:vgpr(s64) = COPY $vgpr3_vgpr4
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; GCN: [[SGPR64_0:%[0-9]+]]:sreg_64_xexec = COPY $sgpr10_sgpr11
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; GCN: [[VGPR64_0:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
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; GCN: [[VGPR64_1:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
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%10:sgpr(s64) = COPY $sgpr10_sgpr11
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%11:vgpr(s64) = COPY $vgpr10_vgpr11
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%12:vgpr(s64) = COPY $vgpr12_vgpr13
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; minnum vs
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; GCN: V_MIN_F32_e32 [[SGPR0]], [[VGPR0]]
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%4:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.minnum.f32), %1, %0
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; minnum sv
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; GCN: V_MIN_F32_e32 [[SGPR0]], [[VGPR0]]
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%5:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.minnum.f32), %0, %1
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; minnum vv
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; GCN: V_MIN_F32_e32 [[VGPR0]], [[VGPR1]]
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%6:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.minnum.f32), %1, %2
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G_STORE %4, %3 :: (store 4 into %ir.global0)
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G_STORE %5, %3 :: (store 4 into %ir.global0)
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G_STORE %6, %3 :: (store 4 into %ir.global0)
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; 64-bit
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; minnum vs
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; GCN: V_MIN_F64 0, [[SGPR64_0]], 0, [[VGPR64_0]], 0, 0
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%14:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.minnum.f64), %10, %11
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; minnum sv
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; GCN: V_MIN_F64 0, [[VGPR64_0]], 0, [[SGPR64_0]], 0, 0
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%15:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.minnum.f64), %11, %10
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; minnum vv
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; GCN: V_MIN_F64 0, [[VGPR64_0]], 0, [[VGPR64_1]], 0, 0
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%16:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.minnum.f64), %11, %12
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G_STORE %14, %3 :: (store 8 into %ir.global0)
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G_STORE %15, %3 :: (store 8 into %ir.global0)
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G_STORE %16, %3 :: (store 8 into %ir.global0)
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...
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---
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