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[NFC][AArch64] Autogenerate a few more tests

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This commit is contained in:
Roman Lebedev 2021-06-23 16:09:38 +03:00
parent 033b3a9ef6
commit 285eb4c722
2 changed files with 1575 additions and 123 deletions
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99
test/CodeGen/AArch64/check-sign-bit-before-extension.ll
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@ -1,4 +1,5 @@
; RUN: llc -mtriple aarch64-gnu-linux -o - -asm-verbose=0 %s | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-gnu-linux -o - | FileCheck %s
; These tests make sure that the `cmp` instruction is rendered with an
; instruction that checks the sign bit of the original unextended data
@ -9,9 +10,17 @@
; looking through a `sign_extend_inreg` and tests that determine the
; sign bit looking through a `sign_extend`.
; CHECK-LABEL: f_i8_sign_extend_inreg:
; CHECK: tbnz w0, #7, .LBB
define i32 @f_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: f_i8_sign_extend_inreg:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: tbnz w0, #7, .LBB0_2
; CHECK-NEXT: // %bb.1: // %A
; CHECK-NEXT: add w0, w8, w1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: // %B
; CHECK-NEXT: add w0, w8, w2
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i8 %in, -1
%ext = zext i8 %in to i32
@ -26,9 +35,17 @@ B:
ret i32 %retB
}
; CHECK-LABEL: f_i16_sign_extend_inreg:
; CHECK: tbnz w0, #15, .LBB
define i32 @f_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: f_i16_sign_extend_inreg:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: tbnz w0, #15, .LBB1_2
; CHECK-NEXT: // %bb.1: // %A
; CHECK-NEXT: add w0, w8, w1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: // %B
; CHECK-NEXT: add w0, w8, w2
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i16 %in, -1
%ext = zext i16 %in to i32
@ -43,9 +60,17 @@ B:
ret i32 %retB
}
; CHECK-LABEL: f_i32_sign_extend_inreg:
; CHECK: tbnz w0, #31, .LBB
define i64 @f_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: f_i32_sign_extend_inreg:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: tbnz w0, #31, .LBB2_2
; CHECK-NEXT: // %bb.1: // %A
; CHECK-NEXT: add x0, x8, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB2_2: // %B
; CHECK-NEXT: add x0, x8, x2
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i32 %in, -1
%ext = zext i32 %in to i64
@ -60,9 +85,17 @@ B:
ret i64 %retB
}
; CHECK-LABEL: g_i8_sign_extend_inreg:
; CHECK: tbnz w0, #7, .LBB
define i32 @g_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: g_i8_sign_extend_inreg:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: tbnz w0, #7, .LBB3_2
; CHECK-NEXT: // %bb.1: // %B
; CHECK-NEXT: add w0, w8, w2
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB3_2: // %A
; CHECK-NEXT: add w0, w8, w1
; CHECK-NEXT: ret
entry:
%cmp = icmp slt i8 %in, 0
%ext = zext i8 %in to i32
@ -77,9 +110,17 @@ B:
ret i32 %retB
}
; CHECK-LABEL: g_i16_sign_extend_inreg:
; CHECK: tbnz w0, #15, .LBB
define i32 @g_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: g_i16_sign_extend_inreg:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: tbnz w0, #15, .LBB4_2
; CHECK-NEXT: // %bb.1: // %B
; CHECK-NEXT: add w0, w8, w2
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB4_2: // %A
; CHECK-NEXT: add w0, w8, w1
; CHECK-NEXT: ret
entry:
%cmp = icmp slt i16 %in, 0
%ext = zext i16 %in to i32
@ -94,9 +135,17 @@ B:
ret i32 %retB
}
; CHECK-LABEL: g_i32_sign_extend_inreg:
; CHECK: tbnz w0, #31, .LBB
define i64 @g_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: g_i32_sign_extend_inreg:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: tbnz w0, #31, .LBB5_2
; CHECK-NEXT: // %bb.1: // %B
; CHECK-NEXT: add x0, x8, x2
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB5_2: // %A
; CHECK-NEXT: add x0, x8, x1
; CHECK-NEXT: ret
entry:
%cmp = icmp slt i32 %in, 0
%ext = zext i32 %in to i64
@ -111,9 +160,17 @@ B:
ret i64 %retB
}
; CHECK-LABEL: f_i32_sign_extend_i64:
; CHECK: tbnz w0, #31, .LBB
define i64 @f_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: f_i32_sign_extend_i64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: tbnz w0, #31, .LBB6_2
; CHECK-NEXT: // %bb.1: // %A
; CHECK-NEXT: add x0, x8, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB6_2: // %B
; CHECK-NEXT: add x0, x8, x2
; CHECK-NEXT: ret
entry:
%inext = sext i32 %in to i64
%cmp = icmp sgt i64 %inext, -1
@ -129,9 +186,17 @@ B:
ret i64 %retB
}
; CHECK-LABEL: g_i32_sign_extend_i64:
; CHECK: tbnz w0, #31, .LBB
define i64 @g_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: g_i32_sign_extend_i64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: tbnz w0, #31, .LBB7_2
; CHECK-NEXT: // %bb.1: // %B
; CHECK-NEXT: add x0, x8, x2
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB7_2: // %A
; CHECK-NEXT: add x0, x8, x1
; CHECK-NEXT: ret
entry:
%inext = sext i32 %in to i64
%cmp = icmp slt i64 %inext, 0

1599
test/CodeGen/AArch64/sve-breakdown-scalable-vectortype.ll
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