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https://github.com/RPCS3/llvm-mirror.git
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Reland "[PowerPC] Implement instruction clustering for stores"
Commit 3c0b3250 introduced store fusion for PowerPC target, but it brought failure under UB sanitizer and was reverted. This patch fixes them.
This commit is contained in:
Qiu Chaofan
parent
dcb7b4b709
commit
28702b5551
@ -174,6 +174,9 @@ def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
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"HasAddisLoadFusion", "true",
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"Power8 Addis-Load fusion",
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[FeatureFusion]>;
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def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true",
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"Target supports store clustering",
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[FeatureFusion]>;
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def FeatureUnalignedFloats :
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SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
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"true", "CPU does not trap on unaligned FP access">;
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@ -345,10 +348,12 @@ def ProcessorFeatures {
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// Power10
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// For P10 CPU we assume that all of the existing features from Power9
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// still exist with the exception of those we know are Power9 specific.
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list<SubtargetFeature> FusionFeatures = [FeatureStoreFusion];
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list<SubtargetFeature> P10AdditionalFeatures =
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[DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
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!listconcat(FusionFeatures, [
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DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
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FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
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FeaturePairedVectorMemops];
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FeaturePairedVectorMemops]);
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list<SubtargetFeature> P10SpecificFeatures = [];
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list<SubtargetFeature> P10InheritableFeatures =
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!listconcat(P9InheritableFeatures, P10AdditionalFeatures);
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@ -2222,6 +2222,112 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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return true;
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}
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bool PPCInstrInfo::getMemOperandsWithOffsetWidth(
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const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
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int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
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const TargetRegisterInfo *TRI) const {
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const MachineOperand *BaseOp;
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OffsetIsScalable = false;
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if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI))
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return false;
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BaseOps.push_back(BaseOp);
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return true;
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}
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static bool isLdStSafeToCluster(const MachineInstr &LdSt,
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const TargetRegisterInfo *TRI) {
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// If this is a volatile load/store, don't mess with it.
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if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3)
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return false;
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if (LdSt.getOperand(2).isFI())
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return true;
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assert(LdSt.getOperand(2).isReg() && "Expected a reg operand.");
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// Can't cluster if the instruction modifies the base register
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// or it is update form. e.g. ld r2,3(r2)
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if (LdSt.modifiesRegister(LdSt.getOperand(2).getReg(), TRI))
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return false;
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return true;
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}
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// Only cluster instruction pair that have the same opcode, and they are
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// clusterable according to PowerPC specification.
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static bool isClusterableLdStOpcPair(unsigned FirstOpc, unsigned SecondOpc,
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const PPCSubtarget &Subtarget) {
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switch (FirstOpc) {
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default:
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return false;
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case PPC::STD:
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case PPC::STFD:
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case PPC::STXSD:
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case PPC::DFSTOREf64:
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return FirstOpc == SecondOpc;
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// PowerPC backend has opcode STW/STW8 for instruction "stw" to deal with
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// 32bit and 64bit instruction selection. They are clusterable pair though
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// they are different opcode.
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case PPC::STW:
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case PPC::STW8:
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return SecondOpc == PPC::STW || SecondOpc == PPC::STW8;
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}
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}
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bool PPCInstrInfo::shouldClusterMemOps(
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ArrayRef<const MachineOperand *> BaseOps1,
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ArrayRef<const MachineOperand *> BaseOps2, unsigned NumLoads,
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unsigned NumBytes) const {
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assert(BaseOps1.size() == 1 && BaseOps2.size() == 1);
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const MachineOperand &BaseOp1 = *BaseOps1.front();
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const MachineOperand &BaseOp2 = *BaseOps2.front();
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assert((BaseOp1.isReg() || BaseOp1.isFI()) &&
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"Only base registers and frame indices are supported.");
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// The NumLoads means the number of loads that has been clustered.
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// Don't cluster memory op if there are already two ops clustered at least.
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if (NumLoads > 2)
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return false;
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// Cluster the load/store only when they have the same base
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// register or FI.
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if ((BaseOp1.isReg() != BaseOp2.isReg()) ||
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(BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) ||
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(BaseOp1.isFI() && BaseOp1.getIndex() != BaseOp2.getIndex()))
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return false;
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// Check if the load/store are clusterable according to the PowerPC
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// specification.
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const MachineInstr &FirstLdSt = *BaseOp1.getParent();
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const MachineInstr &SecondLdSt = *BaseOp2.getParent();
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unsigned FirstOpc = FirstLdSt.getOpcode();
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unsigned SecondOpc = SecondLdSt.getOpcode();
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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// Cluster the load/store only when they have the same opcode, and they are
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// clusterable opcode according to PowerPC specification.
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if (!isClusterableLdStOpcPair(FirstOpc, SecondOpc, Subtarget))
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return false;
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// Can't cluster load/store that have ordered or volatile memory reference.
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if (!isLdStSafeToCluster(FirstLdSt, TRI) ||
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!isLdStSafeToCluster(SecondLdSt, TRI))
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return false;
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int64_t Offset1 = 0, Offset2 = 0;
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unsigned Width1 = 0, Width2 = 0;
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const MachineOperand *Base1 = nullptr, *Base2 = nullptr;
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if (!getMemOperandWithOffsetWidth(FirstLdSt, Base1, Offset1, Width1, TRI) ||
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!getMemOperandWithOffsetWidth(SecondLdSt, Base2, Offset2, Width2, TRI) ||
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Width1 != Width2)
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return false;
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assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 &&
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"getMemOperandWithOffsetWidth return incorrect base op");
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// The caller should already have ordered FirstMemOp/SecondMemOp by offset.
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assert(Offset1 <= Offset2 && "Caller should have ordered offsets.");
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return Offset1 + Width1 == Offset2;
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}
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/// GetInstSize - Return the number of bytes of code the specified
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/// instruction may be. This returns the maximum number of bytes.
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///
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@ -4664,7 +4770,8 @@ bool PPCInstrInfo::getMemOperandWithOffsetWidth(
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return false;
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// Handle only loads/stores with base register followed by immediate offset.
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if (LdSt.getNumExplicitOperands() != 3)
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if (!LdSt.getOperand(1).isImm() ||
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(!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()))
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return false;
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if (!LdSt.getOperand(1).isImm() ||
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(!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()))
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@ -494,6 +494,19 @@ public:
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int64_t &Offset, unsigned &Width,
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const TargetRegisterInfo *TRI) const;
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/// Get the base operand and byte offset of an instruction that reads/writes
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/// memory.
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bool getMemOperandsWithOffsetWidth(
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const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
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int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
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const TargetRegisterInfo *TRI) const override;
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/// Returns true if the two given memory operations should be scheduled
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/// adjacent.
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bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
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ArrayRef<const MachineOperand *> BaseOps2,
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unsigned NumLoads, unsigned NumBytes) const override;
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/// Return true if two MIs access different memory addresses and false
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/// otherwise
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bool
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@ -120,6 +120,7 @@ void PPCSubtarget::initializeEnvironment() {
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HasHTM = false;
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HasFloat128 = false;
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HasFusion = false;
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HasStoreFusion = false;
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HasAddiLoadFusion = false;
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HasAddisLoadFusion = false;
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IsISA3_0 = false;
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@ -140,6 +140,7 @@ protected:
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bool HasHTM;
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bool HasFloat128;
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bool HasFusion;
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bool HasStoreFusion;
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bool HasAddiLoadFusion;
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bool HasAddisLoadFusion;
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bool IsISA3_0;
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@ -317,6 +318,7 @@ public:
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bool isISA3_1() const { return IsISA3_1; }
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bool useLongCalls() const { return UseLongCalls; }
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bool hasFusion() const { return HasFusion; }
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bool hasStoreFusion() const { return HasStoreFusion; }
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bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
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bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
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bool needsSwapsForVSXMemOps() const {
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@ -278,6 +278,8 @@ static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
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std::make_unique<GenericScheduler>(C));
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// add DAG Mutations here.
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DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
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if (ST.hasStoreFusion())
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DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
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if (ST.hasFusion())
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DAG->addMutation(createPowerPCMacroFusionDAGMutation());
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@ -292,6 +294,8 @@ static ScheduleDAGInstrs *createPPCPostMachineScheduler(
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std::make_unique<PPCPostRASchedStrategy>(C) :
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std::make_unique<PostGenericScheduler>(C), true);
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// add DAG Mutations here.
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if (ST.hasStoreFusion())
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DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
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if (ST.hasFusion())
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DAG->addMutation(createPowerPCMacroFusionDAGMutation());
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return DAG;
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268
test/CodeGen/PowerPC/fusion-load-store.ll
Normal file
268
test/CodeGen/PowerPC/fusion-load-store.ll
Normal file
@ -0,0 +1,268 @@
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; Test if several consecutive loads/stores can be clustered(fused) by scheduler. The
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; scheduler will print "Cluster ld/st SU(x) - SU(y)" if SU(x) and SU(y) are fused.
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; REQUIRES: asserts
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; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 \
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; RUN: -mattr=-paired-vector-memops,-pcrelative-memops -verify-misched \
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; RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s
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define i64 @store_i64(i64* nocapture %P, i64 %v) {
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entry:
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: store_i64:%bb.0
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; CHECK: Cluster ld/st SU([[SU3:[0-9]+]]) - SU([[SU4:[0-9]+]])
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; CHECK: Cluster ld/st SU([[SU2:[0-9]+]]) - SU([[SU5:[0-9]+]])
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; CHECK: SU([[SU2]]): STD %[[REG:[0-9]+]]:g8rc, 24
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; CHECK: SU([[SU3]]): STD %[[REG]]:g8rc, 16
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; CHECK: SU([[SU4]]): STD %[[REG]]:g8rc, 8
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; CHECK: SU([[SU5]]): STD %[[REG]]:g8rc, 32
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: store_i64:%bb.0
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; CHECK: Cluster ld/st SU([[SU0:[0-9]+]]) - SU([[SU1:[0-9]+]])
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; CHECK: Cluster ld/st SU([[SU2:[0-9]+]]) - SU([[SU3:[0-9]+]])
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; CHECK: SU([[SU0]]): STD renamable $x[[REG:[0-9]+]], 16
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; CHECK: SU([[SU1]]): STD renamable $x[[REG]], 8
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; CHECK: SU([[SU2]]): STD renamable $x[[REG]], 24
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; CHECK: SU([[SU3]]): STD renamable $x[[REG]], 32
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%arrayidx = getelementptr inbounds i64, i64* %P, i64 3
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store i64 %v, i64* %arrayidx
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%arrayidx1 = getelementptr inbounds i64, i64* %P, i64 2
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store i64 %v, i64* %arrayidx1
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%arrayidx2 = getelementptr inbounds i64, i64* %P, i64 1
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store i64 %v, i64* %arrayidx2
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%arrayidx3 = getelementptr inbounds i64, i64* %P, i64 4
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store i64 %v, i64* %arrayidx3
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ret i64 %v
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}
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define i32 @store_i32(i32* nocapture %P, i32 %v) {
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entry:
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: store_i32:%bb.0
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; CHECK: Cluster ld/st SU([[SU3:[0-9]+]]) - SU([[SU4:[0-9]+]])
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; CHECK: Cluster ld/st SU([[SU2:[0-9]+]]) - SU([[SU5:[0-9]+]])
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; CHECK: SU([[SU2]]): STW %[[REG:[0-9]+]].sub_32:g8rc, 52
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; CHECK: SU([[SU3]]): STW %[[REG]].sub_32:g8rc, 48
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; CHECK: SU([[SU4]]): STW %[[REG]].sub_32:g8rc, 44
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; CHECK: SU([[SU5]]): STW %[[REG]].sub_32:g8rc, 56
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: store_i32:%bb.0
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; CHECK: Cluster ld/st SU([[SU0:[0-9]+]]) - SU([[SU1:[0-9]+]])
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; CHECK: Cluster ld/st SU([[SU2:[0-9]+]]) - SU([[SU3:[0-9]+]])
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; CHECK: SU([[SU0]]): STW renamable $r[[REG:[0-9]+]], 48
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; CHECK: SU([[SU1]]): STW renamable $r[[REG]], 44
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; CHECK: SU([[SU2]]): STW renamable $r[[REG]], 52
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; CHECK: SU([[SU3]]): STW renamable $r[[REG]], 56
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%arrayidx = getelementptr inbounds i32, i32* %P, i32 13
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store i32 %v, i32* %arrayidx
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%arrayidx1 = getelementptr inbounds i32, i32* %P, i32 12
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store i32 %v, i32* %arrayidx1
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%arrayidx2 = getelementptr inbounds i32, i32* %P, i32 11
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store i32 %v, i32* %arrayidx2
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%arrayidx3 = getelementptr inbounds i32, i32* %P, i32 14
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store i32 %v, i32* %arrayidx3
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ret i32 %v
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}
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define void @store_i64_neg(i64* nocapture %P, i64 %v) #0 {
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entry:
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: store_i64_neg:%bb.0
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; CHECK: Cluster ld/st SU([[SU2:[0-9]+]]) - SU([[SU5:[0-9]+]])
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; CHECK: Cluster ld/st SU([[SU3:[0-9]+]]) - SU([[SU4:[0-9]+]])
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; CHECK: SU([[SU2]]): STD %[[REG:[0-9]+]]:g8rc, -24
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; CHECK: SU([[SU3]]): STD %[[REG]]:g8rc, -8
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; CHECK: SU([[SU4]]): STD %[[REG]]:g8rc, -16
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; CHECK: SU([[SU5]]): STD %[[REG]]:g8rc, -32
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: store_i64_neg:%bb.0
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; CHECK: Cluster ld/st SU([[SU2:[0-9]+]]) - SU([[SU3:[0-9]+]])
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; CHECK: Cluster ld/st SU([[SU0:[0-9]+]]) - SU([[SU1:[0-9]+]])
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; CHECK: SU([[SU0]]): STD renamable $x[[REG:[0-9]+]], -8
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; CHECK: SU([[SU1]]): STD renamable $x[[REG]], -16
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; CHECK: SU([[SU2]]): STD renamable $x[[REG]], -24
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; CHECK: SU([[SU3]]): STD renamable $x[[REG]], -32
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%arrayidx = getelementptr inbounds i64, i64* %P, i64 -3
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store i64 %v, i64* %arrayidx
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%arrayidx1 = getelementptr inbounds i64, i64* %P, i64 -1
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store i64 %v, i64* %arrayidx1
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%arrayidx2 = getelementptr inbounds i64, i64* %P, i64 -2
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store i64 %v, i64* %arrayidx2
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%arrayidx3 = getelementptr inbounds i64, i64* %P, i64 -4
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store i64 %v, i64* %arrayidx3
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ret void
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}
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define void @store_i32_neg(i32* nocapture %P, i32 %v) #0 {
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entry:
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: store_i32_neg:%bb.0
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; CHECK: Cluster ld/st SU([[SU2:[0-9]+]]) - SU([[SU5:[0-9]+]])
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; CHECK: Cluster ld/st SU([[SU3:[0-9]+]]) - SU([[SU4:[0-9]+]])
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; CHECK: SU([[SU2]]): STW %[[REG:[0-9]+]].sub_32:g8rc, -12
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; CHECK: SU([[SU3]]): STW %[[REG]].sub_32:g8rc, -4
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; CHECK: SU([[SU4]]): STW %[[REG]].sub_32:g8rc, -8
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; CHECK: SU([[SU5]]): STW %[[REG]].sub_32:g8rc, -16
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: store_i32_neg:%bb.0
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; CHECK: Cluster ld/st SU([[SU2:[0-9]+]]) - SU([[SU3:[0-9]+]])
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; CHECK: Cluster ld/st SU([[SU0:[0-9]+]]) - SU([[SU1:[0-9]+]])
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; CHECK:SU([[SU0]]): STW renamable $r[[REG:[0-9]+]], -4
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; CHECK:SU([[SU1]]): STW renamable $r[[REG]], -8
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; CHECK:SU([[SU2]]): STW renamable $r[[REG]], -12
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; CHECK:SU([[SU3]]): STW renamable $r[[REG]], -16
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%arrayidx = getelementptr inbounds i32, i32* %P, i32 -3
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store i32 %v, i32* %arrayidx
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%arrayidx1 = getelementptr inbounds i32, i32* %P, i32 -1
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store i32 %v, i32* %arrayidx1
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%arrayidx2 = getelementptr inbounds i32, i32* %P, i32 -2
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store i32 %v, i32* %arrayidx2
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%arrayidx3 = getelementptr inbounds i32, i32* %P, i32 -4
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store i32 %v, i32* %arrayidx3
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ret void
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}
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define void @store_double(double* nocapture %P, double %v) {
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entry:
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: store_double:%bb.0
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; CHECK: Cluster ld/st SU([[SU3:[0-9]+]]) - SU([[SU4:[0-9]+]])
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; CHECK: Cluster ld/st SU([[SU2:[0-9]+]]) - SU([[SU5:[0-9]+]])
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; CHECK: SU([[SU2]]): DFSTOREf64 %[[REG:[0-9]+]]:vsfrc, 24
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; CHECK: SU([[SU3]]): DFSTOREf64 %[[REG]]:vsfrc, 8
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; CHECK: SU([[SU4]]): DFSTOREf64 %[[REG]]:vsfrc, 16
|
||||
; CHECK: SU([[SU5]]): DFSTOREf64 %[[REG]]:vsfrc, 32
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK-LABEL: store_double:%bb.0
|
||||
; CHECK: Cluster ld/st SU([[SU0:[0-9]+]]) - SU([[SU1:[0-9]+]])
|
||||
; CHECK: Cluster ld/st SU([[SU2:[0-9]+]]) - SU([[SU3:[0-9]+]])
|
||||
; CHECK: SU([[SU0]]): STFD renamable $f[[REG:[0-9]+]], 8
|
||||
; CHECK: SU([[SU1]]): STFD renamable $f[[REG]], 16
|
||||
; CHECK: SU([[SU2]]): STFD renamable $f[[REG]], 24
|
||||
; CHECK: SU([[SU3]]): STFD renamable $f[[REG]], 32
|
||||
%arrayidx = getelementptr inbounds double, double* %P, i64 3
|
||||
store double %v, double* %arrayidx
|
||||
%arrayidx1 = getelementptr inbounds double, double* %P, i64 1
|
||||
store double %v, double* %arrayidx1
|
||||
%arrayidx2 = getelementptr inbounds double, double* %P, i64 2
|
||||
store double %v, double* %arrayidx2
|
||||
%arrayidx3 = getelementptr inbounds double, double* %P, i64 4
|
||||
store double %v, double* %arrayidx3
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_float(float* nocapture %P, float %v) {
|
||||
entry:
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK-LABEL: store_float:%bb.0
|
||||
; CHECK-NOT: Cluster ld/st
|
||||
; CHECK-NOT: Cluster ld/st
|
||||
; CHECK: SU([[SU2]]): DFSTOREf32 %[[REG:[0-9]+]]:vssrc, 12
|
||||
; CHECK: SU([[SU3]]): DFSTOREf32 %[[REG]]:vssrc, 4
|
||||
; CHECK: SU([[SU4]]): DFSTOREf32 %[[REG]]:vssrc, 8
|
||||
; CHECK: SU([[SU5]]): DFSTOREf32 %[[REG]]:vssrc, 16
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK-LABEL: store_float:%bb.0
|
||||
; CHECK-NOT: Cluster ld/st
|
||||
; CHECK-NOT: Cluster ld/st
|
||||
; CHECK: SU([[SU0]]): STFS renamable $f[[REG:[0-9]+]], 12
|
||||
; CHECK: SU([[SU1]]): STFS renamable $f[[REG]], 4
|
||||
; CHECK: SU([[SU2]]): STFS renamable $f[[REG]], 8
|
||||
; CHECK: SU([[SU3]]): STFS renamable $f[[REG]], 16
|
||||
%arrayidx = getelementptr inbounds float, float* %P, i64 3
|
||||
store float %v, float* %arrayidx
|
||||
%arrayidx1 = getelementptr inbounds float, float* %P, i64 1
|
||||
store float %v, float* %arrayidx1
|
||||
%arrayidx2 = getelementptr inbounds float, float* %P, i64 2
|
||||
store float %v, float* %arrayidx2
|
||||
%arrayidx3 = getelementptr inbounds float, float* %P, i64 4
|
||||
store float %v, float* %arrayidx3
|
||||
ret void
|
||||
}
|
||||
|
||||
; Cannot fuse the store/load if there is volatile in between
|
||||
define i64 @store_volatile(i64* nocapture %P, i64 %v) {
|
||||
entry:
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK-LABEL: store_volatile:%bb.0
|
||||
; CHECK-NOT: Cluster ld/st
|
||||
; CHECK: SU([[SU2]]): STD %[[REG:[0-9]+]]:g8rc, 24
|
||||
; CHECK: SU([[SU3]]): STD %[[REG]]:g8rc, 16
|
||||
; CHECK: SU([[SU4]]): STD %[[REG]]:g8rc, 8
|
||||
; CHECK: SU([[SU5]]): STD %[[REG]]:g8rc, 32
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK-LABEL: store_volatile:%bb.0
|
||||
; CHECK-NOT: Cluster ld/st
|
||||
; CHECK: SU([[SU0]]): STD renamable $x[[REG:[0-9]+]], 24
|
||||
; CHECK: SU([[SU1]]): STD renamable $x[[REG]], 16
|
||||
; CHECK: SU([[SU2]]): STD renamable $x[[REG]], 8
|
||||
; CHECK: SU([[SU3]]): STD renamable $x[[REG]], 32
|
||||
%arrayidx = getelementptr inbounds i64, i64* %P, i64 3
|
||||
store volatile i64 %v, i64* %arrayidx
|
||||
%arrayidx1 = getelementptr inbounds i64, i64* %P, i64 2
|
||||
store volatile i64 %v, i64* %arrayidx1
|
||||
%arrayidx2 = getelementptr inbounds i64, i64* %P, i64 1
|
||||
store volatile i64 %v, i64* %arrayidx2
|
||||
%arrayidx3 = getelementptr inbounds i64, i64* %P, i64 4
|
||||
store volatile i64 %v, i64* %arrayidx3
|
||||
ret i64 %v
|
||||
}
|
||||
|
||||
@p = common local_unnamed_addr global [100 x i32] zeroinitializer, align 4
|
||||
|
||||
define void @store_i32_stw_stw8(i32 signext %m, i32 signext %n) {
|
||||
entry:
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK-LABEL: store_i32_stw_stw8:%bb.0
|
||||
; CHECK: Cluster ld/st SU([[SU5:[0-9]+]]) - SU([[SU8:[0-9]+]])
|
||||
; CHECK: SU([[SU5]]): STW8 %{{[0-9]+}}:g8rc, 24
|
||||
; CHECK: SU([[SU8]]): STW %{{[0-9]+}}:gprc, 20
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK-LABEL: store_i32_stw_stw8:%bb.0
|
||||
; CHECK: Cluster ld/st SU([[SU5:[0-9]+]]) - SU([[SU6:[0-9]+]])
|
||||
; CHECK: SU([[SU5]]): STW8 renamable $x{{[0-9]+}}, 24
|
||||
; CHECK: SU([[SU6]]): STW renamable $r{{[0-9]+}}, 20
|
||||
store i32 9, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @p, i64 0, i64 6), align 4
|
||||
store i32 %n, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @p, i64 0, i64 7), align 4
|
||||
%add = add nsw i32 %n, %m
|
||||
store i32 %add, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @p, i64 0, i64 5), align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @store_i32_stw8(i32 signext %m, i32 signext %n) {
|
||||
entry:
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK-LABEL: store_i32_stw8:%bb.0
|
||||
; CHECK: Cluster ld/st SU([[SU4:[0-9]+]]) - SU([[SU5:[0-9]+]])
|
||||
; CHECK: SU([[SU4]]): STW8 %{{[0-9]+}}:g8rc, 24
|
||||
; CHECK: SU([[SU5]]): STW8 %{{[0-9]+}}:g8rc, 28
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK-LABEL: store_i32_stw8:%bb.0
|
||||
; CHECK: Cluster ld/st SU([[SU3:[0-9]+]]) - SU([[SU4:[0-9]+]])
|
||||
; CHECK: SU([[SU3]]): STW8 renamable $x{{[0-9]+}}, 24
|
||||
; CHECK: SU([[SU4]]): STW8 renamable $x{{[0-9]+}}, 28
|
||||
store i32 9, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @p, i64 0, i64 6), align 4
|
||||
store i32 %n, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @p, i64 0, i64 7), align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @bar(i64*)
|
||||
|
||||
define void @store_frame_index(i32 %a, i32 %b) {
|
||||
entry:
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK-LABEL: store_frame_index:%bb.0
|
||||
; CHECK: Cluster ld/st SU([[SU2:[0-9]+]]) - SU([[SU3:[0-9]+]])
|
||||
; CHECK: SU([[SU2]]): STD %{{[0-9]+}}:g8rc, 0, %stack.0.buf
|
||||
; CHECK: SU([[SU3]]): STD %{{[0-9]+}}:g8rc, 8, %stack.0.buf
|
||||
%buf = alloca [8 x i64], align 8
|
||||
%0 = bitcast [8 x i64]* %buf to i8*
|
||||
%conv = zext i32 %a to i64
|
||||
%arrayidx = getelementptr inbounds [8 x i64], [8 x i64]* %buf, i64 0, i64 0
|
||||
store i64 %conv, i64* %arrayidx, align 8
|
||||
%conv1 = zext i32 %b to i64
|
||||
%arrayidx2 = getelementptr inbounds [8 x i64], [8 x i64]* %buf, i64 0, i64 1
|
||||
store i64 %conv1, i64* %arrayidx2, align 8
|
||||
call void @bar(i64* nonnull %arrayidx)
|
||||
ret void
|
||||
}
|
||||
@ -104,15 +104,15 @@ define dso_local signext i32 @X2IsCallerSaved(i32 signext %a, i32 signext %b, i3
|
||||
; CHECK-P9-NOT: .localentry
|
||||
; CHECK-ALL: # %bb.0: # %entry
|
||||
; CHECK-S-NEXT: std r29, -24(r1) # 8-byte Folded Spill
|
||||
; CHECK-S-NEXT: std r30, -16(r1) # 8-byte Folded Spill
|
||||
; CHECK-S-NEXT: add r11, r4, r3
|
||||
; CHECK-S-NEXT: sub r29, r8, r9
|
||||
; CHECK-S-NEXT: add r9, r10, r9
|
||||
; CHECK-S-NEXT: sub r10, r10, r3
|
||||
; CHECK-S-NEXT: mullw r3, r4, r3
|
||||
; CHECK-S-NEXT: sub r12, r4, r5
|
||||
; CHECK-S-NEXT: add r0, r6, r5
|
||||
; CHECK-S-NEXT: sub r2, r6, r7
|
||||
; CHECK-S-NEXT: std r30, -16(r1) # 8-byte Folded Spill
|
||||
; CHECK-S-NEXT: mullw r3, r4, r3
|
||||
; CHECK-S-NEXT: add r30, r8, r7
|
||||
; CHECK-S-NEXT: mullw r3, r3, r11
|
||||
; CHECK-S-NEXT: mullw r3, r3, r5
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user