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[AMDGPU] fix LDS f32 intrinsics
- using qualified pointer addrspace in intrinsics class to avoid .f32 mangling - changed too common atomic mangling to ds - added missing intrinsics to AMDGPUTTIImpl::getTgtMemIntrinsic Reviewed by: b-sumner Differential Revision: https://reviews.llvm.org/D42383 llvm-svn: 323516
This commit is contained in:
Daniil Fukalov
parent
22e0ea0640
commit
28862346c2
@ -295,10 +295,10 @@ class AMDGPUAtomicIncIntrin : Intrinsic<[llvm_anyint_ty],
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def int_amdgcn_atomic_inc : AMDGPUAtomicIncIntrin;
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def int_amdgcn_atomic_dec : AMDGPUAtomicIncIntrin;
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class AMDGPUAtomicF32Intrin<string clang_builtin> :
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class AMDGPULDSF32Intrin<string clang_builtin> :
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GCCBuiltin<clang_builtin>,
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Intrinsic<[llvm_float_ty],
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[LLVMAnyPointerType<llvm_float_ty>,
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[LLVMQualPointerType<llvm_float_ty, 3>,
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llvm_float_ty,
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llvm_i32_ty, // ordering
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llvm_i32_ty, // scope
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@ -306,9 +306,9 @@ class AMDGPUAtomicF32Intrin<string clang_builtin> :
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[IntrArgMemOnly, NoCapture<0>]
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>;
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def int_amdgcn_atomic_fadd : AMDGPUAtomicF32Intrin<"__builtin_amdgcn_ds_fadd">;
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def int_amdgcn_atomic_fmin : AMDGPUAtomicF32Intrin<"__builtin_amdgcn_ds_fmin">;
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def int_amdgcn_atomic_fmax : AMDGPUAtomicF32Intrin<"__builtin_amdgcn_ds_fmax">;
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def int_amdgcn_ds_fadd : AMDGPULDSF32Intrin<"__builtin_amdgcn_ds_fadd">;
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def int_amdgcn_ds_fmin : AMDGPULDSF32Intrin<"__builtin_amdgcn_ds_fmin">;
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def int_amdgcn_ds_fmax : AMDGPULDSF32Intrin<"__builtin_amdgcn_ds_fmax">;
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class AMDGPUImageLoad<bit NoMem = 0> : Intrinsic <
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[llvm_anyfloat_ty], // vdata(VGPR)
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@ -292,7 +292,10 @@ bool AMDGPUTTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst,
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MemIntrinsicInfo &Info) const {
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switch (Inst->getIntrinsicID()) {
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case Intrinsic::amdgcn_atomic_inc:
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case Intrinsic::amdgcn_atomic_dec: {
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case Intrinsic::amdgcn_atomic_dec:
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case Intrinsic::amdgcn_ds_fadd:
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case Intrinsic::amdgcn_ds_fmin:
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case Intrinsic::amdgcn_ds_fmax: {
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auto *Ordering = dyn_cast<ConstantInt>(Inst->getArgOperand(2));
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auto *Volatile = dyn_cast<ConstantInt>(Inst->getArgOperand(4));
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if (!Ordering || !Volatile)
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@ -475,9 +478,9 @@ static bool isIntrinsicSourceOfDivergence(const IntrinsicInst *I) {
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case Intrinsic::r600_read_tidig_z:
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case Intrinsic::amdgcn_atomic_inc:
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case Intrinsic::amdgcn_atomic_dec:
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case Intrinsic::amdgcn_atomic_fadd:
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case Intrinsic::amdgcn_atomic_fmin:
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case Intrinsic::amdgcn_atomic_fmax:
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case Intrinsic::amdgcn_ds_fadd:
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case Intrinsic::amdgcn_ds_fmin:
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case Intrinsic::amdgcn_ds_fmax:
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case Intrinsic::amdgcn_image_atomic_swap:
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case Intrinsic::amdgcn_image_atomic_add:
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case Intrinsic::amdgcn_image_atomic_sub:
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@ -566,9 +566,9 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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switch (IntrID) {
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case Intrinsic::amdgcn_atomic_inc:
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case Intrinsic::amdgcn_atomic_dec:
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case Intrinsic::amdgcn_atomic_fadd:
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case Intrinsic::amdgcn_atomic_fmin:
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case Intrinsic::amdgcn_atomic_fmax: {
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case Intrinsic::amdgcn_ds_fadd:
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case Intrinsic::amdgcn_ds_fmin:
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case Intrinsic::amdgcn_ds_fmax: {
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Info.opc = ISD::INTRINSIC_W_CHAIN;
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Info.memVT = MVT::getVT(CI.getType());
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Info.ptrVal = CI.getOperand(0);
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@ -807,9 +807,9 @@ bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II,
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switch (II->getIntrinsicID()) {
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case Intrinsic::amdgcn_atomic_inc:
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case Intrinsic::amdgcn_atomic_dec:
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case Intrinsic::amdgcn_atomic_fadd:
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case Intrinsic::amdgcn_atomic_fmin:
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case Intrinsic::amdgcn_atomic_fmax: {
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case Intrinsic::amdgcn_ds_fadd:
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case Intrinsic::amdgcn_ds_fmin:
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case Intrinsic::amdgcn_ds_fmax: {
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Value *Ptr = II->getArgOperand(0);
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AccessTy = II->getType();
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Ops.push_back(Ptr);
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@ -4827,9 +4827,9 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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switch (IntrID) {
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case Intrinsic::amdgcn_atomic_inc:
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case Intrinsic::amdgcn_atomic_dec:
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case Intrinsic::amdgcn_atomic_fadd:
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case Intrinsic::amdgcn_atomic_fmin:
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case Intrinsic::amdgcn_atomic_fmax: {
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case Intrinsic::amdgcn_ds_fadd:
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case Intrinsic::amdgcn_ds_fmin:
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case Intrinsic::amdgcn_ds_fmax: {
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MemSDNode *M = cast<MemSDNode>(Op);
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unsigned Opc;
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switch (IntrID) {
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@ -4839,13 +4839,13 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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case Intrinsic::amdgcn_atomic_dec:
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Opc = AMDGPUISD::ATOMIC_DEC;
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break;
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case Intrinsic::amdgcn_atomic_fadd:
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case Intrinsic::amdgcn_ds_fadd:
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Opc = AMDGPUISD::ATOMIC_LOAD_FADD;
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break;
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case Intrinsic::amdgcn_atomic_fmin:
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case Intrinsic::amdgcn_ds_fmin:
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Opc = AMDGPUISD::ATOMIC_LOAD_FMIN;
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break;
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case Intrinsic::amdgcn_atomic_fmax:
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case Intrinsic::amdgcn_ds_fmax:
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Opc = AMDGPUISD::ATOMIC_LOAD_FMAX;
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break;
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default:
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@ -261,9 +261,9 @@ bool InferAddressSpaces::rewriteIntrinsicOperands(IntrinsicInst *II,
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switch (II->getIntrinsicID()) {
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case Intrinsic::amdgcn_atomic_inc:
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case Intrinsic::amdgcn_atomic_dec:
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case Intrinsic::amdgcn_atomic_fadd:
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case Intrinsic::amdgcn_atomic_fmin:
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case Intrinsic::amdgcn_atomic_fmax: {
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case Intrinsic::amdgcn_ds_fadd:
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case Intrinsic::amdgcn_ds_fmin:
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case Intrinsic::amdgcn_ds_fmax: {
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const ConstantInt *IsVolatile = dyn_cast<ConstantInt>(II->getArgOperand(4));
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if (!IsVolatile || !IsVolatile->isZero())
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return false;
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@ -292,9 +292,9 @@ void InferAddressSpaces::collectRewritableIntrinsicOperands(
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case Intrinsic::objectsize:
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case Intrinsic::amdgcn_atomic_inc:
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case Intrinsic::amdgcn_atomic_dec:
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case Intrinsic::amdgcn_atomic_fadd:
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case Intrinsic::amdgcn_atomic_fmin:
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case Intrinsic::amdgcn_atomic_fmax:
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case Intrinsic::amdgcn_ds_fadd:
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case Intrinsic::amdgcn_ds_fmin:
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case Intrinsic::amdgcn_ds_fmax:
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appendsFlatAddressExpressionToPostorderStack(II->getArgOperand(0),
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PostorderStack, Visited);
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break;
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@ -1,11 +1,11 @@
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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declare float @llvm.amdgcn.atomic.fadd.f32(float addrspace(3)* nocapture, float, i32, i32, i1)
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declare float @llvm.amdgcn.atomic.fmin.f32(float addrspace(3)* nocapture, float, i32, i32, i1)
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declare float @llvm.amdgcn.atomic.fmax.f32(float addrspace(3)* nocapture, float, i32, i32, i1)
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declare float @llvm.amdgcn.ds.fadd(float addrspace(3)* nocapture, float, i32, i32, i1)
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declare float @llvm.amdgcn.ds.fmin(float addrspace(3)* nocapture, float, i32, i32, i1)
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declare float @llvm.amdgcn.ds.fmax(float addrspace(3)* nocapture, float, i32, i32, i1)
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; GCN-LABEL: {{^}}lds_atomic_fadd_f32:
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; GCN-LABEL: {{^}}lds_ds_fadd:
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; VI-DAG: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-DAG: v_mov_b32_e32 [[V0:v[0-9]+]], 0x42280000
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@ -13,20 +13,20 @@ declare float @llvm.amdgcn.atomic.fmax.f32(float addrspace(3)* nocapture, float,
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; GCN: ds_add_f32 [[V3:v[0-9]+]], [[V0]] offset:64
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; GCN: s_waitcnt lgkmcnt(1)
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; GCN: ds_add_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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define amdgpu_kernel void @lds_atomic_fadd_f32(float addrspace(1)* %out, float addrspace(3)* %ptrf, i32 %idx) {
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define amdgpu_kernel void @lds_ds_fadd(float addrspace(1)* %out, float addrspace(3)* %ptrf, i32 %idx) {
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%idx.add = add nuw i32 %idx, 4
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%shl0 = shl i32 %idx.add, 3
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%shl1 = shl i32 %idx.add, 4
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%ptr0 = inttoptr i32 %shl0 to float addrspace(3)*
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%ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
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%a1 = call float @llvm.amdgcn.atomic.fadd.f32(float addrspace(3)* %ptr0, float 4.2e+1, i32 0, i32 0, i1 false)
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%a2 = call float @llvm.amdgcn.atomic.fadd.f32(float addrspace(3)* %ptr1, float 4.2e+1, i32 0, i32 0, i1 false)
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%a3 = call float @llvm.amdgcn.atomic.fadd.f32(float addrspace(3)* %ptrf, float %a1, i32 0, i32 0, i1 false)
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%a1 = call float @llvm.amdgcn.ds.fadd(float addrspace(3)* %ptr0, float 4.2e+1, i32 0, i32 0, i1 false)
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%a2 = call float @llvm.amdgcn.ds.fadd(float addrspace(3)* %ptr1, float 4.2e+1, i32 0, i32 0, i1 false)
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%a3 = call float @llvm.amdgcn.ds.fadd(float addrspace(3)* %ptrf, float %a1, i32 0, i32 0, i1 false)
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store float %a3, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_fmin_f32:
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; GCN-LABEL: {{^}}lds_ds_fmin:
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; VI-DAG: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-DAG: v_mov_b32_e32 [[V0:v[0-9]+]], 0x42280000
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@ -34,20 +34,20 @@ define amdgpu_kernel void @lds_atomic_fadd_f32(float addrspace(1)* %out, float a
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; GCN: ds_min_f32 [[V3:v[0-9]+]], [[V0]] offset:64
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; GCN: s_waitcnt lgkmcnt(1)
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; GCN: ds_min_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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define amdgpu_kernel void @lds_atomic_fmin_f32(float addrspace(1)* %out, float addrspace(3)* %ptrf, i32 %idx) {
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define amdgpu_kernel void @lds_ds_fmin(float addrspace(1)* %out, float addrspace(3)* %ptrf, i32 %idx) {
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%idx.add = add nuw i32 %idx, 4
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%shl0 = shl i32 %idx.add, 3
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%shl1 = shl i32 %idx.add, 4
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%ptr0 = inttoptr i32 %shl0 to float addrspace(3)*
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%ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
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%a1 = call float @llvm.amdgcn.atomic.fmin.f32(float addrspace(3)* %ptr0, float 4.2e+1, i32 0, i32 0, i1 false)
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%a2 = call float @llvm.amdgcn.atomic.fmin.f32(float addrspace(3)* %ptr1, float 4.2e+1, i32 0, i32 0, i1 false)
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%a3 = call float @llvm.amdgcn.atomic.fmin.f32(float addrspace(3)* %ptrf, float %a1, i32 0, i32 0, i1 false)
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%a1 = call float @llvm.amdgcn.ds.fmin(float addrspace(3)* %ptr0, float 4.2e+1, i32 0, i32 0, i1 false)
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%a2 = call float @llvm.amdgcn.ds.fmin(float addrspace(3)* %ptr1, float 4.2e+1, i32 0, i32 0, i1 false)
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%a3 = call float @llvm.amdgcn.ds.fmin(float addrspace(3)* %ptrf, float %a1, i32 0, i32 0, i1 false)
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store float %a3, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_fmax_f32:
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; GCN-LABEL: {{^}}lds_ds_fmax:
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; VI-DAG: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-DAG: v_mov_b32_e32 [[V0:v[0-9]+]], 0x42280000
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@ -55,15 +55,15 @@ define amdgpu_kernel void @lds_atomic_fmin_f32(float addrspace(1)* %out, float a
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; GCN: ds_max_f32 [[V3:v[0-9]+]], [[V0]] offset:64
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; GCN: s_waitcnt lgkmcnt(1)
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; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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define amdgpu_kernel void @lds_atomic_fmax_f32(float addrspace(1)* %out, float addrspace(3)* %ptrf, i32 %idx) {
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define amdgpu_kernel void @lds_ds_fmax(float addrspace(1)* %out, float addrspace(3)* %ptrf, i32 %idx) {
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%idx.add = add nuw i32 %idx, 4
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%shl0 = shl i32 %idx.add, 3
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%shl1 = shl i32 %idx.add, 4
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%ptr0 = inttoptr i32 %shl0 to float addrspace(3)*
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%ptr1 = inttoptr i32 %shl1 to float addrspace(3)*
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%a1 = call float @llvm.amdgcn.atomic.fmax.f32(float addrspace(3)* %ptr0, float 4.2e+1, i32 0, i32 0, i1 false)
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%a2 = call float @llvm.amdgcn.atomic.fmax.f32(float addrspace(3)* %ptr1, float 4.2e+1, i32 0, i32 0, i1 false)
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%a3 = call float @llvm.amdgcn.atomic.fmax.f32(float addrspace(3)* %ptrf, float %a1, i32 0, i32 0, i1 false)
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%a1 = call float @llvm.amdgcn.ds.fmax(float addrspace(3)* %ptr0, float 4.2e+1, i32 0, i32 0, i1 false)
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%a2 = call float @llvm.amdgcn.ds.fmax(float addrspace(3)* %ptr1, float 4.2e+1, i32 0, i32 0, i1 false)
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%a3 = call float @llvm.amdgcn.ds.fmax(float addrspace(3)* %ptrf, float %a1, i32 0, i32 0, i1 false)
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store float %a3, float addrspace(1)* %out
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ret void
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}
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