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[RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates.
Summary: Add R_RISCV_RELAX relocation to all possible relax candidates and update corresponding testcase. Reviewers: asb, apazos Differential Revision: https://reviews.llvm.org/D46677 llvm-svn: 351723
This commit is contained in:
Kito Cheng
parent
e3d6fdcccf
commit
28868a45d5
@ -204,6 +204,7 @@ unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
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const MCExpr *Expr = MO.getExpr();
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MCExpr::ExprKind Kind = Expr->getKind();
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RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid;
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bool RelaxCandidate = false;
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if (Kind == MCExpr::Target) {
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const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
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@ -218,9 +219,11 @@ unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
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FixupKind = RISCV::fixup_riscv_lo12_s;
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else
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llvm_unreachable("VK_RISCV_LO used with unexpected instruction format");
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RelaxCandidate = true;
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break;
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case RISCVMCExpr::VK_RISCV_HI:
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FixupKind = RISCV::fixup_riscv_hi20;
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RelaxCandidate = true;
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break;
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case RISCVMCExpr::VK_RISCV_PCREL_LO:
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if (MIFrm == RISCVII::InstFormatI)
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@ -230,12 +233,15 @@ unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
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else
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llvm_unreachable(
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"VK_RISCV_PCREL_LO used with unexpected instruction format");
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RelaxCandidate = true;
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break;
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case RISCVMCExpr::VK_RISCV_PCREL_HI:
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FixupKind = RISCV::fixup_riscv_pcrel_hi20;
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RelaxCandidate = true;
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break;
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case RISCVMCExpr::VK_RISCV_CALL:
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FixupKind = RISCV::fixup_riscv_call;
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RelaxCandidate = true;
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break;
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}
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} else if (Kind == MCExpr::SymbolRef &&
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@ -257,13 +263,15 @@ unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
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MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
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++MCNumFixups;
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if (EnableRelax) {
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if (FixupKind == RISCV::fixup_riscv_call) {
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Fixups.push_back(
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MCFixup::create(0, Expr, MCFixupKind(RISCV::fixup_riscv_relax),
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MI.getLoc()));
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++MCNumFixups;
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}
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// Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is
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// enabled and the current fixup will result in a relocation that may be
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// relaxed.
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if (EnableRelax && RelaxCandidate) {
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const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
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Fixups.push_back(
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MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax),
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MI.getLoc()));
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++MCNumFixups;
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}
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return 0;
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@ -18,9 +18,58 @@ call foo
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# NORELAX-RELOC: R_RISCV_CALL foo 0x0
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# NORELAX-RELOC-NOT: R_RISCV_RELAX
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# RELAX-RELOC: R_RISCV_CALL foo 0x0
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# RELAX-RELOC: R_RISCV_RELAX foo 0x0
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# RELAX-RELOC: R_RISCV_RELAX - 0x0
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# RELAX-FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_call
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# RELAX-FIXUP: fixup B - offset: 0, value: foo, kind: fixup_riscv_relax
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# RELAX-FIXUP: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
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beq s1, s1, .L1
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# RELAX-RELOC: R_RISCV_BRANCH .L1 0x0
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# RELAX-FIXUP: fixup A - offset: 0, value: .L1, kind: fixup_riscv_branch
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# RELAX-FIXUP-NOT: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
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lui t1, %hi(foo)
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# NORELAX-RELOC: R_RISCV_HI20 foo 0x0
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# NORELAX-RELOC-NOT: R_RISCV_RELAX
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# RELOC: R_RISCV_HI20 foo 0x0
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# RELAX-RELOC: R_RISCV_RELAX - 0x0
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# RELAX-FIXUP: fixup A - offset: 0, value: %hi(foo), kind: fixup_riscv_hi20
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# RELAX-FIXUP: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
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addi t1, t1, %lo(foo)
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# NORELAX-RELOC: R_RISCV_LO12_I foo 0x0
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# NORELAX-RELOC-NOT: R_RISCV_RELAX
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# RELOC: R_RISCV_LO12_I foo 0x0
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# RELAX-RELOC: R_RISCV_RELAX - 0x0
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# RELAX-FIXUP: fixup A - offset: 0, value: %lo(foo), kind: fixup_riscv_lo12_i
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# RELAX-FIXUP: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
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sb t1, %lo(foo)(a2)
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# NORELAX-RELOC: R_RISCV_LO12_S foo 0x0
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# NORELAX-RELOC-NOT: R_RISCV_RELAX
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# RELOC: R_RISCV_LO12_S foo 0x0
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# RELAX-RELOC: R_RISCV_RELAX - 0x0
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# RELAX-FIXUP: fixup A - offset: 0, value: %lo(foo), kind: fixup_riscv_lo12_s
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# RELAX-FIXUP: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
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auipc t1, %pcrel_hi(foo)
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# NORELAX-RELOC: R_RISCV_PCREL_HI20 foo 0x0
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# NORELAX-RELOC-NOT: R_RISCV_RELAX
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# RELOC: R_RISCV_PCREL_HI20 foo 0x0
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# RELAX-RELOC: R_RISCV_RELAX - 0x0
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# RELAX-FIXUP: fixup A - offset: 0, value: %pcrel_hi(foo), kind: fixup_riscv_pcrel_hi20
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# RELAX-FIXUP: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
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addi t1, t1, %pcrel_lo(foo)
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# NORELAX-RELOC: R_RISCV_PCREL_LO12_I foo 0x0
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# NORELAX-RELOC-NOT: R_RISCV_RELAX
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# RELOC: R_RISCV_PCREL_LO12_I foo 0x0
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# RELAX-RELOC: R_RISCV_RELAX - 0x0
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# RELAX-FIXUP: fixup A - offset: 0, value: %pcrel_lo(foo), kind: fixup_riscv_pcrel_lo12_i
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# RELAX-FIXUP: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
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sb t1, %pcrel_lo(foo)(a2)
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# NORELAX-RELOC: R_RISCV_PCREL_LO12_S foo 0x0
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# NORELAX-RELOC-NOT: R_RISCV_RELAX
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# RELOC: R_RISCV_PCREL_LO12_S foo 0x0
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# RELAX-RELOC: R_RISCV_RELAX - 0x0
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# RELAX-FIXUP: fixup A - offset: 0, value: %pcrel_lo(foo), kind: fixup_riscv_pcrel_lo12_s
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# RELAX-FIXUP: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
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@ -21,7 +21,7 @@
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# CHECK-INST: call foo
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# CHECK-RELOC: R_RISCV_CALL foo 0x0
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# CHECK-RELOC-NOT: R_RISCV_RELAX foo 0x0
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# CHECK-RELOC-NOT: R_RISCV_RELAX - 0x0
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call foo
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# CHECK-INST: addi s0, sp, 1020
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@ -36,7 +36,7 @@ addi s0, sp, 1020
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# CHECK-INST: .option relax
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# CHECK-INST: call bar
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# CHECK-RELOC-NEXT: R_RISCV_CALL bar 0x0
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# CHECK-RELOC-NEXT: R_RISCV_RELAX bar 0x0
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# CHECK-RELOC-NEXT: R_RISCV_RELAX - 0x0
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call bar
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.option push # Push relax=true, rvc=false
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@ -58,14 +58,14 @@ addi s0, sp, 1020
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# CHECK-INST: call bar
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# CHECK-RELOC-NEXT: R_RISCV_CALL bar 0x0
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# CHECK-RELOC-NEXT: R_RISCV_RELAX bar 0x0
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# CHECK-RELOC-NEXT: R_RISCV_RELAX - 0x0
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call bar
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.option pop # Pop relax=false, rvc=false
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# CHECK-INST: .option pop
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# CHECK-INST: call baz
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# CHECK-RELOC: R_RISCV_CALL baz 0x0
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# CHECK-RELOC-NOT: R_RISCV_RELAX baz 0x0
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# CHECK-RELOC-NOT: R_RISCV_RELAX - 0x0
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call baz
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# CHECK-INST: addi s0, sp, 1020
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@ -21,7 +21,7 @@
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# CHECK-INST: call foo
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# CHECK-RELOC: R_RISCV_CALL foo 0x0
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# CHECK-RELOC-NOT: R_RISCV_RELAX foo 0x0
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# CHECK-RELOC-NOT: R_RISCV_RELAX - 0x0
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call foo
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# CHECK-RELOC-NEXT: R_RISCV_ADD64
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@ -38,7 +38,7 @@ beq s1, s1, .L1
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# CHECK-INST: call bar
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# CHECK-RELOC-NEXT: R_RISCV_CALL bar 0x0
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# CHECK-RELOC-NEXT: R_RISCV_RELAX bar 0x0
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# CHECK-RELOC-NEXT: R_RISCV_RELAX - 0x0
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call bar
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# CHECK-RELOC-NEXT: R_RISCV_ADD64
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@ -54,7 +54,7 @@ beq s1, s1, .L1
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# CHECK-INST: call baz
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# CHECK-RELOC-NEXT: R_RISCV_CALL baz 0x0
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# CHECK-RELOC-NOT: R_RISCV_RELAX baz 0x0
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# CHECK-RELOC-NOT: R_RISCV_RELAX - 0x0
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call baz
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# CHECK-RELOC-NEXT: R_RISCV_ADD64
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