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AMDGPU/GlobalISel: Select DS GWS intrinsics
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
cfc365cf6e
commit
28876d6a15
@ -1088,6 +1088,115 @@ bool AMDGPUInstructionSelector::selectDSOrderedIntrinsic(
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return Ret;
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}
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static unsigned gwsIntrinToOpcode(unsigned IntrID) {
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switch (IntrID) {
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case Intrinsic::amdgcn_ds_gws_init:
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return AMDGPU::DS_GWS_INIT;
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case Intrinsic::amdgcn_ds_gws_barrier:
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return AMDGPU::DS_GWS_BARRIER;
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case Intrinsic::amdgcn_ds_gws_sema_v:
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return AMDGPU::DS_GWS_SEMA_V;
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case Intrinsic::amdgcn_ds_gws_sema_br:
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return AMDGPU::DS_GWS_SEMA_BR;
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case Intrinsic::amdgcn_ds_gws_sema_p:
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return AMDGPU::DS_GWS_SEMA_P;
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case Intrinsic::amdgcn_ds_gws_sema_release_all:
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return AMDGPU::DS_GWS_SEMA_RELEASE_ALL;
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default:
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llvm_unreachable("not a gws intrinsic");
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}
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}
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bool AMDGPUInstructionSelector::selectDSGWSIntrinsic(MachineInstr &MI,
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Intrinsic::ID IID) const {
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if (IID == Intrinsic::amdgcn_ds_gws_sema_release_all &&
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!STI.hasGWSSemaReleaseAll())
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return false;
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// intrinsic ID, vsrc, offset
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const bool HasVSrc = MI.getNumOperands() == 3;
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assert(HasVSrc || MI.getNumOperands() == 2);
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Register BaseOffset = MI.getOperand(HasVSrc ? 2 : 1).getReg();
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const RegisterBank *OffsetRB = RBI.getRegBank(BaseOffset, *MRI, TRI);
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if (OffsetRB->getID() != AMDGPU::SGPRRegBankID)
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return false;
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MachineInstr *OffsetDef = getDefIgnoringCopies(BaseOffset, *MRI);
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assert(OffsetDef);
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unsigned ImmOffset;
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MachineBasicBlock *MBB = MI.getParent();
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const DebugLoc &DL = MI.getDebugLoc();
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MachineInstr *Readfirstlane = nullptr;
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// If we legalized the VGPR input, strip out the readfirstlane to analyze the
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// incoming offset, in case there's an add of a constant. We'll have to put it
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// back later.
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if (OffsetDef->getOpcode() == AMDGPU::V_READFIRSTLANE_B32) {
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Readfirstlane = OffsetDef;
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BaseOffset = OffsetDef->getOperand(1).getReg();
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OffsetDef = getDefIgnoringCopies(BaseOffset, *MRI);
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}
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if (OffsetDef->getOpcode() == AMDGPU::G_CONSTANT) {
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// If we have a constant offset, try to use the 0 in m0 as the base.
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// TODO: Look into changing the default m0 initialization value. If the
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// default -1 only set the low 16-bits, we could leave it as-is and add 1 to
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// the immediate offset.
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ImmOffset = OffsetDef->getOperand(1).getCImm()->getZExtValue();
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BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::S_MOV_B32), AMDGPU::M0)
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.addImm(0);
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} else {
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std::tie(BaseOffset, ImmOffset, OffsetDef)
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= AMDGPU::getBaseWithConstantOffset(*MRI, BaseOffset);
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if (Readfirstlane) {
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// We have the constant offset now, so put the readfirstlane back on the
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// variable component.
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if (!RBI.constrainGenericRegister(BaseOffset, AMDGPU::VGPR_32RegClass, *MRI))
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return false;
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Readfirstlane->getOperand(1).setReg(BaseOffset);
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BaseOffset = Readfirstlane->getOperand(0).getReg();
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} else {
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if (!RBI.constrainGenericRegister(BaseOffset,
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AMDGPU::SReg_32RegClass, *MRI))
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return false;
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}
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Register M0Base = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
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BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::S_LSHL_B32), M0Base)
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.addReg(BaseOffset)
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.addImm(16);
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BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
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.addReg(M0Base);
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}
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// The resource id offset is computed as (<isa opaque base> + M0[21:16] +
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// offset field) % 64. Some versions of the programming guide omit the m0
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// part, or claim it's from offset 0.
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auto MIB = BuildMI(*MBB, &MI, DL, TII.get(gwsIntrinToOpcode(IID)));
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if (HasVSrc) {
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Register VSrc = MI.getOperand(1).getReg();
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MIB.addReg(VSrc);
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if (!RBI.constrainGenericRegister(VSrc, AMDGPU::VGPR_32RegClass, *MRI))
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return false;
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}
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MIB.addImm(ImmOffset)
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.addImm(-1) // $gds
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.cloneMemRefs(MI);
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MI.eraseFromParent();
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return true;
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}
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bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
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MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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@ -1114,6 +1223,13 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
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case Intrinsic::amdgcn_ds_ordered_add:
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case Intrinsic::amdgcn_ds_ordered_swap:
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return selectDSOrderedIntrinsic(I, IntrinsicID);
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case Intrinsic::amdgcn_ds_gws_init:
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case Intrinsic::amdgcn_ds_gws_barrier:
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case Intrinsic::amdgcn_ds_gws_sema_v:
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case Intrinsic::amdgcn_ds_gws_sema_br:
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case Intrinsic::amdgcn_ds_gws_sema_p:
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case Intrinsic::amdgcn_ds_gws_sema_release_all:
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return selectDSGWSIntrinsic(I, IntrinsicID);
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default:
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return selectImpl(I, *CoverageInfo);
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}
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@ -101,6 +101,7 @@ private:
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bool selectStoreIntrinsic(MachineInstr &MI, bool IsFormat) const;
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bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
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bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
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bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
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int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
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@ -0,0 +1,9 @@
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; XUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.barrier.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.barrier.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.barrier.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.barrier.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.barrier.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.barrier.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.barrier.ll | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-GISEL %S/../llvm.amdgcn.ds.gws.barrier.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.barrier.ll | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-GISEL,GFX10 %S/../llvm.amdgcn.ds.gws.barrier.ll
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; Make sure the op is emitted bundled with a waitcnt with and without the retry loop, and the bundle is not removed by ExpandPostRAPseudos.
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; XUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=postrapseudos -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.barrier.ll | FileCheck -enable-var-scope -check-prefix=MIR %S/../llvm.amdgcn.ds.gws.barrier.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=postrapseudos -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.barrier.ll | FileCheck -enable-var-scope -check-prefix=MIR %S/../llvm.amdgcn.ds.gws.barrier.ll
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@ -0,0 +1,5 @@
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; XUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.init.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.init.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.init.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.init.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.init.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.init.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.init.ll | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-GISEL %S/../llvm.amdgcn.ds.gws.init.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.init.ll | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-GISEL %S/../llvm.amdgcn.ds.gws.init.ll
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@ -0,0 +1,5 @@
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.br.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.sema.br.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.br.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.sema.br.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.br.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.sema.br.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.br.ll | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %S/../llvm.amdgcn.ds.gws.sema.br.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.br.ll | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,GFX10 %S/../llvm.amdgcn.ds.gws.sema.br.ll
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@ -0,0 +1,8 @@
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; RUN: not llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR-GISEL %s
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.sema.release.all.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP,GFX8 %S/../llvm.amdgcn.ds.gws.sema.release.all.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %S/../llvm.amdgcn.ds.gws.sema.release.all.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,GFX10 %S/../llvm.amdgcn.ds.gws.sema.release.all.ll
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; GFX6ERR-GISEL: LLVM ERROR: cannot select: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.release.all), %{{[0-9]+}}:sgpr(s32) :: (store 4 into custom "GWSResource") (in function: gws_sema_release_all_offset0)
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@ -0,0 +1,5 @@
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.v.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.sema.v.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.v.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.sema.v.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.v.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP,GFX8 %S/../llvm.amdgcn.ds.gws.sema.v.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.v.ll | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %S/../llvm.amdgcn.ds.gws.sema.v.ll
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.v.ll | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,GFX10 %S/../llvm.amdgcn.ds.gws.sema.v.ll
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@ -1,8 +1,8 @@
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,GFX10 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-SDAG %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-SDAG,GFX10 %s
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; Make sure the op is emitted bundled with a waitcnt with and without the retry loop, and the bundle is not removed by ExpandPostRAPseudos.
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=postrapseudos -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=MIR %s
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@ -51,8 +51,13 @@ define amdgpu_kernel void @gws_barrier_offset63(i32 %val) #0 {
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; FIXME: Should be able to shift directly into m0
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; GCN-LABEL: {{^}}gws_barrier_sgpr_offset:
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; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}}
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; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
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; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
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; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16
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; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]
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; NOLOOP: ds_gws_barrier [[GWS_VAL]] gds{{$}}
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define amdgpu_kernel void @gws_barrier_sgpr_offset(i32 %val, i32 %offset) #0 {
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@ -63,8 +68,12 @@ define amdgpu_kernel void @gws_barrier_sgpr_offset(i32 %val, i32 %offset) #0 {
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; Variable offset in SGPR with constant add
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; GCN-LABEL: {{^}}gws_barrier_sgpr_offset_add1:
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; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}}
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; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
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; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
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; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16
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; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]
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; NOLOOP: ds_gws_barrier [[GWS_VAL]] offset:1 gds{{$}}
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define amdgpu_kernel void @gws_barrier_sgpr_offset_add1(i32 %val, i32 %offset.base) #0 {
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@ -76,8 +85,12 @@ define amdgpu_kernel void @gws_barrier_sgpr_offset_add1(i32 %val, i32 %offset.ba
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; GCN-LABEL: {{^}}gws_barrier_vgpr_offset:
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; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
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; NOLOOP-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
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; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
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; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
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; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
|
||||
; NOLOOP-GISEL-DAG: s_lshl_b32 m0, [[READLANE]], 16
|
||||
|
||||
; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], [[BAR_NUM]]
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; NOLOOP: ds_gws_barrier [[GWS_VAL]] gds{{$}}
|
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define amdgpu_kernel void @gws_barrier_vgpr_offset(i32 %val) #0 {
|
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@ -90,8 +103,12 @@ define amdgpu_kernel void @gws_barrier_vgpr_offset(i32 %val) #0 {
|
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; GCN-LABEL: {{^}}gws_barrier_vgpr_offset_add:
|
||||
; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
|
||||
; NOLOOP-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
|
||||
; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
|
||||
; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
|
||||
; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
|
||||
; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
|
||||
; NOLOOP-GISEL-DAG: s_lshl_b32 m0, [[READLANE]], 16
|
||||
|
||||
; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], [[BAR_NUM]]
|
||||
; NOLOOP: ds_gws_barrier [[GWS_VAL]] offset:3 gds{{$}}
|
||||
define amdgpu_kernel void @gws_barrier_vgpr_offset_add(i32 %val) #0 {
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-SDAG %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,NOLOOP-SDAG %s
|
||||
|
||||
; Minimum offset
|
||||
; GCN-LABEL: {{^}}gws_init_offset0:
|
||||
@ -47,8 +47,12 @@ define amdgpu_kernel void @gws_init_offset63(i32 %val) #0 {
|
||||
; FIXME: Should be able to shift directly into m0
|
||||
; GCN-LABEL: {{^}}gws_init_sgpr_offset:
|
||||
; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}}
|
||||
; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
|
||||
; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
|
||||
; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
|
||||
; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
|
||||
; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16
|
||||
|
||||
; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]
|
||||
; NOLOOP: ds_gws_init [[GWS_VAL]] gds{{$}}
|
||||
define amdgpu_kernel void @gws_init_sgpr_offset(i32 %val, i32 %offset) #0 {
|
||||
@ -59,8 +63,12 @@ define amdgpu_kernel void @gws_init_sgpr_offset(i32 %val, i32 %offset) #0 {
|
||||
; Variable offset in SGPR with constant add
|
||||
; GCN-LABEL: {{^}}gws_init_sgpr_offset_add1:
|
||||
; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}}
|
||||
; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
|
||||
; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
|
||||
; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
|
||||
; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
|
||||
; NOLOOP-GISEL-DAG: s_lshl_b32 m0, s[[OFFSET]], 16
|
||||
|
||||
; NOLOOP-DAG: v_mov_b32_e32 [[GWS_VAL:v[0-9]+]], s[[BAR_NUM]]
|
||||
; NOLOOP: ds_gws_init [[GWS_VAL]] offset:1 gds{{$}}
|
||||
define amdgpu_kernel void @gws_init_sgpr_offset_add1(i32 %val, i32 %offset.base) #0 {
|
||||
@ -72,8 +80,12 @@ define amdgpu_kernel void @gws_init_sgpr_offset_add1(i32 %val, i32 %offset.base)
|
||||
; GCN-LABEL: {{^}}gws_init_vgpr_offset:
|
||||
; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
|
||||
; NOLOOP-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
|
||||
; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
|
||||
; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
|
||||
; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
|
||||
; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
|
||||
; NOLOOP-GISEL-DAG: s_lshl_b32 m0, [[READLANE]], 16
|
||||
|
||||
; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
|
||||
; NOLOOP: ds_gws_init v0 gds{{$}}
|
||||
define amdgpu_kernel void @gws_init_vgpr_offset(i32 %val) #0 {
|
||||
@ -86,8 +98,12 @@ define amdgpu_kernel void @gws_init_vgpr_offset(i32 %val) #0 {
|
||||
; GCN-LABEL: {{^}}gws_init_vgpr_offset_add:
|
||||
; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
|
||||
; NOLOOP-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
|
||||
; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
|
||||
; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
|
||||
; NOLOOP-SDAG-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
|
||||
; NOLOOP-SDAG-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
|
||||
; NOLOOP-GISEL-DAG: s_lshl_b32 m0, [[READLANE]], 16
|
||||
|
||||
; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
|
||||
; NOLOOP: ds_gws_init v0 offset:3 gds{{$}}
|
||||
define amdgpu_kernel void @gws_init_vgpr_offset_add(i32 %val) #0 {
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user