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https://github.com/RPCS3/llvm-mirror.git
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[Hexagon] Handle selection between HVX vector predicates
Make sure that (select i1 q0 q1) is handled properly.
This commit is contained in:
Krzysztof Parzyszek
parent
77ffdb3e3c
commit
28d3c031c0
@ -477,6 +477,7 @@ private:
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SDValue LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxSelect(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxIntrinsic(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxMaskedOp(SDValue Op, SelectionDAG &DAG) const;
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@ -94,6 +94,7 @@ HexagonTargetLowering::initializeHVXLowering() {
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setOperationAction(ISD::MUL, T, Legal);
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setOperationAction(ISD::CTPOP, T, Legal);
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setOperationAction(ISD::CTLZ, T, Legal);
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setOperationAction(ISD::SELECT, T, Legal);
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setOperationAction(ISD::SPLAT_VECTOR, T, Legal);
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if (T != ByteV) {
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal);
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@ -211,6 +212,7 @@ HexagonTargetLowering::initializeHVXLowering() {
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setOperationAction(ISD::INSERT_VECTOR_ELT, BoolV, Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, BoolV, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, BoolV, Custom);
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setOperationAction(ISD::SELECT, BoolV, Custom);
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setOperationAction(ISD::AND, BoolV, Legal);
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setOperationAction(ISD::OR, BoolV, Legal);
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setOperationAction(ISD::XOR, BoolV, Legal);
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@ -1619,6 +1621,26 @@ HexagonTargetLowering::LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const {
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Op.getOperand(0));
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}
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SDValue
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HexagonTargetLowering::LowerHvxSelect(SDValue Op, SelectionDAG &DAG) const {
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MVT ResTy = ty(Op);
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if (ResTy.getVectorElementType() != MVT::i1)
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return Op;
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const SDLoc &dl(Op);
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unsigned HwLen = Subtarget.getVectorLength();
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unsigned VecLen = ResTy.getVectorNumElements();
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assert(HwLen % VecLen == 0);
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unsigned ElemSize = HwLen / VecLen;
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MVT VecTy = MVT::getVectorVT(MVT::getIntegerVT(ElemSize * 8), VecLen);
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SDValue S =
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DAG.getNode(ISD::SELECT, dl, VecTy, Op.getOperand(0),
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DAG.getNode(HexagonISD::Q2V, dl, VecTy, Op.getOperand(1)),
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DAG.getNode(HexagonISD::Q2V, dl, VecTy, Op.getOperand(2)));
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return DAG.getNode(HexagonISD::V2Q, dl, ResTy, S);
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}
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SDValue
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HexagonTargetLowering::LowerHvxShift(SDValue Op, SelectionDAG &DAG) const {
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if (SDValue S = getVectorShiftByInt(Op, DAG))
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@ -2031,6 +2053,7 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::SIGN_EXTEND: return LowerHvxSignExt(Op, DAG);
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case ISD::ZERO_EXTEND: return LowerHvxZeroExt(Op, DAG);
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case ISD::CTTZ: return LowerHvxCttz(Op, DAG);
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case ISD::SELECT: return LowerHvxSelect(Op, DAG);
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case ISD::SRA:
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case ISD::SHL:
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case ISD::SRL: return LowerHvxShift(Op, DAG);
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@ -2143,27 +2166,41 @@ HexagonTargetLowering::PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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SmallVector<SDValue, 4> Ops(N->ops().begin(), N->ops().end());
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switch (Opc) {
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case ISD::VSELECT: {
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// (vselect (xor x, qtrue), v0, v1) -> (vselect x, v1, v0)
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SDValue Cond = Op.getOperand(0);
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SDValue Cond = Ops[0];
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if (Cond->getOpcode() == ISD::XOR) {
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SDValue C0 = Cond.getOperand(0), C1 = Cond.getOperand(1);
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if (C1->getOpcode() == HexagonISD::QTRUE)
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return DAG.getNode(ISD::VSELECT, dl, ty(Op), C0,
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Op.getOperand(2), Op.getOperand(1));
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return DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, Ops[2], Ops[1]);
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}
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break;
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}
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case HexagonISD::V2Q:
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if (Ops[0].getOpcode() == ISD::SPLAT_VECTOR) {
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if (const auto *C = dyn_cast<ConstantSDNode>(Ops[0].getOperand(0)))
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return C->isNullValue() ? DAG.getNode(HexagonISD::QFALSE, dl, ty(Op))
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: DAG.getNode(HexagonISD::QTRUE, dl, ty(Op));
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}
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break;
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case HexagonISD::Q2V:
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if (Ops[0].getOpcode() == HexagonISD::QTRUE)
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return DAG.getNode(ISD::SPLAT_VECTOR, dl, ty(Op),
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DAG.getConstant(-1, dl, MVT::i32));
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if (Ops[0].getOpcode() == HexagonISD::QFALSE)
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return getZero(dl, ty(Op), DAG);
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break;
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case HexagonISD::VINSERTW0:
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if (isUndef(Op.getOperand(1)))
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return Op.getOperand(0);
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if (isUndef(Ops[1]))
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return Ops[0];;
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break;
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case HexagonISD::VROR: {
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SDValue Op0 = Op.getOperand(0);
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if (Op0.getOpcode() == HexagonISD::VROR) {
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SDValue Vec = Op0.getOperand(0);
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SDValue Rot0 = Op.getOperand(1), Rot1 = Op0.getOperand(1);
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if (Ops[0].getOpcode() == HexagonISD::VROR) {
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SDValue Vec = Ops[0].getOperand(0);
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SDValue Rot0 = Ops[1], Rot1 = Ops[0].getOperand(1);
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SDValue Rot = DAG.getNode(ISD::ADD, dl, ty(Rot0), {Rot0, Rot1});
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return DAG.getNode(HexagonISD::VROR, dl, ty(Op), {Vec, Rot});
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}
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@ -172,16 +172,19 @@ let Predicates = [UseHVX] in {
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}
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let Predicates = [UseHVX] in {
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def: Pat<(VecI8 vzero), (V6_vd0)>;
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def: Pat<(VecI16 vzero), (V6_vd0)>;
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def: Pat<(VecI32 vzero), (V6_vd0)>;
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def: Pat<(VecPI8 vzero), (PS_vdd0)>;
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def: Pat<(VecPI16 vzero), (PS_vdd0)>;
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def: Pat<(VecPI32 vzero), (PS_vdd0)>;
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let AddedComplexity = 100 in {
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// These should be preferred over a vsplat of 0.
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def: Pat<(VecI8 vzero), (V6_vd0)>;
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def: Pat<(VecI16 vzero), (V6_vd0)>;
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def: Pat<(VecI32 vzero), (V6_vd0)>;
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def: Pat<(VecPI8 vzero), (PS_vdd0)>;
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def: Pat<(VecPI16 vzero), (PS_vdd0)>;
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def: Pat<(VecPI32 vzero), (PS_vdd0)>;
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def: Pat<(concat_vectors (VecI8 vzero), (VecI8 vzero)), (PS_vdd0)>;
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def: Pat<(concat_vectors (VecI16 vzero), (VecI16 vzero)), (PS_vdd0)>;
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def: Pat<(concat_vectors (VecI32 vzero), (VecI32 vzero)), (PS_vdd0)>;
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def: Pat<(concat_vectors (VecI8 vzero), (VecI8 vzero)), (PS_vdd0)>;
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def: Pat<(concat_vectors (VecI16 vzero), (VecI16 vzero)), (PS_vdd0)>;
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def: Pat<(concat_vectors (VecI32 vzero), (VecI32 vzero)), (PS_vdd0)>;
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}
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def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),
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(Combinev HvxVR:$Vt, HvxVR:$Vs)>;
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40
test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll
Normal file
40
test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll
Normal file
@ -0,0 +1,40 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; REQUIRES: asserts
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; Check that this doesn't crash.
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; CHECK: vand
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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%s.0 = type { [4 x <32 x i32>] }
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declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1>, <32 x i32>, <32 x i32>) #0
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declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32) #0
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declare <64 x i32> @llvm.hexagon.V6.vdealvdd.128B(<32 x i32>, <32 x i32>, i32) #0
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declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #0
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; Function Attrs: nounwind
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define void @f0() local_unnamed_addr #1 {
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b0:
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%v0 = tail call <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32> undef, i32 16843009)
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%v1 = getelementptr inbounds %s.0, %s.0* null, i32 0, i32 0, i32 3
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br label %b1
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b1: ; preds = %b1, %b0
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%v2 = phi i32 [ 0, %b0 ], [ %v11, %b1 ]
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%v3 = and i32 %v2, 1
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%v4 = icmp eq i32 %v3, 0
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%v5 = select i1 %v4, <128 x i1> zeroinitializer, <128 x i1> %v0
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%v6 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1> %v5, <32 x i32> undef, <32 x i32> undef)
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%v7 = tail call <64 x i32> @llvm.hexagon.V6.vdealvdd.128B(<32 x i32> undef, <32 x i32> %v6, i32 -32)
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%v8 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v7)
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%v9 = tail call <64 x i32> @llvm.hexagon.V6.vdealvdd.128B(<32 x i32> undef, <32 x i32> %v8, i32 -32)
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%v10 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v9)
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store <32 x i32> %v10, <32 x i32>* %v1, align 128
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%v11 = add nuw nsw i32 %v2, 1
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br label %b1
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvx,+hvx-length128b" }
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237
test/CodeGen/Hexagon/autohvx/isel-select-q.ll
Normal file
237
test/CodeGen/Hexagon/autohvx/isel-select-q.ll
Normal file
@ -0,0 +1,237 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that selection (based on i1) between vector predicates works.
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define <128 x i8> @f0(<128 x i8> %a0, <128 x i8> %a1, <128 x i8> %a2, <128 x i8> %a3, i32 %a4) #0 {
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; CHECK-LABEL: f0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: q0 = vcmp.gt(v0.b,v1.b)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q1 = vcmp.gt(v1.b,v2.b)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = #-1
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = cmp.gt(r0,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vand(q1,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v2 = vand(q0,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (p0) v0 = v2
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q3 = vand(v0,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vmux(q3,v1,v3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = icmp sgt <128 x i8> %a0, %a1
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%v1 = icmp sgt <128 x i8> %a1, %a2
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%v2 = icmp sgt i32 %a4, 0
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%v3 = select i1 %v2, <128 x i1> %v0, <128 x i1> %v1
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%v4 = select <128 x i1> %v3, <128 x i8> %a1, <128 x i8> %a3
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ret <128 x i8> %v4
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}
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define <64 x i16> @f1(<64 x i16> %a0, <64 x i16> %a1, <64 x i16> %a2, <64 x i16> %a3, i32 %a4) #0 {
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; CHECK-LABEL: f1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: q0 = vcmp.gt(v0.h,v1.h)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q1 = vcmp.gt(v1.h,v2.h)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = #-1
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = cmp.gt(r0,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vand(q1,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v2 = vand(q0,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (p0) v0 = v2
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q3 = vand(v0,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vmux(q3,v1,v3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = icmp sgt <64 x i16> %a0, %a1
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%v1 = icmp sgt <64 x i16> %a1, %a2
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%v2 = icmp sgt i32 %a4, 0
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%v3 = select i1 %v2, <64 x i1> %v0, <64 x i1> %v1
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%v4 = select <64 x i1> %v3, <64 x i16> %a1, <64 x i16> %a3
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ret <64 x i16> %v4
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}
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define <32 x i32> @f2(<32 x i32> %a0, <32 x i32> %a1, <32 x i32> %a2, <32 x i32> %a3, i32 %a4) #0 {
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; CHECK-LABEL: f2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: q0 = vcmp.gt(v0.w,v1.w)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q1 = vcmp.gt(v1.w,v2.w)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = #-1
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = cmp.gt(r0,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vand(q1,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v2 = vand(q0,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (p0) v0 = v2
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q3 = vand(v0,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vmux(q3,v1,v3)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = icmp sgt <32 x i32> %a0, %a1
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%v1 = icmp sgt <32 x i32> %a1, %a2
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%v2 = icmp sgt i32 %a4, 0
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%v3 = select i1 %v2, <32 x i1> %v0, <32 x i1> %v1
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%v4 = select <32 x i1> %v3, <32 x i32> %a1, <32 x i32> %a3
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ret <32 x i32> %v4
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}
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; Selection of vector predicates first converts them into regular vectors.
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; Check that all-true and all-false bool vectors are optimized into splat(-1)
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; and vxor(v,v).
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define <128 x i8> @f3(<128 x i8> %a0, <128 x i8> %a1, i32 %a2) #0 {
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; CHECK-LABEL: f3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: {
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; CHECK-NEXT: r2 = #-1
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = cmp.gt(r0,#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v2 = vxor(v2,v2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v3 = vsplat(r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (p0) v2 = v3
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q0 = vand(v2,r2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0 = vmux(q0,v0,v1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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%v0 = insertelement <128 x i1> undef, i1 true, i32 0
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%v1 = shufflevector <128 x i1> %v0, <128 x i1> undef, <128 x i32> zeroinitializer
|
||||
%v2 = icmp sgt i32 %a2, 0
|
||||
%v3 = select i1 %v2, <128 x i1> %v1, <128 x i1> zeroinitializer
|
||||
%v4 = select <128 x i1> %v3, <128 x i8> %a0, <128 x i8> %a1
|
||||
ret <128 x i8> %v4
|
||||
}
|
||||
|
||||
define <64 x i16> @f4(<64 x i16> %a0, <64 x i16> %a1, i32 %a2) #0 {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: r2 = #-1
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: p0 = cmp.gt(r0,#0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v2 = vxor(v2,v2)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v3 = vsplat(r2)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: if (p0) v2 = v3
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: q0 = vand(v2,r2)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v0 = vmux(q0,v0,v1)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = insertelement <64 x i1> undef, i1 true, i32 0
|
||||
%v1 = shufflevector <64 x i1> %v0, <64 x i1> undef, <64 x i32> zeroinitializer
|
||||
%v2 = icmp sgt i32 %a2, 0
|
||||
%v3 = select i1 %v2, <64 x i1> %v1, <64 x i1> zeroinitializer
|
||||
%v4 = select <64 x i1> %v3, <64 x i16> %a0, <64 x i16> %a1
|
||||
ret <64 x i16> %v4
|
||||
}
|
||||
|
||||
define <32 x i32> @f5(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
|
||||
; CHECK-LABEL: f5:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: r2 = #-1
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: p0 = cmp.gt(r0,#0)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v2 = vxor(v2,v2)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v3 = vsplat(r2)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: if (p0) v2 = v3
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: q0 = vand(v2,r2)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: v0 = vmux(q0,v0,v1)
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: {
|
||||
; CHECK-NEXT: jumpr r31
|
||||
; CHECK-NEXT: }
|
||||
%v0 = insertelement <32 x i1> undef, i1 true, i32 0
|
||||
%v1 = shufflevector <32 x i1> %v0, <32 x i1> undef, <32 x i32> zeroinitializer
|
||||
%v2 = icmp sgt i32 %a2, 0
|
||||
%v3 = select i1 %v2, <32 x i1> %v1, <32 x i1> zeroinitializer
|
||||
%v4 = select <32 x i1> %v3, <32 x i32> %a0, <32 x i32> %a1
|
||||
ret <32 x i32> %v4
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvx,+hvx-length128b,-packets" }
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user