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AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC

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llvm-svn: 366118
This commit is contained in:
Matt Arsenault 2019-07-15 19:45:49 +00:00
parent 3fc29ae7e7
commit 28d489f925
2 changed files with 30 additions and 0 deletions
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4
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -116,6 +116,10 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
return RBI.constrainGenericRegister(DstReg, *RC, MRI);
}
// TODO: Should probably leave the copy and let copyPhysReg expand it.
if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), MRI))
return false;
BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
.addImm(0)
.addReg(SrcReg);

26
test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
View File

@ -242,3 +242,29 @@ body: |
bb.1:
...
---
name: copy_sgpr_s1_to_vcc_constrain
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; WAVE64-LABEL: name: copy_sgpr_s1_to_vcc_constrain
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]
; WAVE32-LABEL: name: copy_sgpr_s1_to_vcc_constrain
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s1) = G_TRUNC %0
%2:vcc(s1) = COPY %1
S_ENDPGM 0, implicit %2
...