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https://github.com/RPCS3/llvm-mirror.git
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P9: D-form vector load/store. Differential Revision: https://reviews.llvm.org/D33248
llvm-svn: 303780
This commit is contained in:
Zaara Syeda
parent
879361c40b
commit
28e46e17c2
@ -2379,8 +2379,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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// Load Vector Indexed
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def LXVX : X_XT6_RA5_RB5<31, 268, "lxvx" , vsrc,
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[(set v2f64:$XT, (load xoaddr:$src))]>;
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[(set v2f64:$XT, (load xaddr:$src))]>;
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// Load Vector (Left-justified) with Length
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def LXVL : XX1Form<31, 269, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
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"lxvl $XT, $src, $rB", IIC_LdStLoad,
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@ -2430,7 +2429,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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// Store Vector Indexed
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def STXVX : X_XS6_RA5_RB5<31, 396, "stxvx" , vsrc,
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[(store v2f64:$XT, xoaddr:$dst)]>;
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[(store v2f64:$XT, xaddr:$dst)]>;
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// Store Vector (Left-justified) with Length
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def STXVL : XX1Form<31, 397, (outs), (ins vsrc:$XT, memr:$dst, g8rc:$rB),
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@ -2498,21 +2497,38 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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(v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>;
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} // IsLittleEndian, HasP9Vector
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def : Pat<(v2f64 (load xoaddr:$src)), (LXVX xoaddr:$src)>;
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def : Pat<(v2i64 (load xoaddr:$src)), (LXVX xoaddr:$src)>;
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def : Pat<(v4f32 (load xoaddr:$src)), (LXVX xoaddr:$src)>;
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def : Pat<(v4i32 (load xoaddr:$src)), (LXVX xoaddr:$src)>;
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def : Pat<(v4i32 (int_ppc_vsx_lxvw4x xoaddr:$src)), (LXVX xoaddr:$src)>;
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def : Pat<(v2f64 (int_ppc_vsx_lxvd2x xoaddr:$src)), (LXVX xoaddr:$src)>;
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def : Pat<(store v2f64:$rS, xoaddr:$dst), (STXVX $rS, xoaddr:$dst)>;
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def : Pat<(store v2i64:$rS, xoaddr:$dst), (STXVX $rS, xoaddr:$dst)>;
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def : Pat<(store v4f32:$rS, xoaddr:$dst), (STXVX $rS, xoaddr:$dst)>;
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def : Pat<(store v4i32:$rS, xoaddr:$dst), (STXVX $rS, xoaddr:$dst)>;
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def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xoaddr:$dst),
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(STXVX $rS, xoaddr:$dst)>;
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def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst),
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(STXVX $rS, xoaddr:$dst)>;
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// D-Form Load/Store
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def : Pat<(v4i32 (load iaddr:$src)), (LXV memrix16:$src)>;
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def : Pat<(v4f32 (load iaddr:$src)), (LXV memrix16:$src)>;
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def : Pat<(v2i64 (load iaddr:$src)), (LXV memrix16:$src)>;
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def : Pat<(v2f64 (load iaddr:$src)), (LXV memrix16:$src)>;
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def : Pat<(v4i32 (int_ppc_vsx_lxvw4x iaddr:$src)), (LXV memrix16:$src)>;
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def : Pat<(v2f64 (int_ppc_vsx_lxvd2x iaddr:$src)), (LXV memrix16:$src)>;
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def : Pat<(store v4f32:$rS, iaddr:$dst), (STXV $rS, memrix16:$dst)>;
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def : Pat<(store v4i32:$rS, iaddr:$dst), (STXV $rS, memrix16:$dst)>;
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def : Pat<(store v2f64:$rS, iaddr:$dst), (STXV $rS, memrix16:$dst)>;
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def : Pat<(store v2i64:$rS, iaddr:$dst), (STXV $rS, memrix16:$dst)>;
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def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, iaddr:$dst),
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(STXV $rS, memrix16:$dst)>;
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def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, iaddr:$dst),
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(STXV $rS, memrix16:$dst)>;
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def : Pat<(v2f64 (load xaddr:$src)), (LXVX xaddr:$src)>;
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def : Pat<(v2i64 (load xaddr:$src)), (LXVX xaddr:$src)>;
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def : Pat<(v4f32 (load xaddr:$src)), (LXVX xaddr:$src)>;
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def : Pat<(v4i32 (load xaddr:$src)), (LXVX xaddr:$src)>;
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def : Pat<(v4i32 (int_ppc_vsx_lxvw4x xaddr:$src)), (LXVX xaddr:$src)>;
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def : Pat<(v2f64 (int_ppc_vsx_lxvd2x xaddr:$src)), (LXVX xaddr:$src)>;
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def : Pat<(store v2f64:$rS, xaddr:$dst), (STXVX $rS, xaddr:$dst)>;
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def : Pat<(store v2i64:$rS, xaddr:$dst), (STXVX $rS, xaddr:$dst)>;
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def : Pat<(store v4f32:$rS, xaddr:$dst), (STXVX $rS, xaddr:$dst)>;
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def : Pat<(store v4i32:$rS, xaddr:$dst), (STXVX $rS, xaddr:$dst)>;
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def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xaddr:$dst),
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(STXVX $rS, xaddr:$dst)>;
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def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xaddr:$dst),
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(STXVX $rS, xaddr:$dst)>;
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def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))),
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(v4i32 (LXVWSX xoaddr:$src))>;
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def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))),
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@ -869,9 +869,9 @@ entry:
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; P9LE-LABEL: fromDiffConstsi
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; P8BE-LABEL: fromDiffConstsi
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; P8LE-LABEL: fromDiffConstsi
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; P9BE: lxvx
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; P9BE: lxv
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; P9BE: blr
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; P9LE: lxvx
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; P9LE: lxv
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; P9LE: blr
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; P8BE: lxvw4x
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; P8BE: blr
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@ -899,9 +899,9 @@ entry:
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; P9LE-LABEL: fromDiffMemConsAi
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; P8BE-LABEL: fromDiffMemConsAi
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; P8LE-LABEL: fromDiffMemConsAi
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; P9BE: lxvx
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; P9BE: lxv
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; P9BE: blr
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; P9LE: lxvx
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; P9LE: lxv
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; P9LE: blr
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; P8BE: lxvw4x
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; P8BE: blr
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@ -929,12 +929,12 @@ entry:
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; P9LE-LABEL: fromDiffMemConsDi
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; P8BE-LABEL: fromDiffMemConsDi
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; P8LE-LABEL: fromDiffMemConsDi
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; P9BE: lxvx
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; P9BE: lxvx
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; P9BE: lxv
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; P9BE: lxv
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; P9BE: vperm
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; P9BE: blr
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; P9LE: lxvx
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; P9LE: lxvx
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; P9LE: lxv
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; P9LE: lxv
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; P9LE: vperm
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; P9LE: blr
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; P8BE: lxvw4x
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@ -1018,13 +1018,13 @@ entry:
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; P8BE-LABEL: fromDiffMemVarDi
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; P8LE-LABEL: fromDiffMemVarDi
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; P9BE: sldi {{r[0-9]+}}, r4, 2
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; P9BE-DAG: lxvx {{v[0-9]+}}, r3,
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; P9BE-DAG: lxvx
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; P9BE-DAG: lxv {{v[0-9]+}}
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; P9BE-DAG: lxv
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; P9BE: vperm
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; P9BE: blr
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; P9LE: sldi {{r[0-9]+}}, r4, 2
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; P9LE-DAG: lxvx {{v[0-9]+}}, r3,
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; P9LE-DAG: lxvx
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; P9LE-DAG: lxv {{v[0-9]+}}
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; P9LE-DAG: lxv
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; P9LE: vperm
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; P9LE: blr
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; P8BE: sldi {{r[0-9]+}}, r4, 2
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@ -1281,9 +1281,9 @@ entry:
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; P9LE-LABEL: fromDiffConstsConvftoi
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; P8BE-LABEL: fromDiffConstsConvftoi
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; P8LE-LABEL: fromDiffConstsConvftoi
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; P9BE: lxvx
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; P9BE: lxv
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; P9BE: blr
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; P9LE: lxvx
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; P9LE: lxv
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; P9LE: blr
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; P8BE: lxvw4x
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; P8BE: blr
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@ -1303,10 +1303,10 @@ entry:
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; P9LE-LABEL: fromDiffMemConsAConvftoi
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; P8BE-LABEL: fromDiffMemConsAConvftoi
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; P8LE-LABEL: fromDiffMemConsAConvftoi
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; P9BE: lxvx [[REG1:[vs0-9]+]], 0, r3
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; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3)
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; P9BE: xvcvspsxws v2, [[REG1]]
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; P9BE: blr
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; P9LE: lxvx [[REG1:[vs0-9]+]], 0, r3
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; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3)
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; P9LE: xvcvspsxws v2, [[REG1]]
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; P9LE: blr
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; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3
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@ -1341,13 +1341,13 @@ entry:
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; P9LE-LABEL: fromDiffMemConsDConvftoi
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; P8BE-LABEL: fromDiffMemConsDConvftoi
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; P8LE-LABEL: fromDiffMemConsDConvftoi
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; P9BE: lxvx
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; P9BE: lxvx
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; P9BE: lxv
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; P9BE: lxv
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; P9BE: vperm
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; P9BE: xvcvspsxws
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; P9BE: blr
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; P9LE: lxvx
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; P9LE: lxvx
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; P9LE: lxv
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; P9LE: lxv
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; P9LE: vperm
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; P9LE: xvcvspsxws
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; P9LE: blr
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@ -1557,9 +1557,9 @@ entry:
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; P9LE-LABEL: fromDiffConstsConvdtoi
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; P8BE-LABEL: fromDiffConstsConvdtoi
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; P8LE-LABEL: fromDiffConstsConvdtoi
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; P9BE: lxvx
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; P9BE: lxv
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; P9BE: blr
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; P9LE: lxvx
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; P9LE: lxv
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; P9LE: blr
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; P8BE: lxvw4x
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; P8BE: blr
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@ -1584,16 +1584,16 @@ entry:
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; P9LE-LABEL: fromDiffMemConsAConvdtoi
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; P8BE-LABEL: fromDiffMemConsAConvdtoi
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; P8LE-LABEL: fromDiffMemConsAConvdtoi
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; P9BE: lxvx [[REG1:[vs0-9]+]], 0, r3
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; P9BE: lxvx [[REG2:[vs0-9]+]], r3, r4
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; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3)
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; P9BE: lxv [[REG2:[vs0-9]+]], 16(r3)
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; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]]
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; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]]
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; P9BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
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; P9BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
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; P9BE: vmrgew v2, [[REG6]], [[REG5]]
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; P9BE: xvcvspsxws v2, v2
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; P9LE: lxvx [[REG1:[vs0-9]+]], 0, r3
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; P9LE: lxvx [[REG2:[vs0-9]+]], r3, r4
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; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3)
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; P9LE: lxv [[REG2:[vs0-9]+]], 16(r3)
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; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]]
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; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]]
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; P9LE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
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@ -2027,9 +2027,9 @@ entry:
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; P9LE-LABEL: fromDiffConstsui
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; P8BE-LABEL: fromDiffConstsui
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; P8LE-LABEL: fromDiffConstsui
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; P9BE: lxvx
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; P9BE: lxv
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; P9BE: blr
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; P9LE: lxvx
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; P9LE: lxv
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; P9LE: blr
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; P8BE: lxvw4x
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; P8BE: blr
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@ -2057,9 +2057,9 @@ entry:
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; P9LE-LABEL: fromDiffMemConsAui
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; P8BE-LABEL: fromDiffMemConsAui
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; P8LE-LABEL: fromDiffMemConsAui
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; P9BE: lxvx
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; P9BE: lxv
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; P9BE: blr
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; P9LE: lxvx
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; P9LE: lxv
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; P9LE: blr
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; P8BE: lxvw4x
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; P8BE: blr
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@ -2087,12 +2087,12 @@ entry:
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; P9LE-LABEL: fromDiffMemConsDui
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; P8BE-LABEL: fromDiffMemConsDui
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; P8LE-LABEL: fromDiffMemConsDui
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; P9BE: lxvx
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; P9BE: lxvx
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; P9BE: lxv
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; P9BE: lxv
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; P9BE: vperm
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; P9BE: blr
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; P9LE: lxvx
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; P9LE: lxvx
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; P9LE: lxv
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; P9LE: lxv
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; P9LE: vperm
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; P9LE: blr
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; P8BE: lxvw4x
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@ -2177,13 +2177,13 @@ entry:
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; P8BE-LABEL: fromDiffMemVarDui
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; P8LE-LABEL: fromDiffMemVarDui
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; P9BE-DAG: sldi {{r[0-9]+}}, r4, 2
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; P9BE-DAG: lxvx {{v[0-9]+}}, r3
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; P9BE-DAG: lxvx
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; P9BE-DAG: lxv {{v[0-9]+}}, -12(r3)
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; P9BE-DAG: lxv
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; P9BE: vperm
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; P9BE: blr
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; P9LE-DAG: sldi {{r[0-9]+}}, r4, 2
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; P9LE-DAG: lxvx {{v[0-9]+}}, r3
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; P9LE-DAG: lxvx
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; P9LE-DAG: lxv {{v[0-9]+}}, -12(r3)
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; P9LE-DAG: lxv
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; P9LE: vperm
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; P9LE: blr
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; P8BE-DAG: sldi {{r[0-9]+}}, r4, 2
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@ -2439,9 +2439,9 @@ entry:
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; P9LE-LABEL: fromDiffConstsConvftoui
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; P8BE-LABEL: fromDiffConstsConvftoui
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; P8LE-LABEL: fromDiffConstsConvftoui
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; P9BE: lxvx
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; P9BE: lxv
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; P9BE: blr
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; P9LE: lxvx
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; P9LE: lxv
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; P9LE: blr
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; P8BE: lxvw4x
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; P8BE: blr
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@ -2461,10 +2461,10 @@ entry:
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; P9LE-LABEL: fromDiffMemConsAConvftoui
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; P8BE-LABEL: fromDiffMemConsAConvftoui
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; P8LE-LABEL: fromDiffMemConsAConvftoui
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; P9BE: lxvx [[REG1:[vs0-9]+]], 0, r3
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; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3)
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; P9BE: xvcvspuxws v2, [[REG1]]
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; P9BE: blr
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; P9LE: lxvx [[REG1:[vs0-9]+]], 0, r3
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; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3)
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; P9LE: xvcvspuxws v2, [[REG1]]
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; P9LE: blr
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; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3
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@ -2499,13 +2499,13 @@ entry:
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; P9LE-LABEL: fromDiffMemConsDConvftoui
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; P8BE-LABEL: fromDiffMemConsDConvftoui
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; P8LE-LABEL: fromDiffMemConsDConvftoui
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; P9BE: lxvx
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; P9BE: lxvx
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; P9BE: lxv
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; P9BE: lxv
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; P9BE: vperm
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; P9BE: xvcvspuxws
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; P9BE: blr
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; P9LE: lxvx
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; P9LE: lxvx
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; P9LE: lxv
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; P9LE: lxv
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; P9LE: vperm
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; P9LE: xvcvspuxws
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; P9LE: blr
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@ -2715,9 +2715,9 @@ entry:
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; P9LE-LABEL: fromDiffConstsConvdtoui
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; P8BE-LABEL: fromDiffConstsConvdtoui
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; P8LE-LABEL: fromDiffConstsConvdtoui
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; P9BE: lxvx
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; P9BE: lxv
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; P9BE: blr
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; P9LE: lxvx
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; P9LE: lxv
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; P9LE: blr
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; P8BE: lxvw4x
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; P8BE: blr
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@ -2742,16 +2742,16 @@ entry:
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; P9LE-LABEL: fromDiffMemConsAConvdtoui
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; P8BE-LABEL: fromDiffMemConsAConvdtoui
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; P8LE-LABEL: fromDiffMemConsAConvdtoui
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; P9BE: lxvx [[REG1:[vs0-9]+]], 0, r3
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; P9BE: lxvx [[REG2:[vs0-9]+]], r3, r4
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; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3)
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; P9BE: lxv [[REG2:[vs0-9]+]], 16(r3)
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; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]]
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; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]]
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; P9BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
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; P9BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
|
||||
; P9BE: vmrgew v2, [[REG6]], [[REG5]]
|
||||
; P9BE: xvcvspuxws v2, v2
|
||||
; P9LE: lxvx [[REG1:[vs0-9]+]], 0, r3
|
||||
; P9LE: lxvx [[REG2:[vs0-9]+]], r3, r4
|
||||
; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3)
|
||||
; P9LE: lxv [[REG2:[vs0-9]+]], 16(r3)
|
||||
; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]]
|
||||
; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]]
|
||||
; P9LE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
|
||||
@ -3087,9 +3087,9 @@ entry:
|
||||
; P9LE-LABEL: spltConst1ll
|
||||
; P8BE-LABEL: spltConst1ll
|
||||
; P8LE-LABEL: spltConst1ll
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -3105,9 +3105,9 @@ entry:
|
||||
; P9LE-LABEL: spltConst16kll
|
||||
; P8BE-LABEL: spltConst16kll
|
||||
; P8LE-LABEL: spltConst16kll
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -3123,9 +3123,9 @@ entry:
|
||||
; P9LE-LABEL: spltConst32kll
|
||||
; P8BE-LABEL: spltConst32kll
|
||||
; P8LE-LABEL: spltConst32kll
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -3165,9 +3165,9 @@ entry:
|
||||
; P9LE-LABEL: fromDiffConstsll
|
||||
; P8BE-LABEL: fromDiffConstsll
|
||||
; P8LE-LABEL: fromDiffConstsll
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -3188,9 +3188,9 @@ entry:
|
||||
; P9LE-LABEL: fromDiffMemConsAll
|
||||
; P8BE-LABEL: fromDiffMemConsAll
|
||||
; P8LE-LABEL: fromDiffMemConsAll
|
||||
; P9BE: lxvx v2
|
||||
; P9BE: lxv v2
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx v2
|
||||
; P9LE: lxv v2
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x v2
|
||||
; P8BE: blr
|
||||
@ -3213,9 +3213,9 @@ entry:
|
||||
; P9LE-LABEL: fromDiffMemConsDll
|
||||
; P8BE-LABEL: fromDiffMemConsDll
|
||||
; P8LE-LABEL: fromDiffMemConsDll
|
||||
; P9BE: lxvx v2
|
||||
; P9BE: lxv v2
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: xxswapd v2
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
@ -3275,11 +3275,11 @@ entry:
|
||||
; P8BE-LABEL: fromDiffMemVarDll
|
||||
; P8LE-LABEL: fromDiffMemVarDll
|
||||
; P9BE: sldi
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: xxswapd v2
|
||||
; P9BE-NEXT: blr
|
||||
; P9LE: sldi
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: xxswapd v2
|
||||
; P9LE-NEXT: blr
|
||||
; P8BE: sldi
|
||||
@ -3422,9 +3422,9 @@ entry:
|
||||
; P9LE-LABEL: spltCnstConvftoll
|
||||
; P8BE-LABEL: spltCnstConvftoll
|
||||
; P8LE-LABEL: spltCnstConvftoll
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -3466,9 +3466,9 @@ entry:
|
||||
; P9LE-LABEL: fromDiffConstsConvftoll
|
||||
; P8BE-LABEL: fromDiffConstsConvftoll
|
||||
; P8LE-LABEL: fromDiffConstsConvftoll
|
||||
; P9BE: lxvx v2
|
||||
; P9BE: lxv v2
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx v2
|
||||
; P9LE: lxv v2
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x v2
|
||||
; P8BE: blr
|
||||
@ -3705,9 +3705,9 @@ entry:
|
||||
; P9LE-LABEL: spltCnstConvdtoll
|
||||
; P8BE-LABEL: spltCnstConvdtoll
|
||||
; P8LE-LABEL: spltCnstConvdtoll
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -3749,9 +3749,9 @@ entry:
|
||||
; P9LE-LABEL: fromDiffConstsConvdtoll
|
||||
; P8BE-LABEL: fromDiffConstsConvdtoll
|
||||
; P8LE-LABEL: fromDiffConstsConvdtoll
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -3770,10 +3770,10 @@ entry:
|
||||
; P9LE-LABEL: fromDiffMemConsAConvdtoll
|
||||
; P8BE-LABEL: fromDiffMemConsAConvdtoll
|
||||
; P8LE-LABEL: fromDiffMemConsAConvdtoll
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE-NEXT: xvcvdpsxds v2
|
||||
; P9BE-NEXT: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE-NEXT: xvcvdpsxds v2
|
||||
; P9LE-NEXT: blr
|
||||
; P8BE: lxvd2x
|
||||
@ -3801,11 +3801,11 @@ entry:
|
||||
; P9LE-LABEL: fromDiffMemConsDConvdtoll
|
||||
; P8BE-LABEL: fromDiffMemConsDConvdtoll
|
||||
; P8LE-LABEL: fromDiffMemConsDConvdtoll
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE-NEXT: xxswapd
|
||||
; P9BE-NEXT: xvcvdpsxds v2
|
||||
; P9BE-NEXT: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE-NEXT: xxswapd
|
||||
; P9LE-NEXT: xvcvdpsxds v2
|
||||
; P9LE-NEXT: blr
|
||||
@ -3876,12 +3876,12 @@ entry:
|
||||
; P8BE-LABEL: fromDiffMemVarDConvdtoll
|
||||
; P8LE-LABEL: fromDiffMemVarDConvdtoll
|
||||
; P9BE: sldi
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE-NEXT: xxswapd
|
||||
; P9BE-NEXT: xvcvdpsxds v2
|
||||
; P9BE-NEXT: blr
|
||||
; P9LE: sldi
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE-NEXT: xxswapd
|
||||
; P9LE-NEXT: xvcvdpsxds v2
|
||||
; P9LE-NEXT: blr
|
||||
@ -3991,9 +3991,9 @@ entry:
|
||||
; P9LE-LABEL: spltConst1ull
|
||||
; P8BE-LABEL: spltConst1ull
|
||||
; P8LE-LABEL: spltConst1ull
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -4009,9 +4009,9 @@ entry:
|
||||
; P9LE-LABEL: spltConst16kull
|
||||
; P8BE-LABEL: spltConst16kull
|
||||
; P8LE-LABEL: spltConst16kull
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -4027,9 +4027,9 @@ entry:
|
||||
; P9LE-LABEL: spltConst32kull
|
||||
; P8BE-LABEL: spltConst32kull
|
||||
; P8LE-LABEL: spltConst32kull
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -4069,9 +4069,9 @@ entry:
|
||||
; P9LE-LABEL: fromDiffConstsull
|
||||
; P8BE-LABEL: fromDiffConstsull
|
||||
; P8LE-LABEL: fromDiffConstsull
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -4092,9 +4092,9 @@ entry:
|
||||
; P9LE-LABEL: fromDiffMemConsAull
|
||||
; P8BE-LABEL: fromDiffMemConsAull
|
||||
; P8LE-LABEL: fromDiffMemConsAull
|
||||
; P9BE: lxvx v2
|
||||
; P9BE: lxv v2
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx v2
|
||||
; P9LE: lxv v2
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x v2
|
||||
; P8BE: blr
|
||||
@ -4117,9 +4117,9 @@ entry:
|
||||
; P9LE-LABEL: fromDiffMemConsDull
|
||||
; P8BE-LABEL: fromDiffMemConsDull
|
||||
; P8LE-LABEL: fromDiffMemConsDull
|
||||
; P9BE: lxvx v2
|
||||
; P9BE: lxv v2
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: xxswapd v2
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
@ -4179,11 +4179,11 @@ entry:
|
||||
; P8BE-LABEL: fromDiffMemVarDull
|
||||
; P8LE-LABEL: fromDiffMemVarDull
|
||||
; P9BE: sldi
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: xxswapd v2
|
||||
; P9BE-NEXT: blr
|
||||
; P9LE: sldi
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: xxswapd v2
|
||||
; P9LE-NEXT: blr
|
||||
; P8BE: sldi
|
||||
@ -4326,9 +4326,9 @@ entry:
|
||||
; P9LE-LABEL: spltCnstConvftoull
|
||||
; P8BE-LABEL: spltCnstConvftoull
|
||||
; P8LE-LABEL: spltCnstConvftoull
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -4370,9 +4370,9 @@ entry:
|
||||
; P9LE-LABEL: fromDiffConstsConvftoull
|
||||
; P8BE-LABEL: fromDiffConstsConvftoull
|
||||
; P8LE-LABEL: fromDiffConstsConvftoull
|
||||
; P9BE: lxvx v2
|
||||
; P9BE: lxv v2
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx v2
|
||||
; P9LE: lxv v2
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x v2
|
||||
; P8BE: blr
|
||||
@ -4609,9 +4609,9 @@ entry:
|
||||
; P9LE-LABEL: spltCnstConvdtoull
|
||||
; P8BE-LABEL: spltCnstConvdtoull
|
||||
; P8LE-LABEL: spltCnstConvdtoull
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -4653,9 +4653,9 @@ entry:
|
||||
; P9LE-LABEL: fromDiffConstsConvdtoull
|
||||
; P8BE-LABEL: fromDiffConstsConvdtoull
|
||||
; P8LE-LABEL: fromDiffConstsConvdtoull
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE: blr
|
||||
; P8BE: lxvd2x
|
||||
; P8BE: blr
|
||||
@ -4674,10 +4674,10 @@ entry:
|
||||
; P9LE-LABEL: fromDiffMemConsAConvdtoull
|
||||
; P8BE-LABEL: fromDiffMemConsAConvdtoull
|
||||
; P8LE-LABEL: fromDiffMemConsAConvdtoull
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE-NEXT: xvcvdpuxds v2
|
||||
; P9BE-NEXT: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE-NEXT: xvcvdpuxds v2
|
||||
; P9LE-NEXT: blr
|
||||
; P8BE: lxvd2x
|
||||
@ -4705,11 +4705,11 @@ entry:
|
||||
; P9LE-LABEL: fromDiffMemConsDConvdtoull
|
||||
; P8BE-LABEL: fromDiffMemConsDConvdtoull
|
||||
; P8LE-LABEL: fromDiffMemConsDConvdtoull
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE-NEXT: xxswapd
|
||||
; P9BE-NEXT: xvcvdpuxds v2
|
||||
; P9BE-NEXT: blr
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE-NEXT: xxswapd
|
||||
; P9LE-NEXT: xvcvdpuxds v2
|
||||
; P9LE-NEXT: blr
|
||||
@ -4780,12 +4780,12 @@ entry:
|
||||
; P8BE-LABEL: fromDiffMemVarDConvdtoull
|
||||
; P8LE-LABEL: fromDiffMemVarDConvdtoull
|
||||
; P9BE: sldi
|
||||
; P9BE: lxvx
|
||||
; P9BE: lxv
|
||||
; P9BE-NEXT: xxswapd
|
||||
; P9BE-NEXT: xvcvdpuxds v2
|
||||
; P9BE-NEXT: blr
|
||||
; P9LE: sldi
|
||||
; P9LE: lxvx
|
||||
; P9LE: lxv
|
||||
; P9LE-NEXT: xxswapd
|
||||
; P9LE-NEXT: xvcvdpuxds v2
|
||||
; P9LE-NEXT: blr
|
||||
|
||||
@ -972,10 +972,10 @@ define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) {
|
||||
entry:
|
||||
; CHECK-LABEL: insertVarF
|
||||
; CHECK: stxsspx 1,
|
||||
; CHECK: lxvx
|
||||
; CHECK: lxv
|
||||
; CHECK-BE-LABEL: insertVarF
|
||||
; CHECK-BE: stxsspx 1,
|
||||
; CHECK-BE: lxvx
|
||||
; CHECK-BE: lxv
|
||||
%vecins = insertelement <4 x float> %a, float %f, i32 %el
|
||||
ret <4 x float> %vecins
|
||||
}
|
||||
@ -983,10 +983,10 @@ define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) {
|
||||
entry:
|
||||
; CHECK-LABEL: insertVarI
|
||||
; CHECK: stwx
|
||||
; CHECK: lxvx
|
||||
; CHECK: lxv
|
||||
; CHECK-BE-LABEL: insertVarI
|
||||
; CHECK-BE: stwx
|
||||
; CHECK-BE: lxvx
|
||||
; CHECK-BE: lxv
|
||||
%vecins = insertelement <4 x i32> %a, i32 %i, i32 %el
|
||||
ret <4 x i32> %vecins
|
||||
}
|
||||
|
||||
@ -63,7 +63,7 @@ define <1 x i128> @v1i128_increment_by_one(<1 x i128> %a) nounwind {
|
||||
; FIXME: li [[R1:r[0-9]+]], 1
|
||||
; FIXME: li [[R2:r[0-9]+]], 0
|
||||
; FIXME: mtvsrdd [[V1:v[0-9]+]], [[R2]], [[R1]]
|
||||
; CHECK-P9: lxvx [[V1:v[0-9]+]]
|
||||
; CHECK-P9: lxv [[V1:v[0-9]+]]
|
||||
; CHECK-P9: vadduqm v2, v2, [[V1]]
|
||||
; CHECK-P9: blr
|
||||
|
||||
@ -207,7 +207,7 @@ define <1 x i128> @call_v1i128_increment_by_one() nounwind {
|
||||
; CHECK-LE: blr
|
||||
|
||||
; CHECK-P9-LABEL: @call_v1i128_increment_by_one
|
||||
; CHECK-P9: lxvx
|
||||
; CHECK-P9: lxv
|
||||
; CHECK-P9: bl v1i128_increment_by_one
|
||||
; CHECK-P9: blr
|
||||
|
||||
@ -237,8 +237,8 @@ define <1 x i128> @call_v1i128_increment_by_val() nounwind {
|
||||
; CHECK-LE: blr
|
||||
|
||||
; CHECK-P9-LABEL: @call_v1i128_increment_by_val
|
||||
; CHECK-P9-DAG: lxvx v2
|
||||
; CHECK-P9-DAG: lxvx v3
|
||||
; CHECK-P9-DAG: lxv v2
|
||||
; CHECK-P9-DAG: lxv v3
|
||||
; CHECK-P9: bl v1i128_increment_by_val
|
||||
; CHECK-P9: blr
|
||||
|
||||
|
||||
@ -65,5 +65,5 @@ L.LB38_2452:
|
||||
; CHECK-P9-LABEL: @aercalc_
|
||||
; CHECK-P9: lfs
|
||||
; CHECK-P9: xxspltd
|
||||
; CHECK-P9: stxvx
|
||||
; CHECK-P9: stxv
|
||||
; CHECK-P9-NOT: xxswapd
|
||||
|
||||
@ -33,11 +33,11 @@ entry:
|
||||
; CHECK: stxvd2x [[REG5]]
|
||||
|
||||
; CHECK-P9-LABEL: @bar0
|
||||
; CHECK-P9-DAG: lxvx [[REG1:[0-9]+]]
|
||||
; CHECK-P9-DAG: lxv [[REG1:[0-9]+]]
|
||||
; CHECK-P9-DAG: lfd [[REG2:[0-9]+]], 0(3)
|
||||
; CHECK-P9: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
|
||||
; CHECK-P9: xxpermdi [[REG5:[0-9]+]], [[REG1]], [[REG4]], 1
|
||||
; CHECK-P9: stxvx [[REG5]]
|
||||
; CHECK-P9: stxv [[REG5]]
|
||||
|
||||
define void @bar1() {
|
||||
entry:
|
||||
@ -56,9 +56,9 @@ entry:
|
||||
; CHECK: stxvd2x [[REG5]]
|
||||
|
||||
; CHECK-P9-LABEL: @bar1
|
||||
; CHECK-P9-DAG: lxvx [[REG1:[0-9]+]]
|
||||
; CHECK-P9-DAG: lxv [[REG1:[0-9]+]]
|
||||
; CHECK-P9-DAG: lfd [[REG2:[0-9]+]], 0(3)
|
||||
; CHECK-P9: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
|
||||
; CHECK-P9: xxmrgld [[REG5:[0-9]+]], [[REG4]], [[REG1]]
|
||||
; CHECK-P9: stxvx [[REG5]]
|
||||
; CHECK-P9: stxv [[REG5]]
|
||||
|
||||
|
||||
@ -26,82 +26,82 @@ entry:
|
||||
; CHECK-LABEL: test1
|
||||
; CHECK-P9-LABEL: test1
|
||||
; CHECK: lxvd2x
|
||||
; CHECK-P9-DAG: lxvx
|
||||
; CHECK-P9-DAG: lxv
|
||||
%0 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x i32>* @vsi to i8*))
|
||||
; CHECK: stxvd2x
|
||||
; CHECK-P9-DAG: stxvx
|
||||
; CHECK-P9-DAG: stxv
|
||||
store <4 x i32> %0, <4 x i32>* @res_vsi, align 16
|
||||
; CHECK: lxvd2x
|
||||
; CHECK-P9-DAG: lxvx
|
||||
; CHECK-P9-DAG: lxv
|
||||
%1 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x i32>* @vui to i8*))
|
||||
; CHECK: stxvd2x
|
||||
; CHECK-P9-DAG: stxvx
|
||||
; CHECK-P9-DAG: stxv
|
||||
store <4 x i32> %1, <4 x i32>* @res_vui, align 16
|
||||
; CHECK: lxvd2x
|
||||
; CHECK-P9-DAG: lxvx
|
||||
; CHECK-P9-DAG: lxv
|
||||
%2 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x float>* @vf to i8*))
|
||||
%3 = bitcast <4 x i32> %2 to <4 x float>
|
||||
; CHECK: stxvd2x
|
||||
; CHECK-P9-DAG: stxvx
|
||||
; CHECK-P9-DAG: stxv
|
||||
store <4 x float> %3, <4 x float>* @res_vf, align 16
|
||||
; CHECK: lxvd2x
|
||||
; CHECK-P9-DAG: lxvx
|
||||
; CHECK-P9-DAG: lxv
|
||||
%4 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x i64>* @vsll to i8*))
|
||||
%5 = bitcast <2 x double> %4 to <2 x i64>
|
||||
; CHECK: stxvd2x
|
||||
; CHECK-P9-DAG: stxvx
|
||||
; CHECK-P9-DAG: stxv
|
||||
store <2 x i64> %5, <2 x i64>* @res_vsll, align 16
|
||||
; CHECK: lxvd2x
|
||||
; CHECK-P9-DAG: lxvx
|
||||
; CHECK-P9-DAG: lxv
|
||||
%6 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x i64>* @vull to i8*))
|
||||
%7 = bitcast <2 x double> %6 to <2 x i64>
|
||||
; CHECK: stxvd2x
|
||||
; CHECK-P9-DAG: stxvx
|
||||
; CHECK-P9-DAG: stxv
|
||||
store <2 x i64> %7, <2 x i64>* @res_vull, align 16
|
||||
; CHECK: lxvd2x
|
||||
; CHECK-P9-DAG: lxvx
|
||||
; CHECK-P9-DAG: lxv
|
||||
%8 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x double>* @vd to i8*))
|
||||
; CHECK: stxvd2x
|
||||
; CHECK-P9-DAG: stxvx
|
||||
; CHECK-P9-DAG: stxv
|
||||
store <2 x double> %8, <2 x double>* @res_vd, align 16
|
||||
; CHECK: lxvd2x
|
||||
; CHECK-P9-DAG: lxvx
|
||||
; CHECK-P9-DAG: lxv
|
||||
%9 = load <4 x i32>, <4 x i32>* @vsi, align 16
|
||||
; CHECK: stxvd2x
|
||||
; CHECK-P9-DAG: stxvx
|
||||
; CHECK-P9-DAG: stxv
|
||||
call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %9, i8* bitcast (<4 x i32>* @res_vsi to i8*))
|
||||
; CHECK: lxvd2x
|
||||
; CHECK-P9-DAG: lxvx
|
||||
; CHECK-P9-DAG: lxv
|
||||
%10 = load <4 x i32>, <4 x i32>* @vui, align 16
|
||||
; CHECK: stxvd2x
|
||||
; CHECK-P9-DAG: stxvx
|
||||
; CHECK-P9-DAG: stxv
|
||||
call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %10, i8* bitcast (<4 x i32>* @res_vui to i8*))
|
||||
; CHECK: lxvd2x
|
||||
; CHECK-P9-DAG: lxvx
|
||||
; CHECK-P9-DAG: lxv
|
||||
%11 = load <4 x float>, <4 x float>* @vf, align 16
|
||||
%12 = bitcast <4 x float> %11 to <4 x i32>
|
||||
; CHECK: stxvd2x
|
||||
; CHECK-P9-DAG: stxvx
|
||||
; CHECK-P9-DAG: stxv
|
||||
call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %12, i8* bitcast (<4 x float>* @res_vf to i8*))
|
||||
; CHECK: lxvd2x
|
||||
; CHECK-P9-DAG: lxvx
|
||||
; CHECK-P9-DAG: lxv
|
||||
%13 = load <2 x i64>, <2 x i64>* @vsll, align 16
|
||||
%14 = bitcast <2 x i64> %13 to <2 x double>
|
||||
; CHECK: stxvd2x
|
||||
; CHECK-P9-DAG: stxvx
|
||||
; CHECK-P9-DAG: stxv
|
||||
call void @llvm.ppc.vsx.stxvd2x(<2 x double> %14, i8* bitcast (<2 x i64>* @res_vsll to i8*))
|
||||
; CHECK: lxvd2x
|
||||
; CHECK-P9-DAG: lxvx
|
||||
; CHECK-P9-DAG: lxv
|
||||
%15 = load <2 x i64>, <2 x i64>* @vull, align 16
|
||||
%16 = bitcast <2 x i64> %15 to <2 x double>
|
||||
; CHECK: stxvd2x
|
||||
; CHECK-P9-DAG: stxvx
|
||||
; CHECK-P9-DAG: stxv
|
||||
call void @llvm.ppc.vsx.stxvd2x(<2 x double> %16, i8* bitcast (<2 x i64>* @res_vull to i8*))
|
||||
; CHECK: lxvd2x
|
||||
; CHECK-P9-DAG: lxvx
|
||||
; CHECK-P9-DAG: lxv
|
||||
%17 = load <2 x double>, <2 x double>* @vd, align 16
|
||||
; CHECK: stxvd2x
|
||||
; CHECK-P9-DAG: stxvx
|
||||
; CHECK-P9-DAG: stxv
|
||||
call void @llvm.ppc.vsx.stxvd2x(<2 x double> %17, i8* bitcast (<2 x double>* @res_vd to i8*))
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -21,8 +21,8 @@
|
||||
|
||||
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 \
|
||||
; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s > %t
|
||||
; RUN: grep lxvx < %t | count 6
|
||||
; RUN: grep stxvx < %t | count 6
|
||||
; RUN: grep lxv < %t | count 6
|
||||
; RUN: grep stxv < %t | count 6
|
||||
|
||||
|
||||
@vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 16
|
||||
|
||||
@ -36,109 +36,109 @@ entry:
|
||||
%1 = load <16 x i8>, <16 x i8>* @ucb, align 16
|
||||
%add.i = add <16 x i8> %1, %0
|
||||
tail call void (...) @sink(<16 x i8> %add.i)
|
||||
; CHECK: lxvx 34, 0, 3
|
||||
; CHECK: lxvx 35, 0, 4
|
||||
; CHECK: lxv 34, 0(3)
|
||||
; CHECK: lxv 35, 0(4)
|
||||
; CHECK: vaddubm 2, 3, 2
|
||||
; CHECK: stxvx 34,
|
||||
; CHECK: stxv 34,
|
||||
; CHECK: bl sink
|
||||
%2 = load <16 x i8>, <16 x i8>* @sca, align 16
|
||||
%3 = load <16 x i8>, <16 x i8>* @scb, align 16
|
||||
%add.i22 = add <16 x i8> %3, %2
|
||||
tail call void (...) @sink(<16 x i8> %add.i22)
|
||||
; CHECK: lxvx 34, 0, 3
|
||||
; CHECK: lxvx 35, 0, 4
|
||||
; CHECK: lxv 34, 0(3)
|
||||
; CHECK: lxv 35, 0(4)
|
||||
; CHECK: vaddubm 2, 3, 2
|
||||
; CHECK: stxvx 34,
|
||||
; CHECK: stxv 34,
|
||||
; CHECK: bl sink
|
||||
%4 = load <8 x i16>, <8 x i16>* @usa, align 16
|
||||
%5 = load <8 x i16>, <8 x i16>* @usb, align 16
|
||||
%add.i21 = add <8 x i16> %5, %4
|
||||
tail call void (...) @sink(<8 x i16> %add.i21)
|
||||
; CHECK: lxvx 34, 0, 3
|
||||
; CHECK: lxvx 35, 0, 4
|
||||
; CHECK: lxv 34, 0(3)
|
||||
; CHECK: lxv 35, 0(4)
|
||||
; CHECK: vadduhm 2, 3, 2
|
||||
; CHECK: stxvx 34,
|
||||
; CHECK: stxv 34,
|
||||
; CHECK: bl sink
|
||||
%6 = load <8 x i16>, <8 x i16>* @ssa, align 16
|
||||
%7 = load <8 x i16>, <8 x i16>* @ssb, align 16
|
||||
%add.i20 = add <8 x i16> %7, %6
|
||||
tail call void (...) @sink(<8 x i16> %add.i20)
|
||||
; CHECK: lxvx 34, 0, 3
|
||||
; CHECK: lxvx 35, 0, 4
|
||||
; CHECK: lxv 34, 0(3)
|
||||
; CHECK: lxv 35, 0(4)
|
||||
; CHECK: vadduhm 2, 3, 2
|
||||
; CHECK: stxvx 34,
|
||||
; CHECK: stxv 34,
|
||||
; CHECK: bl sink
|
||||
%8 = load <4 x i32>, <4 x i32>* @uia, align 16
|
||||
%9 = load <4 x i32>, <4 x i32>* @uib, align 16
|
||||
%add.i19 = add <4 x i32> %9, %8
|
||||
tail call void (...) @sink(<4 x i32> %add.i19)
|
||||
; CHECK: lxvx 34, 0, 3
|
||||
; CHECK: lxvx 35, 0, 4
|
||||
; CHECK: lxv 34, 0(3)
|
||||
; CHECK: lxv 35, 0(4)
|
||||
; CHECK: vadduwm 2, 3, 2
|
||||
; CHECK: stxvx 34,
|
||||
; CHECK: stxv 34,
|
||||
; CHECK: bl sink
|
||||
%10 = load <4 x i32>, <4 x i32>* @sia, align 16
|
||||
%11 = load <4 x i32>, <4 x i32>* @sib, align 16
|
||||
%add.i18 = add <4 x i32> %11, %10
|
||||
tail call void (...) @sink(<4 x i32> %add.i18)
|
||||
; CHECK: lxvx 34, 0, 3
|
||||
; CHECK: lxvx 35, 0, 4
|
||||
; CHECK: lxv 34, 0(3)
|
||||
; CHECK: lxv 35, 0(4)
|
||||
; CHECK: vadduwm 2, 3, 2
|
||||
; CHECK: stxvx 34,
|
||||
; CHECK: stxv 34,
|
||||
; CHECK: bl sink
|
||||
%12 = load <2 x i64>, <2 x i64>* @ulla, align 16
|
||||
%13 = load <2 x i64>, <2 x i64>* @ullb, align 16
|
||||
%add.i17 = add <2 x i64> %13, %12
|
||||
tail call void (...) @sink(<2 x i64> %add.i17)
|
||||
; CHECK: lxvx 34, 0, 3
|
||||
; CHECK: lxvx 35, 0, 4
|
||||
; CHECK: lxv 34, 0(3)
|
||||
; CHECK: lxv 35, 0(4)
|
||||
; CHECK: vaddudm 2, 3, 2
|
||||
; CHECK: stxvx 34,
|
||||
; CHECK: stxv 34,
|
||||
; CHECK: bl sink
|
||||
%14 = load <2 x i64>, <2 x i64>* @slla, align 16
|
||||
%15 = load <2 x i64>, <2 x i64>* @sllb, align 16
|
||||
%add.i16 = add <2 x i64> %15, %14
|
||||
tail call void (...) @sink(<2 x i64> %add.i16)
|
||||
; CHECK: lxvx 34, 0, 3
|
||||
; CHECK: lxvx 35, 0, 4
|
||||
; CHECK: lxv 34, 0(3)
|
||||
; CHECK: lxv 35, 0(4)
|
||||
; CHECK: vaddudm 2, 3, 2
|
||||
; CHECK: stxvx 34,
|
||||
; CHECK: stxv 34,
|
||||
; CHECK: bl sink
|
||||
%16 = load <1 x i128>, <1 x i128>* @uxa, align 16
|
||||
%17 = load <1 x i128>, <1 x i128>* @uxb, align 16
|
||||
%add.i15 = add <1 x i128> %17, %16
|
||||
tail call void (...) @sink(<1 x i128> %add.i15)
|
||||
; CHECK: lxvx 34, 0, 3
|
||||
; CHECK: lxvx 35, 0, 4
|
||||
; CHECK: lxv 34, 0(3)
|
||||
; CHECK: lxv 35, 0(4)
|
||||
; CHECK: vadduqm 2, 3, 2
|
||||
; CHECK: stxvx 34,
|
||||
; CHECK: stxv 34,
|
||||
; CHECK: bl sink
|
||||
%18 = load <1 x i128>, <1 x i128>* @sxa, align 16
|
||||
%19 = load <1 x i128>, <1 x i128>* @sxb, align 16
|
||||
%add.i14 = add <1 x i128> %19, %18
|
||||
tail call void (...) @sink(<1 x i128> %add.i14)
|
||||
; CHECK: lxvx 34, 0, 3
|
||||
; CHECK: lxvx 35, 0, 4
|
||||
; CHECK: lxv 34, 0(3)
|
||||
; CHECK: lxv 35, 0(4)
|
||||
; CHECK: vadduqm 2, 3, 2
|
||||
; CHECK: stxvx 34,
|
||||
; CHECK: stxv 34,
|
||||
; CHECK: bl sink
|
||||
%20 = load <4 x float>, <4 x float>* @vfa, align 16
|
||||
%21 = load <4 x float>, <4 x float>* @vfb, align 16
|
||||
%add.i13 = fadd <4 x float> %20, %21
|
||||
tail call void (...) @sink(<4 x float> %add.i13)
|
||||
; CHECK: lxvx 0, 0, 3
|
||||
; CHECK: lxvx 1, 0, 4
|
||||
; CHECK: lxv 0, 0(3)
|
||||
; CHECK: lxv 1, 0(4)
|
||||
; CHECK: xvaddsp 34, 0, 1
|
||||
; CHECK: stxvx 34,
|
||||
; CHECK: stxv 34,
|
||||
; CHECK: bl sink
|
||||
%22 = load <2 x double>, <2 x double>* @vda, align 16
|
||||
%23 = load <2 x double>, <2 x double>* @vdb, align 16
|
||||
%add.i12 = fadd <2 x double> %22, %23
|
||||
tail call void (...) @sink(<2 x double> %add.i12)
|
||||
; CHECK: lxvx 0, 0, 3
|
||||
; CHECK: lxvx 1, 0, 4
|
||||
; CHECK: lxv 0, 0(3)
|
||||
; CHECK: lxv 1, 0(4)
|
||||
; CHECK: xvadddp 0, 0, 1
|
||||
; CHECK: stxvx 0,
|
||||
; CHECK: stxv 0,
|
||||
; CHECK: bl sink
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -23,7 +23,7 @@ define <2 x double> @testi0(<2 x double>* %p1, double* %p2) {
|
||||
|
||||
; CHECK-P9-LABEL: testi0
|
||||
; CHECK-P9: lfd [[REG1:[0-9]+]], 0(4)
|
||||
; CHECK-P9: lxvx [[REG2:[0-9]+]], 0, 3
|
||||
; CHECK-P9: lxv [[REG2:[0-9]+]], 0(3)
|
||||
; CHECK-P9: xxspltd [[REG3:[0-9]+]], [[REG1]], 0
|
||||
; CHECK-P9: xxpermdi 34, [[REG2]], [[REG3]], 1
|
||||
}
|
||||
@ -43,7 +43,7 @@ define <2 x double> @testi1(<2 x double>* %p1, double* %p2) {
|
||||
|
||||
; CHECK-P9-LABEL: testi1
|
||||
; CHECK-P9: lfd [[REG1:[0-9]+]], 0(4)
|
||||
; CHECK-P9: lxvx [[REG2:[0-9]+]], 0, 3
|
||||
; CHECK-P9: lxv [[REG2:[0-9]+]], 0(3)
|
||||
; CHECK-P9: xxspltd [[REG3:[0-9]+]], [[REG1]], 0
|
||||
; CHECK-P9: xxmrgld 34, [[REG3]], [[REG2]]
|
||||
}
|
||||
|
||||
@ -19,7 +19,7 @@ define <2 x double> @test00(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxspltd 34, 0, 0
|
||||
|
||||
; CHECK-P9-LABEL: test00
|
||||
; CHECK-P9: lxvx 0, 0, 3
|
||||
; CHECK-P9: lxv 0, 0(3)
|
||||
; CHECK-P9: xxspltd 34, 0, 1
|
||||
}
|
||||
|
||||
@ -34,7 +34,7 @@ define <2 x double> @test01(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxswapd 34, 0
|
||||
|
||||
; CHECK-P9-LABEL: test01
|
||||
; CHECK-P9: lxvx 34, 0, 3
|
||||
; CHECK-P9: lxv 34, 0(3)
|
||||
}
|
||||
|
||||
define <2 x double> @test02(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
@ -51,8 +51,8 @@ define <2 x double> @test02(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxmrgld 34, 1, 0
|
||||
|
||||
; CHECK-P9-LABEL: @test02
|
||||
; CHECK-P9: lxvx 0, 0, 3
|
||||
; CHECK-P9: lxvx 1, 0, 4
|
||||
; CHECK-P9: lxv 0, 0(3)
|
||||
; CHECK-P9: lxv 1, 0(4)
|
||||
; CHECK-P9: xxmrgld 34, 1, 0
|
||||
}
|
||||
|
||||
@ -70,8 +70,8 @@ define <2 x double> @test03(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxpermdi 34, 1, 0, 1
|
||||
|
||||
; CHECK-P9-LABEL: @test03
|
||||
; CHECK-P9: lxvx 0, 0, 3
|
||||
; CHECK-P9: lxvx 1, 0, 4
|
||||
; CHECK-P9: lxv 0, 0(3)
|
||||
; CHECK-P9: lxv 1, 0(4)
|
||||
; CHECK-P9: xxpermdi 34, 1, 0, 1
|
||||
}
|
||||
|
||||
@ -85,7 +85,7 @@ define <2 x double> @test10(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: lxvd2x 34, 0, 3
|
||||
|
||||
; CHECK-P9-LABEL: @test10
|
||||
; CHECK-P9: lxvx 0, 0, 3
|
||||
; CHECK-P9: lxv 0, 0(3)
|
||||
; CHECK-P9: xxswapd 34, 0
|
||||
}
|
||||
|
||||
@ -100,7 +100,7 @@ define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxspltd 34, 0, 1
|
||||
|
||||
; CHECK-P9-LABEL: @test11
|
||||
; CHECK-P9: lxvx 0, 0, 3
|
||||
; CHECK-P9: lxv 0, 0(3)
|
||||
; CHECK-P9: xxspltd 34, 0, 0
|
||||
}
|
||||
|
||||
@ -118,8 +118,8 @@ define <2 x double> @test12(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxpermdi 34, 1, 0, 2
|
||||
|
||||
; CHECK-P9-LABEL: @test12
|
||||
; CHECK-P9: lxvx 0, 0, 3
|
||||
; CHECK-P9: lxvx 1, 0, 4
|
||||
; CHECK-P9: lxv 0, 0(3)
|
||||
; CHECK-P9: lxv 1, 0(4)
|
||||
; CHECK-P9: xxpermdi 34, 1, 0, 2
|
||||
}
|
||||
|
||||
@ -137,8 +137,8 @@ define <2 x double> @test13(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxmrghd 34, 1, 0
|
||||
|
||||
; CHECK-P9-LABEL: @test13
|
||||
; CHECK-P9: lxvx 0, 0, 3
|
||||
; CHECK-P9: lxvx 1, 0, 4
|
||||
; CHECK-P9: lxv 0, 0(3)
|
||||
; CHECK-P9: lxv 1, 0(4)
|
||||
; CHECK-P9: xxmrghd 34, 1, 0
|
||||
}
|
||||
|
||||
@ -156,8 +156,8 @@ define <2 x double> @test20(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxmrgld 34, 0, 1
|
||||
|
||||
; CHECK-P9-LABEL: @test20
|
||||
; CHECK-P9: lxvx 0, 0, 3
|
||||
; CHECK-P9: lxvx 1, 0, 4
|
||||
; CHECK-P9: lxv 0, 0(3)
|
||||
; CHECK-P9: lxv 1, 0(4)
|
||||
; CHECK-P9: xxmrgld 34, 0, 1
|
||||
}
|
||||
|
||||
@ -175,8 +175,8 @@ define <2 x double> @test21(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxpermdi 34, 0, 1, 1
|
||||
|
||||
; CHECK-P9-LABEL: @test21
|
||||
; CHECK-P9: lxvx 0, 0, 3
|
||||
; CHECK-P9: lxvx 1, 0, 4
|
||||
; CHECK-P9: lxv 0, 0(3)
|
||||
; CHECK-P9: lxv 1, 0(4)
|
||||
; CHECK-P9: xxpermdi 34, 0, 1, 1
|
||||
}
|
||||
|
||||
@ -191,7 +191,7 @@ define <2 x double> @test22(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxspltd 34, 0, 0
|
||||
|
||||
; CHECK-P9-LABEL: @test22
|
||||
; CHECK-P9: lxvx 0, 0, 4
|
||||
; CHECK-P9: lxv 0, 0(4)
|
||||
; CHECK-P9: xxspltd 34, 0, 1
|
||||
}
|
||||
|
||||
@ -206,7 +206,7 @@ define <2 x double> @test23(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxswapd 34, 0
|
||||
|
||||
; CHECK-P9-LABEL: @test23
|
||||
; CHECK-P9: lxvx 34, 0, 4
|
||||
; CHECK-P9: lxv 34, 0(4)
|
||||
}
|
||||
|
||||
define <2 x double> @test30(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
@ -223,8 +223,8 @@ define <2 x double> @test30(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxpermdi 34, 0, 1, 2
|
||||
|
||||
; CHECK-P9-LABEL: @test30
|
||||
; CHECK-P9: lxvx 0, 0, 3
|
||||
; CHECK-P9: lxvx 1, 0, 4
|
||||
; CHECK-P9: lxv 0, 0(3)
|
||||
; CHECK-P9: lxv 1, 0(4)
|
||||
; CHECK-P9: xxpermdi 34, 0, 1, 2
|
||||
}
|
||||
|
||||
@ -242,8 +242,8 @@ define <2 x double> @test31(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxmrghd 34, 0, 1
|
||||
|
||||
; CHECK-P9-LABEL: @test31
|
||||
; CHECK-P9: lxvx 0, 0, 3
|
||||
; CHECK-P9: lxvx 1, 0, 4
|
||||
; CHECK-P9: lxv 0, 0(3)
|
||||
; CHECK-P9: lxv 1, 0(4)
|
||||
; CHECK-P9: xxmrghd 34, 0, 1
|
||||
}
|
||||
|
||||
@ -257,7 +257,7 @@ define <2 x double> @test32(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: lxvd2x 34, 0, 4
|
||||
|
||||
; CHECK-P9-LABEL: @test32
|
||||
; CHECK-P9: lxvx 0, 0, 4
|
||||
; CHECK-P9: lxv 0, 0(4)
|
||||
; CHECK-P9: xxswapd 34, 0
|
||||
}
|
||||
|
||||
@ -272,6 +272,6 @@ define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) {
|
||||
; CHECK: xxspltd 34, 0, 1
|
||||
|
||||
; CHECK-P9-LABEL: @test33
|
||||
; CHECK-P9: lxvx 0, 0, 4
|
||||
; CHECK-P9: lxv 0, 0(4)
|
||||
; CHECK-P9: xxspltd 34, 0, 0
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user