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[MIPS] Move MIPS ABI flags structure constants to the separate header
http://reviews.llvm.org/D9517 The separate header file allows to reuse the MIPS ABI flags structure constants in other LLVM tools like the llvm-readobj. No functional changes. llvm-svn: 236732
This commit is contained in:
Simon Atanasyan
parent
05477e7924
commit
2920c56bce
102
include/llvm/Support/MipsABIFlags.h
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102
include/llvm/Support/MipsABIFlags.h
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@ -0,0 +1,102 @@
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//===--- MipsABIFlags.h - MIPS ABI flags ----------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the constants for the ABI flags structure contained
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// in the .MIPS.abiflags section.
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//
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// https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_MIPSABIFLAGS_H
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#define LLVM_SUPPORT_MIPSABIFLAGS_H
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namespace llvm {
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namespace Mips {
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// Values for the xxx_size bytes of an ABI flags structure.
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enum AFL_REG {
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AFL_REG_NONE = 0x00, // No registers
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AFL_REG_32 = 0x01, // 32-bit registers
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AFL_REG_64 = 0x02, // 64-bit registers
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AFL_REG_128 = 0x03 // 128-bit registers
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};
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// Masks for the ases word of an ABI flags structure.
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enum AFL_ASE {
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AFL_ASE_DSP = 0x00000001, // DSP ASE
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AFL_ASE_DSPR2 = 0x00000002, // DSP R2 ASE
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AFL_ASE_EVA = 0x00000004, // Enhanced VA Scheme
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AFL_ASE_MCU = 0x00000008, // MCU (MicroController) ASE
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AFL_ASE_MDMX = 0x00000010, // MDMX ASE
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AFL_ASE_MIPS3D = 0x00000020, // MIPS-3D ASE
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AFL_ASE_MT = 0x00000040, // MT ASE
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AFL_ASE_SMARTMIPS = 0x00000080, // SmartMIPS ASE
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AFL_ASE_VIRT = 0x00000100, // VZ ASE
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AFL_ASE_MSA = 0x00000200, // MSA ASE
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AFL_ASE_MIPS16 = 0x00000400, // MIPS16 ASE
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AFL_ASE_MICROMIPS = 0x00000800, // MICROMIPS ASE
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AFL_ASE_XPA = 0x00001000 // XPA ASE
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};
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// Values for the isa_ext word of an ABI flags structure.
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enum AFL_EXT {
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AFL_EXT_NONE = 0, // None
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AFL_EXT_XLR = 1, // RMI Xlr instruction
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AFL_EXT_OCTEON2 = 2, // Cavium Networks Octeon2
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AFL_EXT_OCTEONP = 3, // Cavium Networks OcteonP
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AFL_EXT_LOONGSON_3A = 4, // Loongson 3A
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AFL_EXT_OCTEON = 5, // Cavium Networks Octeon
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AFL_EXT_5900 = 6, // MIPS R5900 instruction
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AFL_EXT_4650 = 7, // MIPS R4650 instruction
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AFL_EXT_4010 = 8, // LSI R4010 instruction
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AFL_EXT_4100 = 9, // NEC VR4100 instruction
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AFL_EXT_3900 = 10, // Toshiba R3900 instruction
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AFL_EXT_10000 = 11, // MIPS R10000 instruction
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AFL_EXT_SB1 = 12, // Broadcom SB-1 instruction
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AFL_EXT_4111 = 13, // NEC VR4111/VR4181 instruction
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AFL_EXT_4120 = 14, // NEC VR4120 instruction
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AFL_EXT_5400 = 15, // NEC VR5400 instruction
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AFL_EXT_5500 = 16, // NEC VR5500 instruction
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AFL_EXT_LOONGSON_2E = 17, // ST Microelectronics Loongson 2E
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AFL_EXT_LOONGSON_2F = 18, // ST Microelectronics Loongson 2F
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AFL_EXT_OCTEON3 = 19 // Cavium Networks Octeon3
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};
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// Values for the flags1 word of an ABI flags structure.
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enum AFL_FLAGS1 { AFL_FLAGS1_ODDSPREG = 1 };
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// MIPS object attribute tags
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enum {
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Tag_GNU_MIPS_ABI_FP = 4, // Floating-point ABI used by this object file
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Tag_GNU_MIPS_ABI_MSA = 8, // MSA ABI used by this object file
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};
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// Values for the fp_abi word of an ABI flags structure
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// and for the Tag_GNU_MIPS_ABI_FP attribute tag.
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enum Val_GNU_MIPS_ABI_FP {
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Val_GNU_MIPS_ABI_FP_ANY = 0, // not tagged
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Val_GNU_MIPS_ABI_FP_DOUBLE = 1, // hard float / -mdouble-float
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Val_GNU_MIPS_ABI_FP_SINGLE = 2, // hard float / -msingle-float
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Val_GNU_MIPS_ABI_FP_SOFT = 3, // soft float
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Val_GNU_MIPS_ABI_FP_OLD_64 = 4, // -mips32r2 -mfp64
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Val_GNU_MIPS_ABI_FP_XX = 5, // -mfpxx
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Val_GNU_MIPS_ABI_FP_64 = 6, // -mips32r2 -mfp64
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Val_GNU_MIPS_ABI_FP_64A = 7 // -mips32r2 -mfp64 -mno-odd-spreg
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};
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// Values for the Tag_GNU_MIPS_ABI_MSA attribute tag.
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enum Val_GNU_MIPS_ABI_MSA {
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Val_GNU_MIPS_ABI_MSA_ANY = 0, // not tagged
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Val_GNU_MIPS_ABI_MSA_128 = 1 // 128-bit MSA
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};
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}
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}
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#endif
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@ -14,17 +14,18 @@ using namespace llvm;
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uint8_t MipsABIFlagsSection::getFpABIValue() {
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switch (FpABI) {
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case FpABIKind::ANY:
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return Val_GNU_MIPS_ABI_FP_ANY;
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return Mips::Val_GNU_MIPS_ABI_FP_ANY;
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case FpABIKind::SOFT:
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return Val_GNU_MIPS_ABI_FP_SOFT;
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return Mips::Val_GNU_MIPS_ABI_FP_SOFT;
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case FpABIKind::XX:
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return Val_GNU_MIPS_ABI_FP_XX;
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return Mips::Val_GNU_MIPS_ABI_FP_XX;
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case FpABIKind::S32:
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return Val_GNU_MIPS_ABI_FP_DOUBLE;
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return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
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case FpABIKind::S64:
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if (Is32BitABI)
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return OddSPReg ? Val_GNU_MIPS_ABI_FP_64 : Val_GNU_MIPS_ABI_FP_64A;
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return Val_GNU_MIPS_ABI_FP_DOUBLE;
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return OddSPReg ? Mips::Val_GNU_MIPS_ABI_FP_64
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: Mips::Val_GNU_MIPS_ABI_FP_64A;
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return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
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}
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llvm_unreachable("unexpected fp abi value");
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@ -45,7 +46,7 @@ StringRef MipsABIFlagsSection::getFpABIString(FpABIKind Value) {
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uint8_t MipsABIFlagsSection::getCPR1SizeValue() {
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if (FpABI == FpABIKind::XX)
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return (uint8_t)AFL_REG_32;
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return (uint8_t)Mips::AFL_REG_32;
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return (uint8_t)CPR1Size;
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}
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@ -11,73 +11,13 @@
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#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/MipsABIFlags.h"
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namespace llvm {
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class MCStreamer;
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struct MipsABIFlagsSection {
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// Values for the xxx_size bytes of an ABI flags structure.
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enum AFL_REG {
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AFL_REG_NONE = 0x00, // No registers.
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AFL_REG_32 = 0x01, // 32-bit registers.
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AFL_REG_64 = 0x02, // 64-bit registers.
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AFL_REG_128 = 0x03 // 128-bit registers.
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};
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// Masks for the ases word of an ABI flags structure.
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enum AFL_ASE {
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AFL_ASE_DSP = 0x00000001, // DSP ASE.
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AFL_ASE_DSPR2 = 0x00000002, // DSP R2 ASE.
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AFL_ASE_EVA = 0x00000004, // Enhanced VA Scheme.
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AFL_ASE_MCU = 0x00000008, // MCU (MicroController) ASE.
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AFL_ASE_MDMX = 0x00000010, // MDMX ASE.
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AFL_ASE_MIPS3D = 0x00000020, // MIPS-3D ASE.
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AFL_ASE_MT = 0x00000040, // MT ASE.
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AFL_ASE_SMARTMIPS = 0x00000080, // SmartMIPS ASE.
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AFL_ASE_VIRT = 0x00000100, // VZ ASE.
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AFL_ASE_MSA = 0x00000200, // MSA ASE.
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AFL_ASE_MIPS16 = 0x00000400, // MIPS16 ASE.
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AFL_ASE_MICROMIPS = 0x00000800, // MICROMIPS ASE.
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AFL_ASE_XPA = 0x00001000 // XPA ASE.
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};
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// Values for the isa_ext word of an ABI flags structure.
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enum AFL_EXT {
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AFL_EXT_XLR = 1, // RMI Xlr instruction.
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AFL_EXT_OCTEON2 = 2, // Cavium Networks Octeon2.
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AFL_EXT_OCTEONP = 3, // Cavium Networks OcteonP.
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AFL_EXT_LOONGSON_3A = 4, // Loongson 3A.
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AFL_EXT_OCTEON = 5, // Cavium Networks Octeon.
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AFL_EXT_5900 = 6, // MIPS R5900 instruction.
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AFL_EXT_4650 = 7, // MIPS R4650 instruction.
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AFL_EXT_4010 = 8, // LSI R4010 instruction.
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AFL_EXT_4100 = 9, // NEC VR4100 instruction.
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AFL_EXT_3900 = 10, // Toshiba R3900 instruction.
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AFL_EXT_10000 = 11, // MIPS R10000 instruction.
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AFL_EXT_SB1 = 12, // Broadcom SB-1 instruction.
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AFL_EXT_4111 = 13, // NEC VR4111/VR4181 instruction.
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AFL_EXT_4120 = 14, // NEC VR4120 instruction.
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AFL_EXT_5400 = 15, // NEC VR5400 instruction.
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AFL_EXT_5500 = 16, // NEC VR5500 instruction.
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AFL_EXT_LOONGSON_2E = 17, // ST Microelectronics Loongson 2E.
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AFL_EXT_LOONGSON_2F = 18 // ST Microelectronics Loongson 2F.
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};
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// Values for the fp_abi word of an ABI flags structure.
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enum Val_GNU_MIPS_ABI {
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Val_GNU_MIPS_ABI_FP_ANY = 0,
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Val_GNU_MIPS_ABI_FP_DOUBLE = 1,
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Val_GNU_MIPS_ABI_FP_SOFT = 3,
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Val_GNU_MIPS_ABI_FP_XX = 5,
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Val_GNU_MIPS_ABI_FP_64 = 6,
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Val_GNU_MIPS_ABI_FP_64A = 7
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};
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enum AFL_FLAGS1 {
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AFL_FLAGS1_ODDSPREG = 1
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};
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// Internal representation of the fp_abi related values used in .module.
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enum class FpABIKind { ANY, XX, S32, S64, SOFT };
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@ -88,11 +28,11 @@ struct MipsABIFlagsSection {
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// The revision of ISA: 0 for MIPS V and below, 1-n otherwise.
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uint8_t ISARevision;
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// The size of general purpose registers.
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AFL_REG GPRSize;
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Mips::AFL_REG GPRSize;
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// The size of co-processor 1 registers.
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AFL_REG CPR1Size;
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Mips::AFL_REG CPR1Size;
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// The size of co-processor 2 registers.
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AFL_REG CPR2Size;
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Mips::AFL_REG CPR2Size;
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// Processor-specific extension.
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uint32_t ISAExtensionSet;
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// Mask of ASEs used.
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@ -108,9 +48,10 @@ protected:
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public:
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MipsABIFlagsSection()
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: Version(0), ISALevel(0), ISARevision(0), GPRSize(AFL_REG_NONE),
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CPR1Size(AFL_REG_NONE), CPR2Size(AFL_REG_NONE), ISAExtensionSet(0),
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ASESet(0), OddSPReg(false), Is32BitABI(false), FpABI(FpABIKind::ANY) {}
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: Version(0), ISALevel(0), ISARevision(0), GPRSize(Mips::AFL_REG_NONE),
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CPR1Size(Mips::AFL_REG_NONE), CPR2Size(Mips::AFL_REG_NONE),
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ISAExtensionSet(0), ASESet(0), OddSPReg(false), Is32BitABI(false),
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FpABI(FpABIKind::ANY) {}
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uint16_t getVersionValue() { return (uint16_t)Version; }
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uint8_t getISALevelValue() { return (uint8_t)ISALevel; }
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@ -126,7 +67,7 @@ public:
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uint32_t Value = 0;
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if (OddSPReg)
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Value |= (uint32_t)AFL_FLAGS1_ODDSPREG;
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Value |= (uint32_t)Mips::AFL_FLAGS1_ODDSPREG;
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return Value;
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}
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@ -185,32 +126,32 @@ public:
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template <class PredicateLibrary>
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void setGPRSizeFromPredicates(const PredicateLibrary &P) {
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GPRSize = P.isGP64bit() ? AFL_REG_64 : AFL_REG_32;
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GPRSize = P.isGP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32;
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}
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template <class PredicateLibrary>
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void setCPR1SizeFromPredicates(const PredicateLibrary &P) {
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if (P.abiUsesSoftFloat())
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CPR1Size = AFL_REG_NONE;
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CPR1Size = Mips::AFL_REG_NONE;
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else if (P.hasMSA())
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CPR1Size = AFL_REG_128;
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CPR1Size = Mips::AFL_REG_128;
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else
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CPR1Size = P.isFP64bit() ? AFL_REG_64 : AFL_REG_32;
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CPR1Size = P.isFP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32;
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}
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template <class PredicateLibrary>
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void setASESetFromPredicates(const PredicateLibrary &P) {
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ASESet = 0;
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if (P.hasDSP())
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ASESet |= AFL_ASE_DSP;
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ASESet |= Mips::AFL_ASE_DSP;
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if (P.hasDSPR2())
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ASESet |= AFL_ASE_DSPR2;
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ASESet |= Mips::AFL_ASE_DSPR2;
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if (P.hasMSA())
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ASESet |= AFL_ASE_MSA;
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ASESet |= Mips::AFL_ASE_MSA;
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if (P.inMicroMipsMode())
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ASESet |= AFL_ASE_MICROMIPS;
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ASESet |= Mips::AFL_ASE_MICROMIPS;
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if (P.inMips16Mode())
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ASESet |= AFL_ASE_MIPS16;
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ASESet |= Mips::AFL_ASE_MIPS16;
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}
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template <class PredicateLibrary>
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