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ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets.

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This makes it more likely that we can use the 16-bit push and pop instructions
on Thumb-2, saving around 4 bytes per function.

Differential Revision: http://reviews.llvm.org/D9165

llvm-svn: 235637
This commit is contained in:
Peter Collingbourne 2015-04-23 20:31:26 +00:00
parent 337509326a
commit 2930fae4b8
11 changed files with 42 additions and 42 deletions
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4
lib/Target/ARM/ARMFrameLowering.cpp
View File

@ -1688,8 +1688,8 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
unsigned Reg = UnspilledCS1GPRs[i];
// Don't spill high register if the function is thumb1
if (!AFI->isThumb1OnlyFunction() ||
// Don't spill high register if the function is thumb
if (!AFI->isThumbFunction() ||
isARMLowRegister(Reg) || Reg == ARM::LR) {
MRI.setPhysRegUsed(Reg);
if (!MRI.isReserved(Reg))

2
test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll
View File

@ -33,7 +33,7 @@ define void @foo2(double %p0, ; --> D0
%struct_t* byval %p10) ; --> Stack+8
{
entry:
;CHECK: push.w {r11, lr}
;CHECK: push {r7, lr}
;CHECK-NOT: stm
;CHECK: add r0, sp, #16
;CHECK: bl fooUseStruct

2
test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll
View File

@ -22,7 +22,7 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP
i32 %p3) #0 { ; --> SP+4, NSAA=SP+12
entry:
;CHECK: sub sp, #12
;CHECK: push.w {r11, lr}
;CHECK: push {r7, lr}
;CHECK: sub sp, #4
;CHECK: add r0, sp, #12
;CHECK: str r2, [sp, #16]

2
test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll
View File

@ -19,7 +19,7 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP
i32 %p2) #0 { ; --> SP+24, NSAA=SP+24
entry:
;CHECK: push.w {r11, lr}
;CHECK: push {r7, lr}
;CHECK: ldr r0, [sp, #32]
;CHECK: bl fooUseI32
call void @fooUseI32(i32 %p2)

32
test/CodeGen/ARM/debug-frame.ll
View File

@ -264,14 +264,14 @@ declare void @_ZSt9terminatev()
; CHECK-THUMB-V7-FP-LABEL: _Z4testiiiiiddddd:
; CHECK-THUMB-V7-FP: .cfi_startproc
; CHECK-THUMB-V7-FP: push.w {r4, r7, r11, lr}
; CHECK-THUMB-V7-FP: push {r4, r6, r7, lr}
; CHECK-THUMB-V7-FP: .cfi_def_cfa_offset 16
; CHECK-THUMB-V7-FP: .cfi_offset lr, -4
; CHECK-THUMB-V7-FP: .cfi_offset r11, -8
; CHECK-THUMB-V7-FP: .cfi_offset r7, -12
; CHECK-THUMB-V7-FP: .cfi_offset r7, -8
; CHECK-THUMB-V7-FP: .cfi_offset r6, -12
; CHECK-THUMB-V7-FP: .cfi_offset r4, -16
; CHECK-THUMB-V7-FP: add r7, sp, #4
; CHECK-THUMB-V7-FP: .cfi_def_cfa r7, 12
; CHECK-THUMB-V7-FP: add r7, sp, #8
; CHECK-THUMB-V7-FP: .cfi_def_cfa r7, 8
; CHECK-THUMB-V7-FP: vpush {d8, d9, d10, d11, d12}
; CHECK-THUMB-V7-FP: .cfi_offset d12, -24
; CHECK-THUMB-V7-FP: .cfi_offset d11, -32
@ -300,14 +300,14 @@ declare void @_ZSt9terminatev()
; CHECK-THUMB-V7-FP-NOIAS-LABEL: _Z4testiiiiiddddd:
; CHECK-THUMB-V7-FP-NOIAS: .cfi_startproc
; CHECK-THUMB-V7-FP-NOIAS: push.w {r4, r7, r11, lr}
; CHECK-THUMB-V7-FP-NOIAS: push {r4, r6, r7, lr}
; CHECK-THUMB-V7-FP-NOIAS: .cfi_def_cfa_offset 16
; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 14, -4
; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 11, -8
; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 7, -12
; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 7, -8
; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 6, -12
; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 4, -16
; CHECK-THUMB-V7-FP-NOIAS: add r7, sp, #4
; CHECK-THUMB-V7-FP-NOIAS: .cfi_def_cfa 7, 12
; CHECK-THUMB-V7-FP-NOIAS: add r7, sp, #8
; CHECK-THUMB-V7-FP-NOIAS: .cfi_def_cfa 7, 8
; CHECK-THUMB-V7-FP-NOIAS: vpush {d8, d9, d10, d11, d12}
; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 268, -24
; CHECK-THUMB-V7-FP-NOIAS: .cfi_offset 267, -32
@ -404,11 +404,11 @@ entry:
; CHECK-THUMB-V7-FP-ELIM-LABEL: test2:
; CHECK-THUMB-V7-FP-ELIM: .cfi_startproc
; CHECK-THUMB-V7-FP-ELIM: push.w {r11, lr}
; CHECK-THUMB-V7-FP-ELIM: push {r7, lr}
; CHECK-THUMB-V7-FP-ELIM: .cfi_def_cfa_offset 8
; CHECK-THUMB-V7-FP-ELIM: .cfi_offset lr, -4
; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r11, -8
; CHECK-THUMB-V7-FP-ELIM: pop.w {r11, pc}
; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r7, -8
; CHECK-THUMB-V7-FP-ELIM: pop {r7, pc}
; CHECK-THUMB-V7-FP-ELIM: .cfi_endproc
@ -522,13 +522,13 @@ entry:
; CHECK-THUMB-V7-FP-ELIM-LABEL: test3:
; CHECK-THUMB-V7-FP-ELIM: .cfi_startproc
; CHECK-THUMB-V7-FP-ELIM: push.w {r4, r5, r11, lr}
; CHECK-THUMB-V7-FP-ELIM: push {r4, r5, r7, lr}
; CHECK-THUMB-V7-FP-ELIM: .cfi_def_cfa_offset 16
; CHECK-THUMB-V7-FP-ELIM: .cfi_offset lr, -4
; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r11, -8
; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r7, -8
; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r5, -12
; CHECK-THUMB-V7-FP-ELIM: .cfi_offset r4, -16
; CHECK-THUMB-V7-FP-ELIM: pop.w {r4, r5, r11, pc}
; CHECK-THUMB-V7-FP-ELIM: pop {r4, r5, r7, pc}
; CHECK-THUMB-V7-FP-ELIM: .cfi_endproc

16
test/CodeGen/ARM/fold-stack-adjust.ll
View File

@ -12,11 +12,11 @@ declare void @bar(i8*)
define void @check_simple() minsize {
; CHECK-LABEL: check_simple:
; CHECK: push.w {r7, r8, r9, r10, r11, lr}
; CHECK: push {r3, r4, r5, r6, r7, lr}
; CHECK-NOT: sub sp, sp,
; ...
; CHECK-NOT: add sp, sp,
; CHECK: pop.w {r0, r1, r2, r3, r11, pc}
; CHECK: pop {r0, r1, r2, r3, r7, pc}
; CHECK-T1-LABEL: check_simple:
; CHECK-T1: push {r3, r4, r5, r6, r7, lr}
@ -44,11 +44,11 @@ define void @check_simple() minsize {
define void @check_simple_too_big() minsize {
; CHECK-LABEL: check_simple_too_big:
; CHECK: push.w {r11, lr}
; CHECK: push {r7, lr}
; CHECK: sub sp,
; ...
; CHECK: add sp,
; CHECK: pop.w {r11, pc}
; CHECK: pop {r7, pc}
%var = alloca i8, i32 64
call void @bar(i8* %var)
ret void
@ -93,11 +93,11 @@ define void @check_vfp_fold() minsize {
; folded in except that doing so would clobber the value being returned.
define i64 @check_no_return_clobber() minsize {
; CHECK-LABEL: check_no_return_clobber:
; CHECK: push.w {r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK: push {r1, r2, r3, r4, r5, r6, r7, lr}
; CHECK-NOT: sub sp,
; ...
; CHECK: add sp, #24
; CHECK: pop.w {r11, pc}
; CHECK: pop {r7, pc}
; Just to keep iOS FileCheck within previous function:
; CHECK-IOS-LABEL: check_no_return_clobber:
@ -176,9 +176,9 @@ define void @test_varsize(...) minsize {
; CHECK-LABEL: test_varsize:
; CHECK: sub sp, #16
; CHECK: push.w {r9, r10, r11, lr}
; CHECK: push {r5, r6, r7, lr}
; ...
; CHECK: pop.w {r2, r3, r11, lr}
; CHECK: pop.w {r2, r3, r7, lr}
; CHECK: add sp, #16
; CHECK: bx lr

4
test/CodeGen/ARM/interrupt-attr.ll
View File

@ -35,7 +35,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" {
; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to
; appropriate sentinel so no special return needed).
; CHECK-M-LABEL: irq_fn:
; CHECK-M: push.w {r4, r10, r11, lr}
; CHECK-M: push.w {r4, r7, r11, lr}
; CHECK-M: add.w r11, sp, #8
; CHECK-M: mov r4, sp
; CHECK-M: bfc r4, #0, #3
@ -43,7 +43,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" {
; CHECK-M: bl _bar
; CHECK-M: sub.w r4, r11, #8
; CHECK-M: mov sp, r4
; CHECK-M: pop.w {r4, r10, r11, pc}
; CHECK-M: pop.w {r4, r7, r11, pc}
call arm_aapcscc void @bar()
ret void

4
test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
View File

@ -7,8 +7,8 @@ entry:
; CHECK-LABEL: __gcov_execlp:
; CHECK: sub sp, #8
; CHECK: push
; CHECK: add r7, sp, #4
; CHECK: sub.w r4, r7, #4
; CHECK: add r7, sp, #8
; CHECK: sub.w r4, r7, #8
; CHECK: mov sp, r4
; CHECK-NOT: mov sp, r7
; CHECK: add sp, #8

2
test/CodeGen/Thumb2/large-stack.ll
View File

@ -29,7 +29,7 @@ define i32 @test3() {
; DARWIN: sub.w sp, sp, #805306368
; DARWIN: sub sp, #20
; LINUX-LABEL: test3:
; LINUX: push.w {r4, r7, r11, lr}
; LINUX: push {r4, r6, r7, lr}
; LINUX: sub.w sp, sp, #805306368
; LINUX: sub sp, #16
%retval = alloca i32, align 4

8
test/CodeGen/Thumb2/tpsoft.ll
View File

@ -32,13 +32,13 @@ bb: ; preds = %entry
; ELFOBJ: Section {
; ELFOBJ: Name: .text
; ELFOBJ-LE: SectionData (
;;; BL __aeabi_read_tp is ---------+
;;; BL __aeabi_read_tp is ---+
;;; V
; ELFOBJ-LE-NEXT: 0000: 2DE90048 0E487844 0168FFF7 FEFF4058
; ELFOBJ-LE-NEXT: 0000: 80B50E48 78440168 FFF7FEFF 40580D28
; ELFOBJ-BE: SectionData (
;;; BL __aeabi_read_tp is ---------+
;;; BL __aeabi_read_tp is ---+
;;; V
; ELFOBJ-BE-NEXT: 0000: E92D4800 480E4478 6801F7FF FFFE5840
; ELFOBJ-BE-NEXT: 0000: B580480E 44786801 F7FFFFFE 5840280D
bb1: ; preds = %entry

4
test/MC/ARM/elf-thumbfunc-reloc.ll
View File

@ -24,13 +24,13 @@ entry:
; make sure that bl 0 <foo> (fff7feff) is correctly encoded
; CHECK: Sections [
; CHECK: SectionData (
; CHECK: 0000: 70472DE9 0048FFF7 FEFFBDE8 0088
; CHECK: 0000: 704780B5 FFF7FEFF 80BD
; CHECK: )
; CHECK: ]
; CHECK: Relocations [
; CHECK-NEXT: Section {{.*}} .rel.text {
; CHECK-NEXT: 0x6 R_ARM_THM_CALL foo 0x0
; CHECK-NEXT: 0x4 R_ARM_THM_CALL foo 0x0
; CHECK-NEXT: }
; CHECK-NEXT: Section {{.*}} .rel.ARM.exidx {
; CHECK-NEXT: 0x0 R_ARM_PREL31 .text 0x0