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[Hexagon] Remove (redundant) HexagonISelLowering::isHvxOperation(SDValue)
Use isHvxOperation(SDNode*) instead.
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@ -3025,7 +3025,7 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
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return LowerINLINEASM(Op, DAG);
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if (isHvxOperation(Op)) {
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if (isHvxOperation(Op.getNode())) {
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// If HVX lowering returns nothing, try the default lowering.
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if (SDValue V = LowerHvxOperation(Op, DAG))
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return V;
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@ -3132,13 +3132,13 @@ HexagonTargetLowering::ReplaceNodeResults(SDNode *N,
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SDValue
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HexagonTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
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const {
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SDValue Op(N, 0);
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if (isHvxOperation(Op)) {
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if (isHvxOperation(N)) {
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if (SDValue V = PerformHvxDAGCombine(N, DCI))
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return V;
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return SDValue();
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}
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SDValue Op(N, 0);
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const SDLoc &dl(Op);
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unsigned Opc = Op.getOpcode();
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@ -479,7 +479,6 @@ namespace HexagonISD {
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findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
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const override;
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bool isHvxOperation(SDValue Op) const;
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bool isHvxOperation(SDNode *N) const;
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SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const;
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void LowerHvxOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
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@ -1802,17 +1802,6 @@ HexagonTargetLowering::PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
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return SDValue();
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}
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bool
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HexagonTargetLowering::isHvxOperation(SDValue Op) const {
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// If the type of the result, or any operand type are HVX vector types,
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// this is an HVX operation.
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return Subtarget.isHVXVectorType(ty(Op), true) ||
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llvm::any_of(Op.getNode()->ops(),
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[this] (SDValue V) {
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return Subtarget.isHVXVectorType(ty(V), true);
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});
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}
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bool
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HexagonTargetLowering::isHvxOperation(SDNode *N) const {
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// If the type of any result, or any operand type are HVX vector types,
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