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[mips] Remove codegen support for branch likely instructions.
This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421
This commit is contained in:
Simon Dardis
parent
90f7334acf
commit
2947a2cc6d
@ -215,14 +215,25 @@ class SWXC1_FT<string opstr, RegisterOperand DRC,
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}
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class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
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SDPatternOperator Op = null_frag, bit DelaySlot = 1> :
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SDPatternOperator Op = null_frag> :
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InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
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!strconcat(opstr, "\t$fcc, $offset"),
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[(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
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FrmFI, opstr>, HARDFLOAT {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = DelaySlot;
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let hasDelaySlot = 1;
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let Defs = [AT];
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let hasFCCRegOperand = 1;
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}
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class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> :
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InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
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!strconcat(opstr, "\t$fcc, $offset"), [], Itin,
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FrmFI, opstr>, HARDFLOAT {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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let Defs = [AT];
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let hasFCCRegOperand = 1;
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}
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@ -619,11 +630,11 @@ def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
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def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
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BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
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def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, II_BC1FL, MIPS_BRANCH_F, 0>,
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def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>,
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BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
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def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
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BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
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def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>,
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def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>,
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BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
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/// Floating Point Compare
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@ -1399,27 +1399,47 @@ class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
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// Conditional Branch
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class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
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RegisterOperand RO, bit DelaySlot = 1> :
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RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
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!strconcat(opstr, "\t$rs, $rt, $offset"),
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[(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
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FrmI, opstr> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = DelaySlot;
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let hasDelaySlot = 1;
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let Defs = [AT];
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bit isCTI = 1;
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}
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class CBranchLikely<string opstr, DAGOperand opnd, RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
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!strconcat(opstr, "\t$rs, $rt, $offset"), [], II_BCC, FrmI, opstr> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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let Defs = [AT];
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bit isCTI = 1;
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}
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class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
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RegisterOperand RO, bit DelaySlot = 1> :
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RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, opnd:$offset),
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!strconcat(opstr, "\t$rs, $offset"),
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[(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
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FrmI, opstr> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = DelaySlot;
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let hasDelaySlot = 1;
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let Defs = [AT];
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bit isCTI = 1;
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}
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class CBranchZeroLikely<string opstr, DAGOperand opnd, RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, opnd:$offset),
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!strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI, opstr> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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let Defs = [AT];
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bit isCTI = 1;
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}
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@ -1495,10 +1515,10 @@ let isCall=1, hasDelaySlot=1, isCTI=1, Defs = [RA] in {
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[], II_JALR, FrmR, opstr>;
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class BGEZAL_FT<string opstr, DAGOperand opnd,
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RegisterOperand RO, bit DelaySlot = 1> :
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RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, opnd:$offset),
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!strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> {
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let hasDelaySlot = DelaySlot;
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let hasDelaySlot = 1;
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}
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}
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@ -2011,26 +2031,26 @@ def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
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AdditionalRequires<[RelocNotPIC]>, IsBranch;
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def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6;
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def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
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def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
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def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>,
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BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
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def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
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def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
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def BNEL : MMRel, CBranchLikely<"bnel", brtarget, GPR32Opnd>,
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BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
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def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
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BGEZ_FM<1, 1>;
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def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
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def BGEZL : MMRel, CBranchZeroLikely<"bgezl", brtarget, GPR32Opnd>,
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BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
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def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
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BGEZ_FM<7, 0>;
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def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
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def BGTZL : MMRel, CBranchZeroLikely<"bgtzl", brtarget, GPR32Opnd>,
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BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
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def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
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BGEZ_FM<6, 0>;
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def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
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def BLEZL : MMRel, CBranchZeroLikely<"blezl", brtarget, GPR32Opnd>,
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BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
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def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
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BGEZ_FM<1, 0>;
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def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
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def BLTZL : MMRel, CBranchZeroLikely<"bltzl", brtarget, GPR32Opnd>,
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BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
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def B : UncondBranch<BEQ>;
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@ -2044,11 +2064,11 @@ def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
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ISA_MIPS32_NOT_32R6_64R6;
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def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
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ISA_MIPS1_NOT_32R6_64R6;
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def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
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def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd>,
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BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
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def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
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ISA_MIPS1_NOT_32R6_64R6;
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def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
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def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>,
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BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
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def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
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@ -1,5 +1,4 @@
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# Verify that every branch and jump instruction is followed by a delay slot
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# except for the branch likely instructions.
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# Verify that every branch and jump instruction is followed by a delay slot.
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#
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# RUN: llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 | FileCheck %s
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@ -48,52 +47,52 @@
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beqz $11,1332
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# CHECK: bc1fl 1332
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# CHECK-NOT: nop
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# CHECK: nop
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bc1fl 1332
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# CHECK: bc1fl 1332
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# CHECK-NOT: nop
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# CHECK: nop
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bc1fl $fcc0, 1332
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# CHECK: bc1fl $fcc3, 1332
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# CHECK-NOT: nop
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# CHECK: nop
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bc1fl $fcc3, 1332
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# CHECK: bc1tl 1332
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# CHECK-NOT: nop
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# CHECK: nop
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bc1tl 1332
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# CHECK: bc1tl 1332
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# CHECK-NOT: nop
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# CHECK: nop
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bc1tl $fcc0, 1332
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# CHECK: bc1tl $fcc3, 1332
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# CHECK-NOT: nop
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# CHECK: nop
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bc1tl $fcc3, 1332
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# CHECK: beql $9, $6, 1332
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# CHECK-NOT: nop
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# CHECK: nop
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beql $9,$6,1332
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# CHECK: beql $9, $zero, 1332
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# CHECK-NOT: nop
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# CHECK: nop
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beqzl $9,1332
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# CHECK: bnel $9, $6, 1332
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# CHECK-NOT: nop
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# CHECK: nop
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bnel $9,$6,1332
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# CHECK: bnel $9, $zero, 1332
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# CHECK-NOT: nop
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# CHECK: nop
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bnezl $9,1332
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# CHECK: bgezl $6, 1332
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# CHECK-NOT: nop
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# CHECK: nop
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bgezl $6,1332
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# CHECK: bgtzl $6, 1332
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# CHECK-NOT: nop
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# CHECK: nop
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bgtzl $6,1332
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# CHECK: blezl $6, 1332
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# CHECK-NOT: nop
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# CHECK: nop
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blezl $6,1332
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# CHECK: bltzl $6, 1332
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# CHECK-NOT: nop
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# CHECK: nop
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bltzl $6,1332
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# CHECK: bgezall $6, 1332
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# CHECK-NOT: nop
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# CHECK: nop
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bgezall $6,1332
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# CHECK: bltzall $6, 1332
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# CHECK-NOT: nop
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# CHECK: nop
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bltzall $6,1332
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# CHECK: j 1328
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