1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00

Rewrite MachineOperand::print and MachineInstr::print to avoid

uses of TM->getSubtargetImpl and propagate to all calls.

This could be a debugging regression in places where we had a
TargetMachine and/or MachineFunction but don't have it as part
of the MachineInstr. Fixing this would require passing a
MachineFunction/Function down through the print operator, but
none of the existing uses in tree seem to do this.

llvm-svn: 230710
This commit is contained in:
Eric Christopher 2015-02-27 00:11:34 +00:00
parent efb97e5733
commit 29697aeb53
9 changed files with 36 additions and 50 deletions

View File

@ -1113,8 +1113,7 @@ public:
//
// Debugging support
//
void print(raw_ostream &OS, const TargetMachine *TM = nullptr,
bool SkipOpers = false) const;
void print(raw_ostream &OS, bool SkipOpers = false) const;
void dump() const;
//===--------------------------------------------------------------------===//

View File

@ -217,7 +217,7 @@ public:
///
void clearParent() { ParentMI = nullptr; }
void print(raw_ostream &os, const TargetMachine *TM = nullptr) const;
void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr) const;
//===--------------------------------------------------------------------===//
// Accessors that tell you what kind of MachineOperand you're looking at.

View File

@ -276,7 +276,7 @@ public:
/// getDebugLoc - Return DebugLoc of this UserValue.
DebugLoc getDebugLoc() { return dl;}
void print(raw_ostream&, const TargetMachine*);
void print(raw_ostream &, const TargetRegisterInfo *);
};
} // namespace
@ -362,7 +362,7 @@ public:
};
} // namespace
void UserValue::print(raw_ostream &OS, const TargetMachine *TM) {
void UserValue::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
DIVariable DV(Variable);
OS << "!\"";
DV.printExtendedName(OS);
@ -378,7 +378,7 @@ void UserValue::print(raw_ostream &OS, const TargetMachine *TM) {
}
for (unsigned i = 0, e = locations.size(); i != e; ++i) {
OS << " Loc" << i << '=';
locations[i].print(OS, TM);
locations[i].print(OS, TRI);
}
OS << '\n';
}
@ -386,7 +386,7 @@ void UserValue::print(raw_ostream &OS, const TargetMachine *TM) {
void LDVImpl::print(raw_ostream &OS) {
OS << "********** DEBUG VARIABLES **********\n";
for (unsigned i = 0, e = userValues.size(); i != e; ++i)
userValues[i]->print(OS, &MF->getTarget());
userValues[i]->print(OS, TRI);
}
void UserValue::coalesceLocation(unsigned LocNo) {
@ -1004,7 +1004,7 @@ void LDVImpl::emitDebugValues(VirtRegMap *VRM) {
return;
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
for (unsigned i = 0, e = userValues.size(); i != e; ++i) {
DEBUG(userValues[i]->print(dbgs(), &MF->getTarget()));
DEBUG(userValues[i]->print(dbgs(), TRI));
userValues[i]->rewriteLocations(*VRM, *TRI);
userValues[i]->emitDebugValues(VRM, *LIS, *TII);
}

View File

@ -307,7 +307,7 @@ void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
OS << '\t';
if (I->isInsideBundle())
OS << " * ";
I->print(OS, &getParent()->getTarget());
I->print(OS);
}
// Print the successors of this block according to the CFG.

View File

@ -276,17 +276,8 @@ hash_code llvm::hash_value(const MachineOperand &MO) {
/// print - Print the specified machine operand.
///
void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
// If the instruction is embedded into a basic block, we can find the
// target info for the instruction.
if (!TM)
if (const MachineInstr *MI = getParent())
if (const MachineBasicBlock *MBB = MI->getParent())
if (const MachineFunction *MF = MBB->getParent())
TM = &MF->getTarget();
const TargetRegisterInfo *TRI =
TM ? TM->getSubtargetImpl()->getRegisterInfo() : nullptr;
void MachineOperand::print(raw_ostream &OS,
const TargetRegisterInfo *TRI) const {
switch (getType()) {
case MachineOperand::MO_Register:
OS << PrintReg(getReg(), TRI, getSubReg());
@ -1512,17 +1503,19 @@ void MachineInstr::dump() const {
#endif
}
void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
bool SkipOpers) const {
// We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
void MachineInstr::print(raw_ostream &OS, bool SkipOpers) const {
// We can be a bit tidier if we know the MachineFunction.
const MachineFunction *MF = nullptr;
const TargetRegisterInfo *TRI = nullptr;
const MachineRegisterInfo *MRI = nullptr;
const TargetInstrInfo *TII = nullptr;
if (const MachineBasicBlock *MBB = getParent()) {
MF = MBB->getParent();
if (!TM && MF)
TM = &MF->getTarget();
if (MF)
if (MF) {
MRI = &MF->getRegInfo();
TRI = MF->getSubtarget().getRegisterInfo();
TII = MF->getSubtarget().getInstrInfo();
}
}
// Save a list of virtual registers.
@ -1535,7 +1528,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
!getOperand(StartOp).isImplicit();
++StartOp) {
if (StartOp != 0) OS << ", ";
getOperand(StartOp).print(OS, TM);
getOperand(StartOp).print(OS, TRI);
unsigned Reg = getOperand(StartOp).getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg))
VirtRegs.push_back(Reg);
@ -1545,8 +1538,8 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
OS << " = ";
// Print the opcode name.
if (TM && TM->getSubtargetImpl()->getInstrInfo())
OS << TM->getSubtargetImpl()->getInstrInfo()->getName(getOpcode());
if (TII)
OS << TII->getName(getOpcode());
else
OS << "UNKNOWN";
@ -1562,7 +1555,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
// Print asm string.
OS << " ";
getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
getOperand(InlineAsm::MIOp_AsmString).print(OS, TRI);
// Print HasSideEffects, MayLoad, MayStore, IsAlignStack
unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
@ -1600,9 +1593,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
if (MRI->use_empty(Reg)) {
bool HasAliasLive = false;
for (MCRegAliasIterator AI(
Reg, TM->getSubtargetImpl()->getRegisterInfo(), true);
AI.isValid(); ++AI) {
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
unsigned AliasReg = *AI;
if (!MRI->use_empty(AliasReg)) {
HasAliasLive = true;
@ -1635,10 +1626,9 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
if (DI.isVariable() && !DIV.getName().empty())
OS << "!\"" << DIV.getName() << '\"';
else
MO.print(OS, TM);
} else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
OS << TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIndexName(
MO.getImm());
MO.print(OS, TRI);
} else if (TRI && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
OS << TRI->getSubRegIndexName(MO.getImm());
} else if (i == AsmDescOp && MO.isImm()) {
// Pretty print the inline asm operand descriptor.
OS << '$' << AsmOpCount++;
@ -1655,11 +1645,8 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
unsigned RCID = 0;
if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
if (TM) {
const TargetRegisterInfo *TRI =
TM->getSubtargetImpl()->getRegisterInfo();
OS << ':'
<< TRI->getRegClassName(TRI->getRegClass(RCID));
if (TRI) {
OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
} else
OS << ":RC" << RCID;
}
@ -1673,7 +1660,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
// Compute the index of the next operand descriptor.
AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
} else
MO.print(OS, TM);
MO.print(OS, TRI);
}
// Briefly indicate whether any call clobbers were omitted.
@ -1709,7 +1696,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
if (!HaveSemi) OS << ";"; HaveSemi = true;
for (unsigned i = 0; i != VirtRegs.size(); ++i) {
const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
OS << " " << MRI->getTargetRegisterInfo()->getRegClassName(RC)
OS << " " << TRI->getRegClassName(RC)
<< ':' << PrintReg(VirtRegs[i]);
for (unsigned j = i+1; j != VirtRegs.size();) {
if (MRI->getRegClass(VirtRegs[j]) != RC) {

View File

@ -397,7 +397,7 @@ void MachineVerifier::report(const char *msg,
assert(MO);
report(msg, MO->getParent());
errs() << "- operand " << MONum << ": ";
MO->print(errs(), TM);
MO->print(errs(), TRI);
errs() << "\n";
}

View File

@ -1211,7 +1211,7 @@ std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
else if (SU == &ExitSU)
oss << "<exit>";
else
SU->getInstr()->print(oss, &TM, /*SkipOpers=*/true);
SU->getInstr()->print(oss, /*SkipOpers=*/true);
return oss.str();
}

View File

@ -287,12 +287,12 @@ public:
raw_string_ostream OS(S);
OS << "{";
StartInst->print(OS, NULL, true);
StartInst->print(OS, /* SkipOpers= */true);
OS << " -> ";
LastInst->print(OS, NULL, true);
LastInst->print(OS, /* SkipOpers= */true);
if (KillInst) {
OS << " (kill @ ";
KillInst->print(OS, NULL, true);
KillInst->print(OS, /* SkipOpers= */true);
OS << ")";
}
OS << "}";

View File

@ -438,7 +438,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
// Rewind to first instruction newly inserted.
while (Start != BB.begin() && std::prev(Start) != PrevI) --Start;
dbgs() << "Inserted instructions:\n\t";
Start->print(dbgs(), &MF.getTarget());
Start->print(dbgs());
while (++Start != std::next(I)) {}
}
dumpStack();