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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 03:02:36 +01:00
Rewrite MachineOperand::print and MachineInstr::print to avoid
uses of TM->getSubtargetImpl and propagate to all calls. This could be a debugging regression in places where we had a TargetMachine and/or MachineFunction but don't have it as part of the MachineInstr. Fixing this would require passing a MachineFunction/Function down through the print operator, but none of the existing uses in tree seem to do this. llvm-svn: 230710
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@ -1113,8 +1113,7 @@ public:
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//
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// Debugging support
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//
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void print(raw_ostream &OS, const TargetMachine *TM = nullptr,
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bool SkipOpers = false) const;
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void print(raw_ostream &OS, bool SkipOpers = false) const;
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void dump() const;
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//===--------------------------------------------------------------------===//
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@ -217,7 +217,7 @@ public:
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///
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void clearParent() { ParentMI = nullptr; }
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void print(raw_ostream &os, const TargetMachine *TM = nullptr) const;
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void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr) const;
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//===--------------------------------------------------------------------===//
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// Accessors that tell you what kind of MachineOperand you're looking at.
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@ -276,7 +276,7 @@ public:
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/// getDebugLoc - Return DebugLoc of this UserValue.
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DebugLoc getDebugLoc() { return dl;}
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void print(raw_ostream&, const TargetMachine*);
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void print(raw_ostream &, const TargetRegisterInfo *);
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};
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} // namespace
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@ -362,7 +362,7 @@ public:
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};
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} // namespace
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void UserValue::print(raw_ostream &OS, const TargetMachine *TM) {
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void UserValue::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
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DIVariable DV(Variable);
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OS << "!\"";
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DV.printExtendedName(OS);
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@ -378,7 +378,7 @@ void UserValue::print(raw_ostream &OS, const TargetMachine *TM) {
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}
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for (unsigned i = 0, e = locations.size(); i != e; ++i) {
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OS << " Loc" << i << '=';
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locations[i].print(OS, TM);
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locations[i].print(OS, TRI);
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}
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OS << '\n';
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}
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@ -386,7 +386,7 @@ void UserValue::print(raw_ostream &OS, const TargetMachine *TM) {
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void LDVImpl::print(raw_ostream &OS) {
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OS << "********** DEBUG VARIABLES **********\n";
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for (unsigned i = 0, e = userValues.size(); i != e; ++i)
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userValues[i]->print(OS, &MF->getTarget());
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userValues[i]->print(OS, TRI);
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}
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void UserValue::coalesceLocation(unsigned LocNo) {
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@ -1004,7 +1004,7 @@ void LDVImpl::emitDebugValues(VirtRegMap *VRM) {
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return;
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const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
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for (unsigned i = 0, e = userValues.size(); i != e; ++i) {
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DEBUG(userValues[i]->print(dbgs(), &MF->getTarget()));
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DEBUG(userValues[i]->print(dbgs(), TRI));
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userValues[i]->rewriteLocations(*VRM, *TRI);
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userValues[i]->emitDebugValues(VRM, *LIS, *TII);
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}
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@ -307,7 +307,7 @@ void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
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OS << '\t';
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if (I->isInsideBundle())
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OS << " * ";
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I->print(OS, &getParent()->getTarget());
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I->print(OS);
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}
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// Print the successors of this block according to the CFG.
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@ -276,17 +276,8 @@ hash_code llvm::hash_value(const MachineOperand &MO) {
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/// print - Print the specified machine operand.
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///
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void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
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// If the instruction is embedded into a basic block, we can find the
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// target info for the instruction.
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if (!TM)
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if (const MachineInstr *MI = getParent())
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if (const MachineBasicBlock *MBB = MI->getParent())
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if (const MachineFunction *MF = MBB->getParent())
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TM = &MF->getTarget();
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const TargetRegisterInfo *TRI =
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TM ? TM->getSubtargetImpl()->getRegisterInfo() : nullptr;
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void MachineOperand::print(raw_ostream &OS,
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const TargetRegisterInfo *TRI) const {
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switch (getType()) {
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case MachineOperand::MO_Register:
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OS << PrintReg(getReg(), TRI, getSubReg());
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@ -1512,17 +1503,19 @@ void MachineInstr::dump() const {
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#endif
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}
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void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
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bool SkipOpers) const {
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// We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
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void MachineInstr::print(raw_ostream &OS, bool SkipOpers) const {
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// We can be a bit tidier if we know the MachineFunction.
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const MachineFunction *MF = nullptr;
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const TargetRegisterInfo *TRI = nullptr;
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const MachineRegisterInfo *MRI = nullptr;
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const TargetInstrInfo *TII = nullptr;
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if (const MachineBasicBlock *MBB = getParent()) {
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MF = MBB->getParent();
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if (!TM && MF)
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TM = &MF->getTarget();
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if (MF)
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if (MF) {
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MRI = &MF->getRegInfo();
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TRI = MF->getSubtarget().getRegisterInfo();
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TII = MF->getSubtarget().getInstrInfo();
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}
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}
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// Save a list of virtual registers.
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@ -1535,7 +1528,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
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!getOperand(StartOp).isImplicit();
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++StartOp) {
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if (StartOp != 0) OS << ", ";
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getOperand(StartOp).print(OS, TM);
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getOperand(StartOp).print(OS, TRI);
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unsigned Reg = getOperand(StartOp).getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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VirtRegs.push_back(Reg);
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@ -1545,8 +1538,8 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
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OS << " = ";
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// Print the opcode name.
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if (TM && TM->getSubtargetImpl()->getInstrInfo())
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OS << TM->getSubtargetImpl()->getInstrInfo()->getName(getOpcode());
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if (TII)
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OS << TII->getName(getOpcode());
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else
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OS << "UNKNOWN";
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@ -1562,7 +1555,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
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if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
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// Print asm string.
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OS << " ";
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getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
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getOperand(InlineAsm::MIOp_AsmString).print(OS, TRI);
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// Print HasSideEffects, MayLoad, MayStore, IsAlignStack
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unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
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@ -1600,9 +1593,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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if (MRI->use_empty(Reg)) {
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bool HasAliasLive = false;
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for (MCRegAliasIterator AI(
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Reg, TM->getSubtargetImpl()->getRegisterInfo(), true);
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AI.isValid(); ++AI) {
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for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
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unsigned AliasReg = *AI;
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if (!MRI->use_empty(AliasReg)) {
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HasAliasLive = true;
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@ -1635,10 +1626,9 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
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if (DI.isVariable() && !DIV.getName().empty())
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OS << "!\"" << DIV.getName() << '\"';
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else
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MO.print(OS, TM);
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} else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
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OS << TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIndexName(
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MO.getImm());
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MO.print(OS, TRI);
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} else if (TRI && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
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OS << TRI->getSubRegIndexName(MO.getImm());
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} else if (i == AsmDescOp && MO.isImm()) {
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// Pretty print the inline asm operand descriptor.
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OS << '$' << AsmOpCount++;
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@ -1655,11 +1645,8 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
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unsigned RCID = 0;
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if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
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if (TM) {
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const TargetRegisterInfo *TRI =
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TM->getSubtargetImpl()->getRegisterInfo();
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OS << ':'
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<< TRI->getRegClassName(TRI->getRegClass(RCID));
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if (TRI) {
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OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
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} else
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OS << ":RC" << RCID;
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}
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@ -1673,7 +1660,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
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// Compute the index of the next operand descriptor.
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AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
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} else
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MO.print(OS, TM);
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MO.print(OS, TRI);
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}
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// Briefly indicate whether any call clobbers were omitted.
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@ -1709,7 +1696,7 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
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if (!HaveSemi) OS << ";"; HaveSemi = true;
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for (unsigned i = 0; i != VirtRegs.size(); ++i) {
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const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
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OS << " " << MRI->getTargetRegisterInfo()->getRegClassName(RC)
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OS << " " << TRI->getRegClassName(RC)
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<< ':' << PrintReg(VirtRegs[i]);
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for (unsigned j = i+1; j != VirtRegs.size();) {
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if (MRI->getRegClass(VirtRegs[j]) != RC) {
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@ -397,7 +397,7 @@ void MachineVerifier::report(const char *msg,
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assert(MO);
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report(msg, MO->getParent());
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errs() << "- operand " << MONum << ": ";
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MO->print(errs(), TM);
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MO->print(errs(), TRI);
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errs() << "\n";
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}
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@ -1211,7 +1211,7 @@ std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
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else if (SU == &ExitSU)
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oss << "<exit>";
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else
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SU->getInstr()->print(oss, &TM, /*SkipOpers=*/true);
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SU->getInstr()->print(oss, /*SkipOpers=*/true);
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return oss.str();
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}
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@ -287,12 +287,12 @@ public:
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raw_string_ostream OS(S);
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OS << "{";
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StartInst->print(OS, NULL, true);
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StartInst->print(OS, /* SkipOpers= */true);
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OS << " -> ";
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LastInst->print(OS, NULL, true);
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LastInst->print(OS, /* SkipOpers= */true);
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if (KillInst) {
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OS << " (kill @ ";
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KillInst->print(OS, NULL, true);
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KillInst->print(OS, /* SkipOpers= */true);
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OS << ")";
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}
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OS << "}";
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@ -438,7 +438,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
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// Rewind to first instruction newly inserted.
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while (Start != BB.begin() && std::prev(Start) != PrevI) --Start;
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dbgs() << "Inserted instructions:\n\t";
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Start->print(dbgs(), &MF.getTarget());
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Start->print(dbgs());
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while (++Start != std::next(I)) {}
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}
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dumpStack();
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