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[ARM,MVE] Add vqdmull[b,t]q intrinsic families
Summary: This patch adds two families of ACLE intrinsics: vqdmullbq and vqdmulltq (including vector-vector and vector-scalar variants) and the corresponding LLVM IR intrinsics llvm.arm.mve.vqdmull and llvm.arm.mve.vqdmull.predicated. Reviewers: simon_tatham, MarkMurrayARM, dmgreen, ostannard Reviewed By: MarkMurrayARM Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74845
This commit is contained in:
Mikhail Maltsev
parent
c4fa124875
commit
29b9c00369
@ -1168,4 +1168,14 @@ defm int_arm_mve_vbrsr: MVEMXPredicated<
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[llvm_anyvector_ty], [],
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[LLVMMatchType<0>, llvm_i32_ty], LLVMMatchType<0>, llvm_anyvector_ty>;
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def int_arm_mve_vqdmull: Intrinsic<
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[llvm_anyvector_ty],
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[llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty],
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[IntrNoMem]>;
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def int_arm_mve_vqdmull_predicated: Intrinsic<
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[llvm_anyvector_ty],
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[llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty, llvm_anyvector_ty,
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LLVMMatchType<0>],
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[IntrNoMem]>;
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} // end TargetPrefix
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@ -4577,13 +4577,34 @@ class MVE_VQDMULL<string iname, string suffix, bit size, bit T,
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let validForTailPredication = 1;
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}
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multiclass MVE_VQDMULL_halves<string suffix, bit size, string cstr=""> {
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def bh : MVE_VQDMULL<"vqdmullb", suffix, size, 0b0, cstr>;
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def th : MVE_VQDMULL<"vqdmullt", suffix, size, 0b1, cstr>;
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multiclass MVE_VQDMULL_m<string iname, MVEVectorVTInfo VTI, bit size, bit T,
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string cstr> {
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def "" : MVE_VQDMULL<iname, VTI.Suffix, size, T, cstr>;
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defvar Inst = !cast<Instruction>(NAME);
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let Predicates = [HasMVEInt] in {
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// Unpredicated saturating multiply
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def : Pat<(VTI.DblVec (int_arm_mve_vqdmull (VTI.Vec MQPR:$Qm),
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(VTI.Vec MQPR:$Qn), (i32 T))),
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(VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
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// Predicated saturating multiply
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def : Pat<(VTI.DblVec (int_arm_mve_vqdmull_predicated
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(VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
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(i32 T), (VTI.DblPred VCCR:$mask),
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(VTI.DblVec MQPR:$inactive))),
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(VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
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ARMVCCThen, (VTI.DblPred VCCR:$mask),
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(VTI.DblVec MQPR:$inactive)))>;
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}
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}
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defm MVE_VQDMULLs16 : MVE_VQDMULL_halves<"s16", 0b0>;
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defm MVE_VQDMULLs32 : MVE_VQDMULL_halves<"s32", 0b1, "@earlyclobber $Qd">;
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multiclass MVE_VQDMULL_halves<MVEVectorVTInfo VTI, bit size, string cstr=""> {
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defm bh : MVE_VQDMULL_m<"vqdmullb", VTI, size, 0b0, cstr>;
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defm th : MVE_VQDMULL_m<"vqdmullt", VTI, size, 0b1, cstr>;
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}
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defm MVE_VQDMULLs16 : MVE_VQDMULL_halves<MVE_v8s16, 0b0>;
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defm MVE_VQDMULLs32 : MVE_VQDMULL_halves<MVE_v4s32, 0b1, "@earlyclobber $Qd">;
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// end of mve_qDest_qSrc
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@ -4766,13 +4787,37 @@ class MVE_VQDMULL_qr<string iname, string suffix, bit size,
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let validForTailPredication = 1;
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}
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multiclass MVE_VQDMULL_qr_halves<string suffix, bit size, string cstr=""> {
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def bh : MVE_VQDMULL_qr<"vqdmullb", suffix, size, 0b0, cstr>;
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def th : MVE_VQDMULL_qr<"vqdmullt", suffix, size, 0b1, cstr>;
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multiclass MVE_VQDMULL_qr_m<string iname, MVEVectorVTInfo VTI, bit size,
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bit T, string cstr> {
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def "" : MVE_VQDMULL_qr<iname, VTI.Suffix, size, T, cstr>;
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defvar Inst = !cast<Instruction>(NAME);
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let Predicates = [HasMVEInt] in {
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// Unpredicated saturating multiply
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def : Pat<(VTI.DblVec (int_arm_mve_vqdmull (VTI.Vec MQPR:$Qm),
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(VTI.Vec (ARMvdup rGPR:$val)),
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(i32 T))),
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(VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (i32 rGPR:$val)))>;
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// Predicated saturating multiply
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def : Pat<(VTI.DblVec (int_arm_mve_vqdmull_predicated
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(VTI.Vec MQPR:$Qm),
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(VTI.Vec (ARMvdup rGPR:$val)),
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(i32 T),
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(VTI.DblPred VCCR:$mask),
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(VTI.DblVec MQPR:$inactive))),
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(VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (i32 rGPR:$val),
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ARMVCCThen, (VTI.DblPred VCCR:$mask),
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(VTI.DblVec MQPR:$inactive)))>;
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}
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}
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defm MVE_VQDMULL_qr_s16 : MVE_VQDMULL_qr_halves<"s16", 0b0>;
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defm MVE_VQDMULL_qr_s32 : MVE_VQDMULL_qr_halves<"s32", 0b1, "@earlyclobber $Qd">;
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multiclass MVE_VQDMULL_qr_halves<MVEVectorVTInfo VTI, bit size, string cstr=""> {
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defm bh : MVE_VQDMULL_qr_m<"vqdmullb", VTI, size, 0b0, cstr>;
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defm th : MVE_VQDMULL_qr_m<"vqdmullt", VTI, size, 0b1, cstr>;
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}
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defm MVE_VQDMULL_qr_s16 : MVE_VQDMULL_qr_halves<MVE_v8s16, 0b0>;
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defm MVE_VQDMULL_qr_s32 : MVE_VQDMULL_qr_halves<MVE_v4s32, 0b1, "@earlyclobber $Qd">;
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class MVE_VxADDSUB_qr<string iname, string suffix,
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bit bit_28, bits<2> bits_21_20, bit subtract,
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221
test/CodeGen/Thumb2/mve-intrinsics/vqdmull.ll
Normal file
221
test/CodeGen/Thumb2/mve-intrinsics/vqdmull.ll
Normal file
@ -0,0 +1,221 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s
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declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
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declare <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32)
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declare <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32>, <4 x i32>, i32)
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declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>)
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declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <2 x i64>)
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define arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_s16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test_vqdmullbq_s16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqdmullb.s16 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0)
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_s32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vqdmullbq_s32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqdmullb.s32 q2, q0, q1
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; CHECK-NEXT: vmov q0, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0)
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ret <2 x i64> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_s16(<4 x i32> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vqdmullbq_m_s16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vqdmullbt.s16 q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 0, <4 x i1> %1, <4 x i32> %inactive)
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ret <4 x i32> %2
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}
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define arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_s32(<2 x i64> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vqdmullbq_m_s32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vqdmullbt.s32 q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1, <2 x i64> %inactive)
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ret <2 x i64> %2
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}
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define arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_n_s16(<8 x i16> %a, i16 signext %b) {
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; CHECK-LABEL: test_vqdmullbq_n_s16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqdmullb.s16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0
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%.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
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%0 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %a, <8 x i16> %.splat, i32 0)
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_n_s32(<4 x i32> %a, i32 %b) #0 {
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; CHECK-LABEL: test_vqdmullbq_n_s32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqdmullb.s32 q1, q0, r0
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0
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%.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
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%0 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %a, <4 x i32> %.splat, i32 0)
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ret <2 x i64> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @test_vqdmullbq_m_n_s16(<4 x i32> %inactive, <8 x i16> %a, i16 signext %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vqdmullbq_m_n_s16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vqdmullbt.s16 q0, q1, r0
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; CHECK-NEXT: bx lr
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entry:
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%.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0
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%.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %.splat, i32 0, <4 x i1> %1, <4 x i32> %inactive)
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ret <4 x i32> %2
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}
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define arm_aapcs_vfpcc <2 x i64> @test_vqdmullbq_m_n_s32(<2 x i64> %inactive, <4 x i32> %a, i32 %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vqdmullbq_m_n_s32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vqdmullbt.s32 q0, q1, r0
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; CHECK-NEXT: bx lr
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entry:
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%.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0
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%.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %.splat, i32 0, <4 x i1> %1, <2 x i64> %inactive)
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ret <2 x i64> %2
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}
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define arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_s16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test_vqdmulltq_s16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqdmullt.s16 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1)
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_s32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vqdmulltq_s32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqdmullt.s32 q2, q0, q1
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; CHECK-NEXT: vmov q0, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1)
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ret <2 x i64> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_s16(<4 x i32> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vqdmulltq_m_s16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vqdmulltt.s16 q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 1, <4 x i1> %1, <4 x i32> %inactive)
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ret <4 x i32> %2
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}
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define arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_s32(<2 x i64> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vqdmulltq_m_s32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vqdmulltt.s32 q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, <4 x i1> %1, <2 x i64> %inactive)
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ret <2 x i64> %2
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}
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define arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_n_s16(<8 x i16> %a, i16 signext %b) {
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; CHECK-LABEL: test_vqdmulltq_n_s16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqdmullt.s16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0
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%.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
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%0 = call <4 x i32> @llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> %a, <8 x i16> %.splat, i32 1)
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_n_s32(<4 x i32> %a, i32 %b) {
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; CHECK-LABEL: test_vqdmulltq_n_s32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqdmullt.s32 q1, q0, r0
|
||||
; CHECK-NEXT: vmov q0, q1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0
|
||||
%.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
%0 = call <2 x i64> @llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> %a, <4 x i32> %.splat, i32 1)
|
||||
ret <2 x i64> %0
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @test_vqdmulltq_m_n_s16(<4 x i32> %inactive, <8 x i16> %a, i16 signext %b, i16 zeroext %p) {
|
||||
; CHECK-LABEL: test_vqdmulltq_m_n_s16:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vqdmulltt.s16 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%.splatinsert = insertelement <8 x i16> undef, i16 %b, i32 0
|
||||
%.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %.splat, i32 1, <4 x i1> %1, <4 x i32> %inactive)
|
||||
ret <4 x i32> %2
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <2 x i64> @test_vqdmulltq_m_n_s32(<2 x i64> %inactive, <4 x i32> %a, i32 %b, i16 zeroext %p) {
|
||||
; CHECK-LABEL: test_vqdmulltq_m_n_s32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmsr p0, r1
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vqdmulltt.s32 q0, q1, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%.splatinsert = insertelement <4 x i32> undef, i32 %b, i32 0
|
||||
%.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
%0 = zext i16 %p to i32
|
||||
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
|
||||
%2 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %.splat, i32 1, <4 x i1> %1, <2 x i64> %inactive)
|
||||
ret <2 x i64> %2
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user