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[PowerPC-QPX] add more test for QPX madd/msub operands order - NFC

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This commit is contained in:
Chen Zheng 2020-04-29 00:48:49 -04:00
parent 9e66c35e52
commit 29eb6637b1
1 changed files with 59 additions and 0 deletions
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59
test/CodeGen/PowerPC/qpx-qvfmadd.ll
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@ -18,3 +18,62 @@ define <4 x float> @test_qvfmadds(<4 x float> %0, <4 x float> %1, <4 x float> %2
%5 = fadd reassoc nsz <4 x float> %4, %0
ret <4 x float> %5
}
define <2 x double> @test_qvfnmadd(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
; CHECK: test_qvfnmadd
; CHECK: QVFNMADD %2, %0, %1, implicit $rm
;
%4 = fmul reassoc nsz <2 x double> %2, %1
%5 = fadd reassoc nsz <2 x double> %4, %0
%6 = fneg reassoc nsz <2 x double> %5
ret <2 x double> %6
}
define <4 x float> @test_qvfnmadds(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
; CHECK: test_qvfnmadds
; CHECK: QVFNMADDSs %2, %0, %1, implicit $rm
;
%4 = fmul reassoc nsz <4 x float> %2, %1
%5 = fadd reassoc nsz <4 x float> %4, %0
%6 = fneg reassoc nsz <4 x float> %5
ret <4 x float> %6
}
define <2 x double> @test_qvfmsub(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
; CHECK: test_qvfmsub
; CHECK: QVFMSUB %2, %0, %1, implicit $rm
;
%4 = fmul reassoc nsz <2 x double> %2, %1
%5 = fsub reassoc nsz <2 x double> %4, %0
ret <2 x double> %5
}
define <4 x float> @test_qvfmsubs(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
; CHECK: test_qvfmsubs
; CHECK: QVFMSUBSs %2, %0, %1, implicit $rm
;
%4 = fmul reassoc nsz <4 x float> %2, %1
%5 = fsub reassoc nsz <4 x float> %4, %0
ret <4 x float> %5
}
define <2 x double> @test_qvfnmsub(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
; CHECK: test_qvfnmsub
; CHECK: QVFNMSUB %2, %0, %1, implicit $rm
;
%4 = fmul reassoc nsz <2 x double> %2, %1
%5 = fsub reassoc nsz <2 x double> %4, %0
%6 = fneg reassoc nsz <2 x double> %5
ret <2 x double> %6
}
define <4 x float> @test_qvfnmsubs(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
; CHECK: test_qvfnmsubs
; CHECK: QVFNMSUBSs %2, %0, %1, implicit $rm
;
%4 = fmul reassoc nsz <4 x float> %2, %1
%5 = fsub reassoc nsz <4 x float> %4, %0
%6 = fneg reassoc nsz <4 x float> %5
ret <4 x float> %6
}