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[AArch64] Teach RegisterBankInfo about the CC register bank.

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We need to cover each register class with a register bank.

llvm-svn: 265629
This commit is contained in:
Quentin Colombet 2016-04-07 00:39:29 +00:00
parent 5f260975e3
commit 29f0c6f517
2 changed files with 12 additions and 0 deletions
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11
lib/Target/AArch64/AArch64RegisterBankInfo.cpp
View File

@ -51,6 +51,15 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
assert(RBFPR.getSize() == 512 &&
"FPRs should hold up to 512-bit via QQQQ sequence");
// Initialize the CCR bank.
createRegisterBank(AArch64::CCRRegBankID, "CCR");
addRegBankCoverage(AArch64::CCRRegBankID, AArch64::CCRRegClassID, TRI);
const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
(void)RBCCR;
assert(RBCCR.contains(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
"Class not added?");
assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
verify(TRI);
}
@ -94,6 +103,8 @@ const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass(
case AArch64::WSeqPairsClassRegClassID:
case AArch64::XSeqPairsClassRegClassID:
return getRegBank(AArch64::FPRRegBankID);
case AArch64::CCRRegClassID:
return getRegBank(AArch64::CCRRegBankID);
default:
llvm_unreachable("Register class not supported");
}

1
lib/Target/AArch64/AArch64RegisterBankInfo.h
View File

@ -24,6 +24,7 @@ namespace AArch64 {
enum {
GPRRegBankID = 0, /// General Purpose Registers: W, X.
FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q.
CCRRegBankID = 2, /// Conditional register: NZCV.
NumRegisterBanks
};
} // End AArch64 namespace.