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[ARM][ParallelDSP] Change the search for smlads
Two functional changes have been made here:
- Now search up from any add instruction to find the chains of
operations that we may turn into a smlad. This allows the
generation of a smlad which doesn't accumulate into a phi.
- The search function has been corrected to stop it falsely searching
up through an invalid path.
The bulk of the changes have been making the Reduction struct a class
and making it more C++y with getters and setters.
Differential Revision: https://reviews.llvm.org/D61780
llvm-svn: 365740
This commit is contained in:
Sam Parker
parent
bca59d7f71
commit
29f96962d8
@ -48,7 +48,7 @@ DisableParallelDSP("disable-arm-parallel-dsp", cl::Hidden, cl::init(false),
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namespace {
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struct OpChain;
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struct BinOpChain;
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struct Reduction;
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class Reduction;
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using OpChainList = SmallVector<std::unique_ptr<OpChain>, 8>;
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using ReductionList = SmallVector<Reduction, 8>;
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@ -79,10 +79,8 @@ namespace {
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unsigned size() const { return AllValues.size(); }
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};
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// 'BinOpChain' and 'Reduction' are just some bookkeeping data structures.
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// 'Reduction' contains the phi-node and accumulator statement from where we
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// start pattern matching, and 'BinOpChain' the multiplication
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// instructions that are candidates for parallel execution.
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// 'BinOpChain' holds the multiplication instructions that are candidates
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// for parallel execution.
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struct BinOpChain : public OpChain {
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ValueList LHS; // List of all (narrow) left hand operands.
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ValueList RHS; // List of all (narrow) right hand operands.
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@ -97,15 +95,70 @@ namespace {
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bool AreSymmetrical(BinOpChain *Other);
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};
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struct Reduction {
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PHINode *Phi; // The Phi-node from where we start
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// pattern matching.
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Instruction *AccIntAdd; // The accumulating integer add statement,
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// i.e, the reduction statement.
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OpChainList MACCandidates; // The MAC candidates associated with
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// this reduction statement.
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PMACPairList PMACPairs;
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Reduction (PHINode *P, Instruction *Acc) : Phi(P), AccIntAdd(Acc) { };
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/// Represent a sequence of multiply-accumulate operations with the aim to
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/// perform the multiplications in parallel.
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class Reduction {
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Instruction *Root = nullptr;
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Value *Acc = nullptr;
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OpChainList Muls;
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PMACPairList MulPairs;
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SmallPtrSet<Instruction*, 4> Adds;
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public:
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Reduction() = delete;
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Reduction (Instruction *Add) : Root(Add) { }
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/// Record an Add instruction that is a part of the this reduction.
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void InsertAdd(Instruction *I) { Adds.insert(I); }
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/// Record a BinOpChain, rooted at a Mul instruction, that is a part of
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/// this reduction.
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void InsertMul(Instruction *I, ValueList &LHS, ValueList &RHS) {
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Muls.push_back(make_unique<BinOpChain>(I, LHS, RHS));
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}
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/// Add the incoming accumulator value, returns true if a value had not
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/// already been added. Returning false signals to the user that this
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/// reduction already has a value to initialise the accumulator.
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bool InsertAcc(Value *V) {
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if (Acc)
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return false;
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Acc = V;
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return true;
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}
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/// Set two BinOpChains, rooted at muls, that can be executed as a single
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/// parallel operation.
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void AddMulPair(BinOpChain *Mul0, BinOpChain *Mul1) {
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MulPairs.push_back(std::make_pair(Mul0, Mul1));
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}
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/// Return true if enough mul operations are found that can be executed in
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/// parallel.
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bool CreateParallelPairs();
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/// Return the add instruction which is the root of the reduction.
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Instruction *getRoot() { return Root; }
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/// Return the incoming value to be accumulated. This maybe null.
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Value *getAccumulator() { return Acc; }
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/// Return the set of adds that comprise the reduction.
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SmallPtrSetImpl<Instruction*> &getAdds() { return Adds; }
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/// Return the BinOpChain, rooted at mul instruction, that comprise the
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/// the reduction.
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OpChainList &getMuls() { return Muls; }
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/// Return the BinOpChain, rooted at mul instructions, that have been
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/// paired for parallel execution.
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PMACPairList &getMulPairs() { return MulPairs; }
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/// To finalise, replace the uses of the root with the intrinsic call.
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void UpdateRoot(Instruction *SMLAD) {
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Root->replaceAllUsesWith(SMLAD);
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}
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};
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class WidenedLoad {
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@ -133,25 +186,25 @@ namespace {
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const DataLayout *DL;
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Module *M;
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std::map<LoadInst*, LoadInst*> LoadPairs;
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SmallPtrSet<LoadInst*, 4> OffsetLoads;
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std::map<LoadInst*, std::unique_ptr<WidenedLoad>> WideLoads;
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template<unsigned>
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bool IsNarrowSequence(Value *V, ValueList &VL);
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bool RecordMemoryOps(BasicBlock *BB);
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bool InsertParallelMACs(Reduction &Reduction);
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void InsertParallelMACs(Reduction &Reduction);
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bool AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, MemInstList &VecMem);
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LoadInst* CreateWideLoad(SmallVectorImpl<LoadInst*> &Loads,
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IntegerType *LoadTy);
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void CreateParallelMACPairs(Reduction &R);
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Instruction *CreateSMLADCall(SmallVectorImpl<LoadInst*> &VecLd0,
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SmallVectorImpl<LoadInst*> &VecLd1,
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Instruction *Acc, bool Exchange,
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Instruction *InsertAfter);
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bool CreateParallelPairs(Reduction &R);
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/// Try to match and generate: SMLAD, SMLADX - Signed Multiply Accumulate
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/// Dual performs two signed 16x16-bit multiplications. It adds the
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/// products to a 32-bit accumulate operand. Optionally, the instruction can
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/// exchange the halfwords of the second operand before performing the
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/// arithmetic.
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bool MatchSMLAD(Function &F);
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bool MatchSMLAD(Loop *L);
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public:
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static char ID;
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@ -201,11 +254,8 @@ namespace {
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return false;
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}
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// We need a preheader as getIncomingValueForBlock assumes there is one.
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if (!TheLoop->getLoopPreheader()) {
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LLVM_DEBUG(dbgs() << "No preheader found, bailing out\n");
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return false;
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}
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if (!TheLoop->getLoopPreheader())
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InsertPreheaderForLoop(L, DT, LI, nullptr, true);
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Function &F = *Header->getParent();
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M = F.getParent();
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@ -242,7 +292,7 @@ namespace {
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return false;
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}
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bool Changes = MatchSMLAD(F);
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bool Changes = MatchSMLAD(L);
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return Changes;
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}
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};
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@ -275,6 +325,51 @@ bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1,
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return true;
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}
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// MaxBitwidth: the maximum supported bitwidth of the elements in the DSP
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// instructions, which is set to 16. So here we should collect all i8 and i16
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// narrow operations.
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// TODO: we currently only collect i16, and will support i8 later, so that's
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// why we check that types are equal to MaxBitWidth, and not <= MaxBitWidth.
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template<unsigned MaxBitWidth>
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bool ARMParallelDSP::IsNarrowSequence(Value *V, ValueList &VL) {
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ConstantInt *CInt;
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if (match(V, m_ConstantInt(CInt))) {
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// TODO: if a constant is used, it needs to fit within the bit width.
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return false;
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}
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auto *I = dyn_cast<Instruction>(V);
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if (!I)
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return false;
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Value *Val, *LHS, *RHS;
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if (match(V, m_Trunc(m_Value(Val)))) {
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if (cast<TruncInst>(I)->getDestTy()->getIntegerBitWidth() == MaxBitWidth)
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return IsNarrowSequence<MaxBitWidth>(Val, VL);
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} else if (match(V, m_Add(m_Value(LHS), m_Value(RHS)))) {
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// TODO: we need to implement sadd16/sadd8 for this, which enables to
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// also do the rewrite for smlad8.ll, but it is unsupported for now.
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return false;
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} else if (match(V, m_ZExtOrSExt(m_Value(Val)))) {
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if (cast<CastInst>(I)->getSrcTy()->getIntegerBitWidth() != MaxBitWidth)
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return false;
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if (match(Val, m_Load(m_Value()))) {
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auto *Ld = cast<LoadInst>(Val);
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// Check that these load could be paired.
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if (!LoadPairs.count(Ld) && !OffsetLoads.count(Ld))
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return false;
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VL.push_back(Val);
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VL.push_back(I);
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return true;
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}
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}
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return false;
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}
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/// Iterate through the block and record base, offset pairs of loads which can
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/// be widened into a single load.
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bool ARMParallelDSP::RecordMemoryOps(BasicBlock *BB) {
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@ -342,6 +437,7 @@ bool ARMParallelDSP::RecordMemoryOps(BasicBlock *BB) {
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if (AreSequentialAccesses<LoadInst>(Base, Offset, *DL, *SE) &&
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SafeToPair(Base, Offset)) {
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LoadPairs[Base] = Offset;
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OffsetLoads.insert(Offset);
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break;
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}
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}
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@ -357,15 +453,150 @@ bool ARMParallelDSP::RecordMemoryOps(BasicBlock *BB) {
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return LoadPairs.size() > 1;
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}
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void ARMParallelDSP::CreateParallelMACPairs(Reduction &R) {
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OpChainList &Candidates = R.MACCandidates;
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PMACPairList &PMACPairs = R.PMACPairs;
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const unsigned Elems = Candidates.size();
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// Loop Pass that needs to identify integer add/sub reductions of 16-bit vector
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// multiplications.
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// To use SMLAD:
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// 1) we first need to find integer add then look for this pattern:
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//
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// acc0 = ...
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// ld0 = load i16
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// sext0 = sext i16 %ld0 to i32
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// ld1 = load i16
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// sext1 = sext i16 %ld1 to i32
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// mul0 = mul %sext0, %sext1
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// ld2 = load i16
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// sext2 = sext i16 %ld2 to i32
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// ld3 = load i16
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// sext3 = sext i16 %ld3 to i32
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// mul1 = mul i32 %sext2, %sext3
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// add0 = add i32 %mul0, %acc0
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// acc1 = add i32 %add0, %mul1
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//
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// Which can be selected to:
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//
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// ldr r0
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// ldr r1
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// smlad r2, r0, r1, r2
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//
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// If constants are used instead of loads, these will need to be hoisted
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// out and into a register.
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//
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// If loop invariants are used instead of loads, these need to be packed
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// before the loop begins.
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//
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bool ARMParallelDSP::MatchSMLAD(Loop *L) {
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// Search recursively back through the operands to find a tree of values that
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// form a multiply-accumulate chain. The search records the Add and Mul
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// instructions that form the reduction and allows us to find a single value
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// to be used as the initial input to the accumlator.
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std::function<bool(Value*, Reduction&)> Search = [&]
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(Value *V, Reduction &R) -> bool {
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if (Elems < 2)
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return;
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// If we find a non-instruction, try to use it as the initial accumulator
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// value. This may have already been found during the search in which case
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// this function will return false, signaling a search fail.
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auto *I = dyn_cast<Instruction>(V);
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if (!I)
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return R.InsertAcc(V);
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auto CanPair = [&](BinOpChain *PMul0, BinOpChain *PMul1) {
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switch (I->getOpcode()) {
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default:
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break;
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case Instruction::PHI:
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// Could be the accumulator value.
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return R.InsertAcc(V);
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case Instruction::Add: {
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// Adds should be adding together two muls, or another add and a mul to
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// be within the mac chain. One of the operands may also be the
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// accumulator value at which point we should stop searching.
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bool ValidLHS = Search(I->getOperand(0), R);
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bool ValidRHS = Search(I->getOperand(1), R);
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if (!ValidLHS && !ValidLHS)
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return false;
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else if (ValidLHS && ValidRHS) {
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R.InsertAdd(I);
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return true;
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} else {
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R.InsertAdd(I);
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return R.InsertAcc(I);
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}
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}
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case Instruction::Mul: {
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Value *MulOp0 = I->getOperand(0);
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Value *MulOp1 = I->getOperand(1);
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if (isa<SExtInst>(MulOp0) && isa<SExtInst>(MulOp1)) {
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ValueList LHS;
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ValueList RHS;
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if (IsNarrowSequence<16>(MulOp0, LHS) &&
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IsNarrowSequence<16>(MulOp1, RHS)) {
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R.InsertMul(I, LHS, RHS);
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return true;
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}
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}
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return false;
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}
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case Instruction::SExt:
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return Search(I->getOperand(0), R);
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}
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return false;
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};
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bool Changed = false;
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SmallPtrSet<Instruction*, 4> AllAdds;
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BasicBlock *Latch = L->getLoopLatch();
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for (Instruction &I : reverse(*Latch)) {
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if (I.getOpcode() != Instruction::Add)
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continue;
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if (AllAdds.count(&I))
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continue;
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const auto *Ty = I.getType();
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if (!Ty->isIntegerTy(32) && !Ty->isIntegerTy(64))
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continue;
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Reduction R(&I);
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if (!Search(&I, R))
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continue;
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if (!CreateParallelPairs(R))
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continue;
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InsertParallelMACs(R);
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Changed = true;
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AllAdds.insert(R.getAdds().begin(), R.getAdds().end());
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}
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return Changed;
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}
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bool ARMParallelDSP::CreateParallelPairs(Reduction &R) {
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// Not enough mul operations to make a pair.
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if (R.getMuls().size() < 2)
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return false;
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// Check that the muls operate directly upon sign extended loads.
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for (auto &MulChain : R.getMuls()) {
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// A mul has 2 operands, and a narrow op consist of sext and a load; thus
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// we expect at least 4 items in this operand value list.
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if (MulChain->size() < 4) {
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LLVM_DEBUG(dbgs() << "Operand list too short.\n");
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return false;
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}
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MulChain->PopulateLoads();
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ValueList &LHS = static_cast<BinOpChain*>(MulChain.get())->LHS;
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ValueList &RHS = static_cast<BinOpChain*>(MulChain.get())->RHS;
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// Use +=2 to skip over the expected extend instructions.
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for (unsigned i = 0, e = LHS.size(); i < e; i += 2) {
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if (!isa<LoadInst>(LHS[i]) || !isa<LoadInst>(RHS[i]))
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return false;
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}
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}
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auto CanPair = [&](Reduction &R, BinOpChain *PMul0, BinOpChain *PMul1) {
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if (!PMul0->AreSymmetrical(PMul1))
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return false;
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@ -391,13 +622,13 @@ void ARMParallelDSP::CreateParallelMACPairs(Reduction &R) {
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if (AreSequentialLoads(Ld0, Ld1, PMul0->VecLd)) {
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if (AreSequentialLoads(Ld2, Ld3, PMul1->VecLd)) {
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LLVM_DEBUG(dbgs() << "OK: found two pairs of parallel loads!\n");
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PMACPairs.push_back(std::make_pair(PMul0, PMul1));
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R.AddMulPair(PMul0, PMul1);
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return true;
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} else if (AreSequentialLoads(Ld3, Ld2, PMul1->VecLd)) {
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LLVM_DEBUG(dbgs() << "OK: found two pairs of parallel loads!\n");
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LLVM_DEBUG(dbgs() << " exchanging Ld2 and Ld3\n");
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PMul1->Exchange = true;
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PMACPairs.push_back(std::make_pair(PMul0, PMul1));
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R.AddMulPair(PMul0, PMul1);
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return true;
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}
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} else if (AreSequentialLoads(Ld1, Ld0, PMul0->VecLd) &&
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@ -407,16 +638,18 @@ void ARMParallelDSP::CreateParallelMACPairs(Reduction &R) {
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LLVM_DEBUG(dbgs() << " and swapping muls\n");
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PMul0->Exchange = true;
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// Only the second operand can be exchanged, so swap the muls.
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PMACPairs.push_back(std::make_pair(PMul1, PMul0));
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R.AddMulPair(PMul1, PMul0);
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return true;
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}
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}
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return false;
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};
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OpChainList &Muls = R.getMuls();
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const unsigned Elems = Muls.size();
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SmallPtrSet<const Instruction*, 4> Paired;
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for (unsigned i = 0; i < Elems; ++i) {
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BinOpChain *PMul0 = static_cast<BinOpChain*>(Candidates[i].get());
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BinOpChain *PMul0 = static_cast<BinOpChain*>(Muls[i].get());
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if (Paired.count(PMul0->Root))
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continue;
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@ -424,7 +657,7 @@ void ARMParallelDSP::CreateParallelMACPairs(Reduction &R) {
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if (i == j)
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continue;
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BinOpChain *PMul1 = static_cast<BinOpChain*>(Candidates[j].get());
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BinOpChain *PMul1 = static_cast<BinOpChain*>(Muls[j].get());
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if (Paired.count(PMul1->Root))
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continue;
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@ -435,199 +668,67 @@ void ARMParallelDSP::CreateParallelMACPairs(Reduction &R) {
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assert(PMul0 != PMul1 && "expected different chains");
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if (CanPair(PMul0, PMul1)) {
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if (CanPair(R, PMul0, PMul1)) {
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Paired.insert(Mul0);
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Paired.insert(Mul1);
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break;
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}
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}
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}
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return !R.getMulPairs().empty();
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}
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|
||||
bool ARMParallelDSP::InsertParallelMACs(Reduction &Reduction) {
|
||||
Instruction *Acc = Reduction.Phi;
|
||||
Instruction *InsertAfter = Reduction.AccIntAdd;
|
||||
|
||||
for (auto &Pair : Reduction.PMACPairs) {
|
||||
void ARMParallelDSP::InsertParallelMACs(Reduction &R) {
|
||||
|
||||
auto CreateSMLADCall = [&](SmallVectorImpl<LoadInst*> &VecLd0,
|
||||
SmallVectorImpl<LoadInst*> &VecLd1,
|
||||
Value *Acc, bool Exchange,
|
||||
Instruction *InsertAfter) {
|
||||
// Replace the reduction chain with an intrinsic call
|
||||
IntegerType *Ty = IntegerType::get(M->getContext(), 32);
|
||||
LoadInst *WideLd0 = WideLoads.count(VecLd0[0]) ?
|
||||
WideLoads[VecLd0[0]]->getLoad() : CreateWideLoad(VecLd0, Ty);
|
||||
LoadInst *WideLd1 = WideLoads.count(VecLd1[0]) ?
|
||||
WideLoads[VecLd1[0]]->getLoad() : CreateWideLoad(VecLd1, Ty);
|
||||
|
||||
Value* Args[] = { WideLd0, WideLd1, Acc };
|
||||
Function *SMLAD = nullptr;
|
||||
if (Exchange)
|
||||
SMLAD = Acc->getType()->isIntegerTy(32) ?
|
||||
Intrinsic::getDeclaration(M, Intrinsic::arm_smladx) :
|
||||
Intrinsic::getDeclaration(M, Intrinsic::arm_smlaldx);
|
||||
else
|
||||
SMLAD = Acc->getType()->isIntegerTy(32) ?
|
||||
Intrinsic::getDeclaration(M, Intrinsic::arm_smlad) :
|
||||
Intrinsic::getDeclaration(M, Intrinsic::arm_smlald);
|
||||
|
||||
IRBuilder<NoFolder> Builder(InsertAfter->getParent(),
|
||||
++BasicBlock::iterator(InsertAfter));
|
||||
Instruction *Call = Builder.CreateCall(SMLAD, Args);
|
||||
NumSMLAD++;
|
||||
return Call;
|
||||
};
|
||||
|
||||
Instruction *InsertAfter = R.getRoot();
|
||||
Value *Acc = R.getAccumulator();
|
||||
if (!Acc)
|
||||
Acc = ConstantInt::get(IntegerType::get(M->getContext(), 32), 0);
|
||||
|
||||
LLVM_DEBUG(dbgs() << "Root: " << *InsertAfter << "\n"
|
||||
<< "Acc: " << *Acc << "\n");
|
||||
for (auto &Pair : R.getMulPairs()) {
|
||||
BinOpChain *PMul0 = Pair.first;
|
||||
BinOpChain *PMul1 = Pair.second;
|
||||
LLVM_DEBUG(dbgs() << "Found parallel MACs:\n"
|
||||
LLVM_DEBUG(dbgs() << "Muls:\n"
|
||||
<< "- " << *PMul0->Root << "\n"
|
||||
<< "- " << *PMul1->Root << "\n");
|
||||
|
||||
Acc = CreateSMLADCall(PMul0->VecLd, PMul1->VecLd, Acc, PMul1->Exchange,
|
||||
InsertAfter);
|
||||
InsertAfter = Acc;
|
||||
InsertAfter = cast<Instruction>(Acc);
|
||||
}
|
||||
|
||||
if (Acc != Reduction.Phi) {
|
||||
LLVM_DEBUG(dbgs() << "Replace Accumulate: "; Acc->dump());
|
||||
Reduction.AccIntAdd->replaceAllUsesWith(Acc);
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
template<typename InstType, unsigned BitWidth>
|
||||
bool IsExtendingLoad(Value *V) {
|
||||
auto *I = dyn_cast<InstType>(V);
|
||||
if (!I)
|
||||
return false;
|
||||
|
||||
if (I->getSrcTy()->getIntegerBitWidth() != BitWidth)
|
||||
return false;
|
||||
|
||||
return isa<LoadInst>(I->getOperand(0));
|
||||
}
|
||||
|
||||
static void MatchParallelMACSequences(Reduction &R,
|
||||
OpChainList &Candidates) {
|
||||
Instruction *Acc = R.AccIntAdd;
|
||||
LLVM_DEBUG(dbgs() << "\n- Analysing:\t" << *Acc << "\n");
|
||||
|
||||
// Returns false to signal the search should be stopped.
|
||||
std::function<bool(Value*)> Match =
|
||||
[&Candidates, &Match](Value *V) -> bool {
|
||||
|
||||
auto *I = dyn_cast<Instruction>(V);
|
||||
if (!I)
|
||||
return false;
|
||||
|
||||
switch (I->getOpcode()) {
|
||||
case Instruction::Add:
|
||||
if (Match(I->getOperand(0)) || (Match(I->getOperand(1))))
|
||||
return true;
|
||||
break;
|
||||
case Instruction::Mul: {
|
||||
Value *Op0 = I->getOperand(0);
|
||||
Value *Op1 = I->getOperand(1);
|
||||
if (IsExtendingLoad<SExtInst, 16>(Op0) &&
|
||||
IsExtendingLoad<SExtInst, 16>(Op1)) {
|
||||
ValueList LHS = { cast<SExtInst>(Op0)->getOperand(0), Op0 };
|
||||
ValueList RHS = { cast<SExtInst>(Op1)->getOperand(0), Op1 };
|
||||
Candidates.push_back(make_unique<BinOpChain>(I, LHS, RHS));
|
||||
}
|
||||
return false;
|
||||
}
|
||||
case Instruction::SExt:
|
||||
return Match(I->getOperand(0));
|
||||
}
|
||||
return false;
|
||||
};
|
||||
|
||||
while (Match (Acc));
|
||||
LLVM_DEBUG(dbgs() << "Finished matching MAC sequences, found "
|
||||
<< Candidates.size() << " candidates.\n");
|
||||
}
|
||||
|
||||
static bool CheckMACMemory(OpChainList &Candidates) {
|
||||
for (auto &C : Candidates) {
|
||||
// A mul has 2 operands, and a narrow op consist of sext and a load; thus
|
||||
// we expect at least 4 items in this operand value list.
|
||||
if (C->size() < 4) {
|
||||
LLVM_DEBUG(dbgs() << "Operand list too short.\n");
|
||||
return false;
|
||||
}
|
||||
C->PopulateLoads();
|
||||
ValueList &LHS = static_cast<BinOpChain*>(C.get())->LHS;
|
||||
ValueList &RHS = static_cast<BinOpChain*>(C.get())->RHS;
|
||||
|
||||
// Use +=2 to skip over the expected extend instructions.
|
||||
for (unsigned i = 0, e = LHS.size(); i < e; i += 2) {
|
||||
if (!isa<LoadInst>(LHS[i]) || !isa<LoadInst>(RHS[i]))
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
// Loop Pass that needs to identify integer add/sub reductions of 16-bit vector
|
||||
// multiplications.
|
||||
// To use SMLAD:
|
||||
// 1) we first need to find integer add reduction PHIs,
|
||||
// 2) then from the PHI, look for this pattern:
|
||||
//
|
||||
// acc0 = phi i32 [0, %entry], [%acc1, %loop.body]
|
||||
// ld0 = load i16
|
||||
// sext0 = sext i16 %ld0 to i32
|
||||
// ld1 = load i16
|
||||
// sext1 = sext i16 %ld1 to i32
|
||||
// mul0 = mul %sext0, %sext1
|
||||
// ld2 = load i16
|
||||
// sext2 = sext i16 %ld2 to i32
|
||||
// ld3 = load i16
|
||||
// sext3 = sext i16 %ld3 to i32
|
||||
// mul1 = mul i32 %sext2, %sext3
|
||||
// add0 = add i32 %mul0, %acc0
|
||||
// acc1 = add i32 %add0, %mul1
|
||||
//
|
||||
// Which can be selected to:
|
||||
//
|
||||
// ldr.h r0
|
||||
// ldr.h r1
|
||||
// smlad r2, r0, r1, r2
|
||||
//
|
||||
// If constants are used instead of loads, these will need to be hoisted
|
||||
// out and into a register.
|
||||
//
|
||||
// If loop invariants are used instead of loads, these need to be packed
|
||||
// before the loop begins.
|
||||
//
|
||||
bool ARMParallelDSP::MatchSMLAD(Function &F) {
|
||||
|
||||
auto FindReductions = [&](ReductionList &Reductions) {
|
||||
RecurrenceDescriptor RecDesc;
|
||||
const bool HasFnNoNaNAttr =
|
||||
F.getFnAttribute("no-nans-fp-math").getValueAsString() == "true";
|
||||
BasicBlock *Latch = L->getLoopLatch();
|
||||
|
||||
for (PHINode &Phi : Latch->phis()) {
|
||||
const auto *Ty = Phi.getType();
|
||||
if (!Ty->isIntegerTy(32) && !Ty->isIntegerTy(64))
|
||||
continue;
|
||||
|
||||
const bool IsReduction = RecurrenceDescriptor::AddReductionVar(
|
||||
&Phi, RecurrenceDescriptor::RK_IntegerAdd, L, HasFnNoNaNAttr, RecDesc);
|
||||
|
||||
if (!IsReduction)
|
||||
continue;
|
||||
|
||||
Instruction *Acc = dyn_cast<Instruction>(Phi.getIncomingValueForBlock(Latch));
|
||||
if (!Acc)
|
||||
continue;
|
||||
|
||||
Reductions.push_back(Reduction(&Phi, Acc));
|
||||
}
|
||||
return !Reductions.empty();
|
||||
};
|
||||
|
||||
ReductionList Reductions;
|
||||
if (!FindReductions(Reductions))
|
||||
return false;
|
||||
|
||||
for (auto &R : Reductions) {
|
||||
OpChainList MACCandidates;
|
||||
MatchParallelMACSequences(R, MACCandidates);
|
||||
if (!CheckMACMemory(MACCandidates))
|
||||
continue;
|
||||
|
||||
R.MACCandidates = std::move(MACCandidates);
|
||||
|
||||
LLVM_DEBUG(dbgs() << "MAC candidates:\n";
|
||||
for (auto &M : R.MACCandidates)
|
||||
M->Root->dump();
|
||||
dbgs() << "\n";);
|
||||
}
|
||||
|
||||
bool Changed = false;
|
||||
// Check whether statements in the basic block that write to memory alias
|
||||
// with the memory locations accessed by the MAC-chains.
|
||||
for (auto &R : Reductions) {
|
||||
CreateParallelMACPairs(R);
|
||||
Changed |= InsertParallelMACs(R);
|
||||
}
|
||||
|
||||
return Changed;
|
||||
R.UpdateRoot(cast<Instruction>(Acc));
|
||||
}
|
||||
|
||||
LoadInst* ARMParallelDSP::CreateWideLoad(SmallVectorImpl<LoadInst*> &Loads,
|
||||
@ -696,43 +797,6 @@ LoadInst* ARMParallelDSP::CreateWideLoad(SmallVectorImpl<LoadInst*> &Loads,
|
||||
return WideLoad;
|
||||
}
|
||||
|
||||
Instruction *ARMParallelDSP::CreateSMLADCall(SmallVectorImpl<LoadInst*> &VecLd0,
|
||||
SmallVectorImpl<LoadInst*> &VecLd1,
|
||||
Instruction *Acc, bool Exchange,
|
||||
Instruction *InsertAfter) {
|
||||
LLVM_DEBUG(dbgs() << "Create SMLAD intrinsic using:\n"
|
||||
<< "- " << *VecLd0[0] << "\n"
|
||||
<< "- " << *VecLd0[1] << "\n"
|
||||
<< "- " << *VecLd1[0] << "\n"
|
||||
<< "- " << *VecLd1[1] << "\n"
|
||||
<< "- " << *Acc << "\n"
|
||||
<< "- Exchange: " << Exchange << "\n");
|
||||
|
||||
// Replace the reduction chain with an intrinsic call
|
||||
IntegerType *Ty = IntegerType::get(M->getContext(), 32);
|
||||
LoadInst *WideLd0 = WideLoads.count(VecLd0[0]) ?
|
||||
WideLoads[VecLd0[0]]->getLoad() : CreateWideLoad(VecLd0, Ty);
|
||||
LoadInst *WideLd1 = WideLoads.count(VecLd1[0]) ?
|
||||
WideLoads[VecLd1[0]]->getLoad() : CreateWideLoad(VecLd1, Ty);
|
||||
|
||||
Value* Args[] = { WideLd0, WideLd1, Acc };
|
||||
Function *SMLAD = nullptr;
|
||||
if (Exchange)
|
||||
SMLAD = Acc->getType()->isIntegerTy(32) ?
|
||||
Intrinsic::getDeclaration(M, Intrinsic::arm_smladx) :
|
||||
Intrinsic::getDeclaration(M, Intrinsic::arm_smlaldx);
|
||||
else
|
||||
SMLAD = Acc->getType()->isIntegerTy(32) ?
|
||||
Intrinsic::getDeclaration(M, Intrinsic::arm_smlad) :
|
||||
Intrinsic::getDeclaration(M, Intrinsic::arm_smlald);
|
||||
|
||||
IRBuilder<NoFolder> Builder(InsertAfter->getParent(),
|
||||
++BasicBlock::iterator(InsertAfter));
|
||||
CallInst *Call = Builder.CreateCall(SMLAD, Args);
|
||||
NumSMLAD++;
|
||||
return Call;
|
||||
}
|
||||
|
||||
// Compare the value lists in Other to this chain.
|
||||
bool BinOpChain::AreSymmetrical(BinOpChain *Other) {
|
||||
// Element-by-element comparison of Value lists returning true if they are
|
||||
|
||||
@ -451,8 +451,10 @@ for.body:
|
||||
br i1 %exitcond, label %for.body, label %for.cond.cleanup
|
||||
}
|
||||
|
||||
; TODO: I think we should be able to generate one smlad here. The search fails
|
||||
; when it finds the alias.
|
||||
; CHECK-LABEL: one_pair_alias
|
||||
; FIXME: This tests shows we have a bug with smlad insertion
|
||||
; CHECK-NOT: call i32 @llvm.arm.smlad
|
||||
define i32 @one_pair_alias(i16* noalias nocapture readonly %b, i16* noalias nocapture readonly %c) {
|
||||
entry:
|
||||
br label %for.body
|
||||
|
||||
151
test/CodeGen/ARM/ParallelDSP/inner-full-unroll.ll
Normal file
151
test/CodeGen/ARM/ParallelDSP/inner-full-unroll.ll
Normal file
@ -0,0 +1,151 @@
|
||||
; RUN: opt -mtriple=thumbv7em -arm-parallel-dsp -dce -S %s -o - | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: full_unroll
|
||||
; CHECK: [[IV:%[^ ]+]] = phi i32
|
||||
; CHECK: [[AI:%[^ ]+]] = getelementptr inbounds i32, i32* %a, i32 [[IV]]
|
||||
; CHECK: [[BI:%[^ ]+]] = getelementptr inbounds i16*, i16** %b, i32 [[IV]]
|
||||
; CHECK: [[BIJ:%[^ ]+]] = load i16*, i16** %arrayidx5, align 4
|
||||
; CHECK: [[CI:%[^ ]+]] = getelementptr inbounds i16*, i16** %c, i32 [[IV]]
|
||||
; CHECK: [[CIJ:%[^ ]+]] = load i16*, i16** [[CI]], align 4
|
||||
; CHECK: [[BIJ_CAST:%[^ ]+]] = bitcast i16* [[BIJ]] to i32*
|
||||
; CHECK: [[BIJ_LD:%[^ ]+]] = load i32, i32* [[BIJ_CAST]], align 2
|
||||
; CHECK: [[CIJ_CAST:%[^ ]+]] = bitcast i16* [[CIJ]] to i32*
|
||||
; CHECK: [[CIJ_LD:%[^ ]+]] = load i32, i32* [[CIJ_CAST]], align 2
|
||||
; CHECK: [[BIJ_2:%[^ ]+]] = getelementptr inbounds i16, i16* [[BIJ]], i32 2
|
||||
; CHECK: [[BIJ_2_CAST:%[^ ]+]] = bitcast i16* [[BIJ_2]] to i32*
|
||||
; CHECK: [[BIJ_2_LD:%[^ ]+]] = load i32, i32* [[BIJ_2_CAST]], align 2
|
||||
; CHECK: [[CIJ_2:%[^ ]+]] = getelementptr inbounds i16, i16* [[CIJ]], i32 2
|
||||
; CHECK: [[CIJ_2_CAST:%[^ ]+]] = bitcast i16* [[CIJ_2]] to i32*
|
||||
; CHECK: [[CIJ_2_LD:%[^ ]+]] = load i32, i32* [[CIJ_2_CAST]], align 2
|
||||
; CHECK: [[SMLAD0:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[CIJ_2_LD]], i32 [[BIJ_2_LD]], i32 0)
|
||||
; CHECK: [[SMLAD1:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[CIJ_LD]], i32 [[BIJ_LD]], i32 [[SMLAD0]])
|
||||
; CHECK: store i32 [[SMLAD1]], i32* %arrayidx, align 4
|
||||
|
||||
define void @full_unroll(i32* noalias nocapture %a, i16** noalias nocapture readonly %b, i16** noalias nocapture readonly %c, i32 %N) {
|
||||
entry:
|
||||
%cmp29 = icmp eq i32 %N, 0
|
||||
br i1 %cmp29, label %for.cond.cleanup, label %for.body
|
||||
|
||||
for.cond.cleanup: ; preds = %for.body, %entry
|
||||
ret void
|
||||
|
||||
for.body: ; preds = %entry, %for.body
|
||||
%i.030 = phi i32 [ %inc12, %for.body ], [ 0, %entry ]
|
||||
%arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.030
|
||||
%arrayidx5 = getelementptr inbounds i16*, i16** %b, i32 %i.030
|
||||
%0 = load i16*, i16** %arrayidx5, align 4
|
||||
%arrayidx7 = getelementptr inbounds i16*, i16** %c, i32 %i.030
|
||||
%1 = load i16*, i16** %arrayidx7, align 4
|
||||
%2 = load i16, i16* %0, align 2
|
||||
%conv = sext i16 %2 to i32
|
||||
%3 = load i16, i16* %1, align 2
|
||||
%conv9 = sext i16 %3 to i32
|
||||
%mul = mul nsw i32 %conv9, %conv
|
||||
%arrayidx6.1 = getelementptr inbounds i16, i16* %0, i32 1
|
||||
%4 = load i16, i16* %arrayidx6.1, align 2
|
||||
%conv.1 = sext i16 %4 to i32
|
||||
%arrayidx8.1 = getelementptr inbounds i16, i16* %1, i32 1
|
||||
%5 = load i16, i16* %arrayidx8.1, align 2
|
||||
%conv9.1 = sext i16 %5 to i32
|
||||
%mul.1 = mul nsw i32 %conv9.1, %conv.1
|
||||
%add.1 = add nsw i32 %mul.1, %mul
|
||||
%arrayidx6.2 = getelementptr inbounds i16, i16* %0, i32 2
|
||||
%6 = load i16, i16* %arrayidx6.2, align 2
|
||||
%conv.2 = sext i16 %6 to i32
|
||||
%arrayidx8.2 = getelementptr inbounds i16, i16* %1, i32 2
|
||||
%7 = load i16, i16* %arrayidx8.2, align 2
|
||||
%conv9.2 = sext i16 %7 to i32
|
||||
%mul.2 = mul nsw i32 %conv9.2, %conv.2
|
||||
%add.2 = add nsw i32 %mul.2, %add.1
|
||||
%arrayidx6.3 = getelementptr inbounds i16, i16* %0, i32 3
|
||||
%8 = load i16, i16* %arrayidx6.3, align 2
|
||||
%conv.3 = sext i16 %8 to i32
|
||||
%arrayidx8.3 = getelementptr inbounds i16, i16* %1, i32 3
|
||||
%9 = load i16, i16* %arrayidx8.3, align 2
|
||||
%conv9.3 = sext i16 %9 to i32
|
||||
%mul.3 = mul nsw i32 %conv9.3, %conv.3
|
||||
%add.3 = add nsw i32 %mul.3, %add.2
|
||||
store i32 %add.3, i32* %arrayidx, align 4
|
||||
%inc12 = add nuw i32 %i.030, 1
|
||||
%exitcond = icmp eq i32 %inc12, %N
|
||||
br i1 %exitcond, label %for.cond.cleanup, label %for.body
|
||||
}
|
||||
|
||||
; CHECK-LABEL: full_unroll_sub
|
||||
; CHEC: [[IV:%[^ ]+]] = phi i32
|
||||
; CHECK: [[AI:%[^ ]+]] = getelementptr inbounds i32, i32* %a, i32 [[IV]]
|
||||
; CHECK: [[BI:%[^ ]+]] = getelementptr inbounds i16*, i16** %b, i32 [[IV]]
|
||||
; CHECK: [[BIJ:%[^ ]+]] = load i16*, i16** [[BI]], align 4
|
||||
; CHECK: [[CI:%[^ ]+]] = getelementptr inbounds i16*, i16** %c, i32 [[IV]]
|
||||
; CHECK: [[CIJ:%[^ ]+]] = load i16*, i16** [[CI]], align 4
|
||||
; CHECK: [[BIJ_LD:%[^ ]+]] = load i16, i16* [[BIJ]], align 2
|
||||
; CHECK: [[BIJ_LD_SXT:%[^ ]+]] = sext i16 [[BIJ_LD]] to i32
|
||||
; CHECK: [[CIJ_LD:%[^ ]+]] = load i16, i16* [[CIJ]], align 2
|
||||
; CHECK: [[CIJ_LD_SXT:%[^ ]+]] = sext i16 [[CIJ_LD]] to i32
|
||||
; CHECK: [[SUB:%[^ ]+]] = sub nsw i32 [[CIJ_LD_SXT]], [[BIJ_LD_SXT]]
|
||||
; CHECK: [[BIJ_1:%[^ ]+]] = getelementptr inbounds i16, i16* [[BIJ]], i32 1
|
||||
; CHECK: [[BIJ_1_LD:%[^ ]+]] = load i16, i16* [[BIJ_1]], align 2
|
||||
; CHECK: [[BIJ_1_LD_SXT:%[^ ]+]] = sext i16 [[BIJ_1_LD]] to i32
|
||||
; CHECK: [[CIJ_1:%[^ ]+]] = getelementptr inbounds i16, i16* [[CIJ]], i32 1
|
||||
; CHECK: [[CIJ_1_LD:%[^ ]+]] = load i16, i16* [[CIJ_1]], align 2
|
||||
; CHECK: [[CIJ_1_LD_SXT:%[^ ]+]] = sext i16 [[CIJ_1_LD]] to i32
|
||||
; CHECK: [[MUL:%[^ ]+]] = mul nsw i32 [[CIJ_1_LD_SXT]], [[BIJ_1_LD_SXT]]
|
||||
; CHECK: [[ACC:%[^ ]+]] = add nsw i32 [[MUL]], [[SUB]]
|
||||
; CHECK: [[BIJ_2:%[^ ]+]] = getelementptr inbounds i16, i16* [[BIJ]], i32 2
|
||||
; CHECK: [[BIJ_2_CAST:%[^ ]+]] = bitcast i16* [[BIJ_2]] to i32*
|
||||
; CHECK: [[BIJ_2_LD:%[^ ]+]] = load i32, i32* [[BIJ_2_CAST]], align 2
|
||||
; CHECK: [[CIJ_2:%[^ ]+]] = getelementptr inbounds i16, i16* [[CIJ]], i32 2
|
||||
; CHECK: [[CIJ_2_CAST:%[^ ]+]] = bitcast i16* [[CIJ_2]] to i32*
|
||||
; CHECK: [[CIJ_2_LD:%[^ ]+]] = load i32, i32* [[CIJ_2_CAST]], align 2
|
||||
; CHECK: [[SMLAD0:%[^ ]+]] = call i32 @llvm.arm.smlad(i32 [[CIJ_2_LD]], i32 [[BIJ_2_LD]], i32 [[ACC]])
|
||||
; CHECK: store i32 [[SMLAD0]], i32* %arrayidx, align 4
|
||||
|
||||
define void @full_unroll_sub(i32* noalias nocapture %a, i16** noalias nocapture readonly %b, i16** noalias nocapture readonly %c, i32 %N) {
|
||||
entry:
|
||||
%cmp29 = icmp eq i32 %N, 0
|
||||
br i1 %cmp29, label %for.cond.cleanup, label %for.body
|
||||
|
||||
for.cond.cleanup: ; preds = %for.body, %entry
|
||||
ret void
|
||||
|
||||
for.body: ; preds = %entry, %for.body
|
||||
%i.030 = phi i32 [ %inc12, %for.body ], [ 0, %entry ]
|
||||
%arrayidx = getelementptr inbounds i32, i32* %a, i32 %i.030
|
||||
%arrayidx5 = getelementptr inbounds i16*, i16** %b, i32 %i.030
|
||||
%0 = load i16*, i16** %arrayidx5, align 4
|
||||
%arrayidx7 = getelementptr inbounds i16*, i16** %c, i32 %i.030
|
||||
%1 = load i16*, i16** %arrayidx7, align 4
|
||||
%2 = load i16, i16* %0, align 2
|
||||
%conv = sext i16 %2 to i32
|
||||
%3 = load i16, i16* %1, align 2
|
||||
%conv9 = sext i16 %3 to i32
|
||||
%sub = sub nsw i32 %conv9, %conv
|
||||
%arrayidx6.1 = getelementptr inbounds i16, i16* %0, i32 1
|
||||
%4 = load i16, i16* %arrayidx6.1, align 2
|
||||
%conv.1 = sext i16 %4 to i32
|
||||
%arrayidx8.1 = getelementptr inbounds i16, i16* %1, i32 1
|
||||
%5 = load i16, i16* %arrayidx8.1, align 2
|
||||
%conv9.1 = sext i16 %5 to i32
|
||||
%mul.1 = mul nsw i32 %conv9.1, %conv.1
|
||||
%add.1 = add nsw i32 %mul.1, %sub
|
||||
%arrayidx6.2 = getelementptr inbounds i16, i16* %0, i32 2
|
||||
%6 = load i16, i16* %arrayidx6.2, align 2
|
||||
%conv.2 = sext i16 %6 to i32
|
||||
%arrayidx8.2 = getelementptr inbounds i16, i16* %1, i32 2
|
||||
%7 = load i16, i16* %arrayidx8.2, align 2
|
||||
%conv9.2 = sext i16 %7 to i32
|
||||
%mul.2 = mul nsw i32 %conv9.2, %conv.2
|
||||
%add.2 = add nsw i32 %mul.2, %add.1
|
||||
%arrayidx6.3 = getelementptr inbounds i16, i16* %0, i32 3
|
||||
%8 = load i16, i16* %arrayidx6.3, align 2
|
||||
%conv.3 = sext i16 %8 to i32
|
||||
%arrayidx8.3 = getelementptr inbounds i16, i16* %1, i32 3
|
||||
%9 = load i16, i16* %arrayidx8.3, align 2
|
||||
%conv9.3 = sext i16 %9 to i32
|
||||
%mul.3 = mul nsw i32 %conv9.3, %conv.3
|
||||
%add.3 = add nsw i32 %mul.3, %add.2
|
||||
store i32 %add.3, i32* %arrayidx, align 4
|
||||
%inc12 = add nuw i32 %i.030, 1
|
||||
%exitcond = icmp eq i32 %inc12, %N
|
||||
br i1 %exitcond, label %for.cond.cleanup, label %for.body
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user