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Testcase for better rotate left and mask support
llvm-svn: 30579
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test/Regression/CodeGen/PowerPC/rlwinm2.ll
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30
test/Regression/CodeGen/PowerPC/rlwinm2.ll
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; All of these ands and shifts should be folded into rlw[i]nm instructions
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; RUN: llvm-as < %s | llc -march=ppc32 | not grep and &&
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; RUN: llvm-as < %s | llc -march=ppc32 | not grep srawi &&
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; RUN: llvm-as < %s | llc -march=ppc32 | not grep srwi &&
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; RUN: llvm-as < %s | llc -march=ppc32 | not grep slwi &&
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; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwnm | wc -l | grep 1 &&
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; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwinm | wc -l | grep 1
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implementation ; Functions:
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uint %test1(uint %X, int %Y) {
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entry:
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%tmp = cast int %Y to ubyte ; <ubyte> [#uses=2]
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%tmp1 = shl uint %X, ubyte %tmp ; <uint> [#uses=1]
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%tmp2 = sub ubyte 32, %tmp ; <ubyte> [#uses=1]
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%tmp3 = shr uint %X, ubyte %tmp2 ; <uint> [#uses=1]
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%tmp4 = or uint %tmp1, %tmp3 ; <uint> [#uses=1]
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%tmp6 = and uint %tmp4, 127 ; <uint> [#uses=1]
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ret uint %tmp6
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}
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uint %test2(uint %X) {
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entry:
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%tmp1 = shr uint %X, ubyte 27 ; <uint> [#uses=1]
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%tmp2 = shl uint %X, ubyte 5 ; <uint> [#uses=1]
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%tmp2.masked = and uint %tmp2, 96 ; <uint> [#uses=1]
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%tmp5 = or uint %tmp1, %tmp2.masked ; <uint> [#uses=1]
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ret uint %tmp5
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}
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