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Fix a DAGCombiner abort on an invalid shift count constant. This fixes PR3250.
llvm-svn: 61613
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@ -3277,6 +3277,8 @@ SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
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if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
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// See if we can recursively simplify the LHS.
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unsigned Amt = RHSC->getZExtValue();
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// Watch out for shift count overflow though.
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if (Amt >= Mask.getBitWidth()) break;
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APInt NewMask = Mask << Amt;
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SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
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if (SimplifyLHS.getNode()) {
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17
test/CodeGen/X86/pr3250.ll
Normal file
17
test/CodeGen/X86/pr3250.ll
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@ -0,0 +1,17 @@
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; RUN: llvm-as < %s | llc -march=x86
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; PR3250
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declare i32 @safe_sub_func_short_u_u(i16 signext, i16 signext) nounwind
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define i32 @func_106(i32 %p_107) nounwind {
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entry:
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%0 = tail call i32 (...)* @safe_div_(i32 %p_107, i32 1) nounwind
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; <i32> [#uses=1]
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%1 = lshr i32 %0, -9 ; <i32> [#uses=1]
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%2 = trunc i32 %1 to i16 ; <i16> [#uses=1]
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%3 = tail call i32 @safe_sub_func_short_u_u(i16 signext 1, i16 signext
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%2) nounwind ; <i32> [#uses=0]
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ret i32 undef
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}
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declare i32 @safe_div_(...)
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