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[X86] Add patterns to make blends with immediate control commutable during isel for load folding.
llvm-svn: 313476
This commit is contained in:
Craig Topper
parent
d1020c20b9
commit
2a324415cd
@ -6542,6 +6542,21 @@ multiclass SS41I_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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def BlendCommuteImm2 : SDNodeXForm<imm, [{
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uint8_t Imm = N->getZExtValue() & 0x03;
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return getI8Imm(Imm ^ 0x03, SDLoc(N));
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}]>;
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def BlendCommuteImm4 : SDNodeXForm<imm, [{
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uint8_t Imm = N->getZExtValue() & 0x0f;
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return getI8Imm(Imm ^ 0x0f, SDLoc(N));
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}]>;
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def BlendCommuteImm8 : SDNodeXForm<imm, [{
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uint8_t Imm = N->getZExtValue() & 0xff;
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return getI8Imm(Imm ^ 0xff, SDLoc(N));
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}]>;
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let Predicates = [HasAVX] in {
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let isCommutable = 0 in {
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defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
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@ -6549,26 +6564,6 @@ let Predicates = [HasAVX] in {
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DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_WIG;
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}
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let ExeDomain = SSEPackedSingle in {
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defm VBLENDPS : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v4f32,
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VR128, loadv4f32, f128mem, 0,
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DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_WIG;
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defm VBLENDPSY : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v8f32,
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VR256, loadv8f32, f256mem, 0,
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DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L, VEX_WIG;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VBLENDPD : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v2f64,
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VR128, loadv2f64, f128mem, 0,
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DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_WIG;
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defm VBLENDPDY : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v4f64,
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VR256, loadv4f64, f256mem, 0,
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DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L, VEX_WIG;
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}
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defm VPBLENDW : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v8i16,
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VR128, loadv2i64, i128mem, 0,
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DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_WIG;
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let ExeDomain = SSEPackedSingle in
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defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
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VR128, loadv4f32, f128mem, 0,
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@ -6589,9 +6584,6 @@ let Predicates = [HasAVX2] in {
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VR256, loadv4i64, i256mem, 0,
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DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L, VEX_WIG;
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}
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defm VPBLENDWY : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v16i16,
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VR256, loadv4i64, i256mem, 0,
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DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L, VEX_WIG;
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}
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let Constraints = "$src1 = $dst" in {
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@ -6600,17 +6592,7 @@ let Constraints = "$src1 = $dst" in {
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VR128, memopv2i64, i128mem,
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1, SSE_MPSADBW_ITINS>;
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}
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let ExeDomain = SSEPackedSingle in
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defm BLENDPS : SS41I_binop_rmi<0x0C, "blendps", X86Blendi, v4f32,
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VR128, memopv4f32, f128mem,
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1, SSE_INTALU_ITINS_FBLEND_P>;
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let ExeDomain = SSEPackedDouble in
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defm BLENDPD : SS41I_binop_rmi<0x0D, "blendpd", X86Blendi, v2f64,
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VR128, memopv2f64, f128mem,
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1, SSE_INTALU_ITINS_FBLEND_P>;
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defm PBLENDW : SS41I_binop_rmi<0x0E, "pblendw", X86Blendi, v8i16,
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VR128, memopv2i64, i128mem,
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1, SSE_INTALU_ITINS_BLEND_P>;
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let ExeDomain = SSEPackedSingle in
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defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
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VR128, memopv4f32, f128mem, 1,
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@ -6621,6 +6603,82 @@ let Constraints = "$src1 = $dst" in {
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SSE_DPPD_ITINS>;
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}
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/// SS41I_blend_rmi - SSE 4.1 blend with 8-bit immediate
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multiclass SS41I_blend_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
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X86MemOperand x86memop, bit Is2Addr, Domain d,
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OpndItins itins, SDNodeXForm commuteXForm> {
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let ExeDomain = d, Constraints = !if(Is2Addr, "$src1 = $dst", "") in {
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let isCommutable = 1 in
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def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, u8imm:$src3),
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!if(Is2Addr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))],
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itins.rr>, Sched<[itins.Sched]>;
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def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2, u8imm:$src3),
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!if(Is2Addr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src1,
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(bitconvert (memop_frag addr:$src2)), imm:$src3)))], itins.rm>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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// Pattern to commute if load is in first source.
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def : Pat<(OpVT (OpNode (bitconvert (memop_frag addr:$src2)),
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RC:$src1, imm:$src3)),
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(!cast<Instruction>(NAME#"rmi") RC:$src1, addr:$src2,
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(commuteXForm imm:$src3))>;
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}
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let Predicates = [HasAVX] in {
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defm VBLENDPS : SS41I_blend_rmi<0x0C, "vblendps", X86Blendi, v4f32,
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VR128, loadv4f32, f128mem, 0, SSEPackedSingle,
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DEFAULT_ITINS_FBLENDSCHED, BlendCommuteImm4>,
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VEX_4V, VEX_WIG;
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defm VBLENDPSY : SS41I_blend_rmi<0x0C, "vblendps", X86Blendi, v8f32,
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VR256, loadv8f32, f256mem, 0, SSEPackedSingle,
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DEFAULT_ITINS_FBLENDSCHED, BlendCommuteImm8>,
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VEX_4V, VEX_L, VEX_WIG;
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defm VBLENDPD : SS41I_blend_rmi<0x0D, "vblendpd", X86Blendi, v2f64,
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VR128, loadv2f64, f128mem, 0, SSEPackedDouble,
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DEFAULT_ITINS_FBLENDSCHED, BlendCommuteImm2>,
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VEX_4V, VEX_WIG;
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defm VBLENDPDY : SS41I_blend_rmi<0x0D, "vblendpd", X86Blendi, v4f64,
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VR256, loadv4f64, f256mem, 0, SSEPackedDouble,
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DEFAULT_ITINS_FBLENDSCHED, BlendCommuteImm4>,
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VEX_4V, VEX_L, VEX_WIG;
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defm VPBLENDW : SS41I_blend_rmi<0x0E, "vpblendw", X86Blendi, v8i16,
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VR128, loadv2i64, i128mem, 0, SSEPackedInt,
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DEFAULT_ITINS_BLENDSCHED, BlendCommuteImm8>,
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VEX_4V, VEX_WIG;
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}
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let Predicates = [HasAVX2] in {
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defm VPBLENDWY : SS41I_blend_rmi<0x0E, "vpblendw", X86Blendi, v16i16,
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VR256, loadv4i64, i256mem, 0, SSEPackedInt,
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DEFAULT_ITINS_BLENDSCHED, BlendCommuteImm8>,
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VEX_4V, VEX_L, VEX_WIG;
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}
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defm BLENDPS : SS41I_blend_rmi<0x0C, "blendps", X86Blendi, v4f32,
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VR128, memopv4f32, f128mem, 1, SSEPackedSingle,
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SSE_INTALU_ITINS_FBLEND_P, BlendCommuteImm4>;
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defm BLENDPD : SS41I_blend_rmi<0x0D, "blendpd", X86Blendi, v2f64,
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VR128, memopv2f64, f128mem, 1, SSEPackedDouble,
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SSE_INTALU_ITINS_FBLEND_P, BlendCommuteImm2>;
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defm PBLENDW : SS41I_blend_rmi<0x0E, "pblendw", X86Blendi, v8i16,
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VR128, memopv2i64, i128mem, 1, SSEPackedInt,
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SSE_INTALU_ITINS_BLEND_P, BlendCommuteImm8>;
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// For insertion into the zero index (low half) of a 256-bit vector, it is
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// more efficient to generate a blend with immediate instead of an insert*128.
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let Predicates = [HasAVX] in {
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@ -7810,10 +7868,10 @@ let Predicates = [HasF16C, NoVLX] in {
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// AVX2 Instructions
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//===----------------------------------------------------------------------===//
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/// AVX2_binop_rmi - AVX2 binary operator with 8-bit immediate
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multiclass AVX2_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
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/// AVX2_blend_rmi - AVX2 blend with 8-bit immediate
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multiclass AVX2_blend_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
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X86MemOperand x86memop> {
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X86MemOperand x86memop, SDNodeXForm commuteXForm> {
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let isCommutable = 1 in
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def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, u8imm:$src3),
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@ -7829,12 +7887,19 @@ multiclass AVX2_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
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(OpVT (OpNode RC:$src1,
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(bitconvert (memop_frag addr:$src2)), imm:$src3)))]>,
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Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
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// Pattern to commute if load is in first source.
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def : Pat<(OpVT (OpNode (bitconvert (memop_frag addr:$src2)),
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RC:$src1, imm:$src3)),
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(!cast<Instruction>(NAME#"rmi") RC:$src1, addr:$src2,
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(commuteXForm imm:$src3))>;
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}
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defm VPBLENDD : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v4i32,
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VR128, loadv2i64, i128mem>;
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defm VPBLENDDY : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v8i32,
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VR256, loadv4i64, i256mem>, VEX_L;
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defm VPBLENDD : AVX2_blend_rmi<0x02, "vpblendd", X86Blendi, v4i32,
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VR128, loadv2i64, i128mem, BlendCommuteImm4>;
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defm VPBLENDDY : AVX2_blend_rmi<0x02, "vpblendd", X86Blendi, v8i32,
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VR256, loadv4i64, i256mem, BlendCommuteImm8>,
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VEX_L;
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// For insertion into the zero index (low half) of a 256-bit vector, it is
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// more efficient to generate a blend with immediate instead of an insert*128.
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