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[AMDGPU] Fix check prefix for VOP3 VI disassembler tests

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Also, following D81841, don't try to encode f16 literals in i16/u16
instructions.

Differential Revision: https://reviews.llvm.org/D90242
This commit is contained in:
Jay Foad 2020-10-27 15:14:12 +00:00
parent a330db66de
commit 2a3c18dd52
2 changed files with 28 additions and 28 deletions
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8
test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
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@ -114,8 +114,8 @@
# GFX9: v_mad_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04
# GFX9: v_mad_i16 v5, v1, v2, 0xc400 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x05,0xfe,0x03]
0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03
# GFX9: v_mad_i16 v5, v1, v2, 63 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x05,0xfe,0x02]
0x05,0x00,0x05,0xd2,0x01,0x05,0xfe,0x02
# GFX9: v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x05,0xd2,0x01,0x05,0x0e,0x04]
0x05,0x40,0x05,0xd2,0x01,0x05,0x0e,0x04
@ -174,8 +174,8 @@
# GFX9: v_mad_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04
# GFX9: v_mad_u16 v5, v1, v2, 0xc400 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x05,0xfe,0x03]
0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03
# GFX9: v_mad_u16 v5, v1, v2, 63 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x05,0xfe,0x02]
0x05,0x00,0x04,0xd2,0x01,0x05,0xfe,0x02
# GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x04,0xd2,0x01,0x05,0x0e,0x04]
0x05,0x08,0x04,0xd2,0x01,0x05,0x0e,0x04

48
test/MC/Disassembler/AMDGPU/vop3_vi.txt
View File

@ -261,59 +261,59 @@
# VI: v_fma_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04
# CHECK: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
# VI: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04
# CHECK: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
# VI: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04
# CHECK: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
# VI: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03
# CHECK: v_div_fixup_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
# VI: v_div_fixup_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4
# CHECK: v_div_fixup_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
# VI: v_div_fixup_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04
# CHECK: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
# VI: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04
# CHECK: v_mad_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
# VI: v_mad_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04
# CHECK: v_mad_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
# VI: v_mad_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04
# CHECK: v_mad_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
# VI: v_mad_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03
# CHECK: v_mad_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
# VI: v_mad_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4
# CHECK: v_mad_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
# VI: v_mad_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04
# CHECK: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
# VI: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04
# CHECK: v_mad_i16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0xf0,0x04,0x0e,0x04]
0x05,0x00,0xec,0xd1,0xf0,0x04,0x0e,0x04
# VI: v_mad_i16 v5, -1, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0xc1,0x04,0x0e,0x04]
0x05,0x00,0xec,0xd1,0xc1,0x04,0x0e,0x04
# CHECK: v_mad_i16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0xe1,0x0d,0x04]
0x05,0x00,0xec,0xd1,0x01,0xe1,0x0d,0x04
# VI: v_mad_i16 v5, v1, 20, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x29,0x0d,0x04]
0x05,0x00,0xec,0xd1,0x01,0x29,0x0d,0x04
# CHECK: v_mad_i16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xc2,0x03]
0x05,0x00,0xec,0xd1,0x01,0x05,0xc2,0x03
# VI: v_mad_i16 v5, v1, v2, 63 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfe,0x02]
0x05,0x00,0xec,0xd1,0x01,0x05,0xfe,0x02
# CHECK: v_mad_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04
# VI: v_mad_u16 v5, -1, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0xc1,0x04,0x0e,0x04]
0x05,0x00,0xeb,0xd1,0xc1,0x04,0x0e,0x04
# CHECK: v_mad_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04
# VI: v_mad_u16 v5, v1, 20, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x29,0x0d,0x04]
0x05,0x00,0xeb,0xd1,0x01,0x29,0x0d,0x04
# CHECK: v_mad_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03
# VI: v_mad_u16 v5, v1, v2, 63 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfe,0x02]
0x05,0x00,0xeb,0xd1,0x01,0x05,0xfe,0x02
# VI: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00