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Fix PR12529. The Vxx family of instructions are only supported by AVX.

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Use non-vex instructions for SSE4.

llvm-svn: 154770
This commit is contained in:
Nadav Rotem 2012-04-15 19:36:44 +00:00
parent f6cbb0b2cb
commit 2a4e2ef10c
2 changed files with 14 additions and 4 deletions
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16
lib/Target/X86/X86InstrSSE.td
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@ -6742,6 +6742,16 @@ let Predicates = [HasAVX] in {
def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
(imm:$mask))),
(VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
(imm:$mask))),
(VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
(imm:$mask))),
(VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
(imm:$mask))),
(VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
}
let Predicates = [HasAVX2] in {
@ -6802,13 +6812,13 @@ let Predicates = [HasSSE41] in {
def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
(imm:$mask))),
(VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
(PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
(imm:$mask))),
(VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
(BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
(imm:$mask))),
(VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
(BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
}

2
test/CodeGen/X86/vec_shuffle-20.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -o /dev/null -march=x86 -mcpu=corei7 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 2
; RUN: llc < %s -o /dev/null -march=x86 -mcpu=corei7 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 3
define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) nounwind {
entry: