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[X86-64] Support Intel AMX instructions

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Summary:
INTEL ADVANCED MATRIX EXTENSIONS (AMX).
AMX is a new programming paradigm, it has a set of 2-dimensional registers
(TILES) representing sub-arrays from a larger 2-dimensional memory image and
operate on TILES.

Spec can be found in Chapter 3 here https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Reviewers: LuoYuanke, annita.zhang, pengfei, RKSimon, xiangzhangllvm

Reviewed By: xiangzhangllvm

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82705
This commit is contained in:
Xiang1 Zhang 2020-07-02 08:36:45 +08:00
parent 006e66f9bb
commit 2a61d4a241
34 changed files with 1564 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
include/llvm/Support/X86DisassemblerDecoderCommon.h
View File

@ -323,6 +323,7 @@ typedef uint16_t InstrUID;
ENUM_ENTRY(MODRM_SPLITRM) \ ENUM_ENTRY(MODRM_SPLITRM) \
ENUM_ENTRY(MODRM_SPLITMISC) \ ENUM_ENTRY(MODRM_SPLITMISC) \
ENUM_ENTRY(MODRM_SPLITREG) \ ENUM_ENTRY(MODRM_SPLITREG) \
ENUM_ENTRY(MODRM_SPLITREGM) \
ENUM_ENTRY(MODRM_FULL) ENUM_ENTRY(MODRM_FULL)
#define ENUM_ENTRY(n) n, #define ENUM_ENTRY(n) n,
@ -361,6 +362,7 @@ enum ModRMDecisionType {
ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \ ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \
ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \ ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \
ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \ ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \
ENUM_ENTRY(ENCODING_SIB, "Force SIB operand in ModR/M byte.") \
ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \ ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \
ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \ ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \
ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \ ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \
@ -411,6 +413,7 @@ enum OperandEncoding {
ENUM_ENTRY(TYPE_IMM, "immediate operand") \ ENUM_ENTRY(TYPE_IMM, "immediate operand") \
ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \ ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \
ENUM_ENTRY(TYPE_M, "Memory operand") \ ENUM_ENTRY(TYPE_M, "Memory operand") \
ENUM_ENTRY(TYPE_MSIB, "Memory operand force sib encoding") \
ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \ ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \
ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \ ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \
ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \ ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \
@ -424,6 +427,7 @@ enum OperandEncoding {
ENUM_ENTRY(TYPE_ZMM, "64-byte") \ ENUM_ENTRY(TYPE_ZMM, "64-byte") \
ENUM_ENTRY(TYPE_VK, "mask register") \ ENUM_ENTRY(TYPE_VK, "mask register") \
ENUM_ENTRY(TYPE_VK_PAIR, "mask register pair") \ ENUM_ENTRY(TYPE_VK_PAIR, "mask register pair") \
ENUM_ENTRY(TYPE_TMM, "tile") \
ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \

10
lib/Support/Host.cpp
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@ -1392,8 +1392,8 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
// indicates that the AVX registers will be saved and restored on context // indicates that the AVX registers will be saved and restored on context
// switch, then we have full AVX support. // switch, then we have full AVX support.
bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
!getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6);
#if defined(__APPLE__) #if defined(__APPLE__)
// Darwin lazily saves the AVX512 context on first use: trust that the OS will // Darwin lazily saves the AVX512 context on first use: trust that the OS will
// save the AVX512 context if we use AVX512 instructions, even the bit is not // save the AVX512 context if we use AVX512 instructions, even the bit is not
@ -1403,6 +1403,9 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
// AVX512 requires additional context to be saved by the OS. // AVX512 requires additional context to be saved by the OS.
bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
#endif #endif
// AMX requires additional context to be saved by the OS.
const unsigned AMXBits = (1 << 17) | (1 << 18);
bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits);
Features["avx"] = HasAVXSave; Features["avx"] = HasAVXSave;
Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave; Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
@ -1493,6 +1496,9 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
// detecting features using the "-march=native" flag. // detecting features using the "-march=native" flag.
// For more info, see X86 ISA docs. // For more info, see X86 ISA docs.
Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1); Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
bool HasLeaf7Subleaf1 = bool HasLeaf7Subleaf1 =
MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;

5
lib/Target/X86/AsmParser/X86Operand.h
View File

@ -315,6 +315,11 @@ struct X86Operand final : public MCParsedAsmOperand {
bool isMem512() const { bool isMem512() const {
return Kind == Memory && (!Mem.Size || Mem.Size == 512); return Kind == Memory && (!Mem.Size || Mem.Size == 512);
} }
bool isSibMem() const {
return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP;
}
bool isMemIndexReg(unsigned LowR, unsigned HighR) const { bool isMemIndexReg(unsigned LowR, unsigned HighR) const {
assert(Kind == Memory && "Invalid access!"); assert(Kind == Memory && "Invalid access!");
return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR; return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR;

36
lib/Target/X86/Disassembler/X86Disassembler.cpp
View File

@ -166,6 +166,9 @@ static InstrUID decode(OpcodeType type, InstructionContext insnContext,
if (modFromModRM(modRM) == 0x3) if (modFromModRM(modRM) == 0x3)
return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3) + 8]; return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3) + 8];
return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)]; return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)];
case MODRM_SPLITREGM:
assert(modFromModRM(modRM) == 0x3);
return modRMTable[dec->instructionIDs+(modRM & 0x7)];
case MODRM_SPLITMISC: case MODRM_SPLITMISC:
if (modFromModRM(modRM) == 0x3) if (modFromModRM(modRM) == 0x3)
return modRMTable[dec->instructionIDs + (modRM & 0x3f) + 8]; return modRMTable[dec->instructionIDs + (modRM & 0x3f) + 8];
@ -776,6 +779,10 @@ static int readModRM(struct InternalInstruction *insn) {
return prefix##_YMM0 + index; \ return prefix##_YMM0 + index; \
case TYPE_XMM: \ case TYPE_XMM: \
return prefix##_XMM0 + index; \ return prefix##_XMM0 + index; \
case TYPE_TMM: \
if (index > 7) \
*valid = 0; \
return prefix##_TMM0 + index; \
case TYPE_VK: \ case TYPE_VK: \
index &= 0xf; \ index &= 0xf; \
if (index > 7) \ if (index > 7) \
@ -849,6 +856,7 @@ static int fixupReg(struct InternalInstruction *insn,
if (!valid) if (!valid)
return -1; return -1;
break; break;
case ENCODING_SIB:
CASE_ENCODING_RM: CASE_ENCODING_RM:
if (insn->eaBase >= insn->eaRegBase) { if (insn->eaBase >= insn->eaRegBase) {
insn->eaBase = (EABase)fixupRMValue( insn->eaBase = (EABase)fixupRMValue(
@ -1533,6 +1541,15 @@ static int readOperands(struct InternalInstruction *insn) {
if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB); insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB);
break; break;
case ENCODING_SIB:
// Reject if SIB wasn't used.
if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64)
return -1;
if (readModRM(insn))
return -1;
if (fixupReg(insn, &Op))
return -1;
break;
case ENCODING_REG: case ENCODING_REG:
CASE_ENCODING_RM: CASE_ENCODING_RM:
if (readModRM(insn)) if (readModRM(insn))
@ -2006,9 +2023,11 @@ static bool translateRMRegister(MCInst &mcInst,
/// @param mcInst - The MCInst to append to. /// @param mcInst - The MCInst to append to.
/// @param insn - The instruction to extract Mod, R/M, and SIB fields /// @param insn - The instruction to extract Mod, R/M, and SIB fields
/// from. /// from.
/// @param ForceSIB - The instruction must use SIB.
/// @return - 0 on success; nonzero otherwise /// @return - 0 on success; nonzero otherwise
static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
const MCDisassembler *Dis) { const MCDisassembler *Dis,
bool ForceSIB = false) {
// Addresses in an MCInst are represented as five operands: // Addresses in an MCInst are represented as five operands:
// 1. basereg (register) The R/M base, or (if there is a SIB) the // 1. basereg (register) The R/M base, or (if there is a SIB) the
// SIB base // SIB base
@ -2067,11 +2086,12 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
// -Any base register used other than ESP/RSP/R12D/R12. Using these as a // -Any base register used other than ESP/RSP/R12D/R12. Using these as a
// base always requires a SIB byte. // base always requires a SIB byte.
// -A scale other than 1 is used. // -A scale other than 1 is used.
if (insn.sibScale != 1 || if (!ForceSIB &&
(insn.sibBase == SIB_BASE_NONE && insn.mode != MODE_64BIT) || (insn.sibScale != 1 ||
(insn.sibBase != SIB_BASE_NONE && (insn.sibBase == SIB_BASE_NONE && insn.mode != MODE_64BIT) ||
insn.sibBase != SIB_BASE_ESP && insn.sibBase != SIB_BASE_RSP && (insn.sibBase != SIB_BASE_NONE &&
insn.sibBase != SIB_BASE_R12D && insn.sibBase != SIB_BASE_R12)) { insn.sibBase != SIB_BASE_ESP && insn.sibBase != SIB_BASE_RSP &&
insn.sibBase != SIB_BASE_R12D && insn.sibBase != SIB_BASE_R12))) {
indexReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIZ : indexReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIZ :
X86::RIZ); X86::RIZ);
} else } else
@ -2182,6 +2202,7 @@ static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
case TYPE_XMM: case TYPE_XMM:
case TYPE_YMM: case TYPE_YMM:
case TYPE_ZMM: case TYPE_ZMM:
case TYPE_TMM:
case TYPE_VK_PAIR: case TYPE_VK_PAIR:
case TYPE_VK: case TYPE_VK:
case TYPE_DEBUGREG: case TYPE_DEBUGREG:
@ -2193,6 +2214,8 @@ static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
case TYPE_MVSIBY: case TYPE_MVSIBY:
case TYPE_MVSIBZ: case TYPE_MVSIBZ:
return translateRMMemory(mcInst, insn, Dis); return translateRMMemory(mcInst, insn, Dis);
case TYPE_MSIB:
return translateRMMemory(mcInst, insn, Dis, true);
} }
} }
@ -2242,6 +2265,7 @@ static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
return false; return false;
case ENCODING_WRITEMASK: case ENCODING_WRITEMASK:
return translateMaskRegister(mcInst, insn.writemask); return translateMaskRegister(mcInst, insn.writemask);
case ENCODING_SIB:
CASE_ENCODING_RM: CASE_ENCODING_RM:
CASE_ENCODING_VSIB: CASE_ENCODING_VSIB:
return translateRM(mcInst, operand, insn, Dis); return translateRM(mcInst, operand, insn, Dis);

12
lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
View File

@ -380,6 +380,17 @@ namespace X86Disassembler {
ENTRY(BND2) \ ENTRY(BND2) \
ENTRY(BND3) ENTRY(BND3)
#undef REGS_TMM
#define REGS_TMM \
ENTRY(TMM0) \
ENTRY(TMM1) \
ENTRY(TMM2) \
ENTRY(TMM3) \
ENTRY(TMM4) \
ENTRY(TMM5) \
ENTRY(TMM6) \
ENTRY(TMM7)
#define ALL_EA_BASES \ #define ALL_EA_BASES \
EA_BASES_16BIT \ EA_BASES_16BIT \
EA_BASES_32BIT \ EA_BASES_32BIT \
@ -404,6 +415,7 @@ namespace X86Disassembler {
REGS_DEBUG \ REGS_DEBUG \
REGS_CONTROL \ REGS_CONTROL \
REGS_BOUND \ REGS_BOUND \
REGS_TMM \
ENTRY(RIP) ENTRY(RIP)
/// All possible values of the base field for effective-address /// All possible values of the base field for effective-address

12
lib/Target/X86/MCTargetDesc/X86BaseInfo.h
View File

@ -623,6 +623,15 @@ namespace X86II {
/// information. In the intel manual these are represented as /0, /1, ... /// information. In the intel manual these are represented as /0, /1, ...
/// ///
// Instructions operate on a register Reg/Opcode operand not the r/m field.
MRMr0 = 21,
/// MRMSrcMem - But force to use the SIB field.
MRMSrcMemFSIB = 22,
/// MRMDestMem - But force to use the SIB field.
MRMDestMemFSIB = 23,
/// MRMDestMem - This form is used for instructions that use the Mod/RM byte /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
/// to specify a destination, which in this case is memory. /// to specify a destination, which in this case is memory.
/// ///
@ -1082,8 +1091,10 @@ namespace X86II {
case X86II::PrefixByte: case X86II::PrefixByte:
return -1; return -1;
case X86II::MRMDestMem: case X86II::MRMDestMem:
case X86II::MRMDestMemFSIB:
return 0; return 0;
case X86II::MRMSrcMem: case X86II::MRMSrcMem:
case X86II::MRMSrcMemFSIB:
// Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
// mask register. // mask register.
return 1 + HasVEX_4V + HasEVEX_K; return 1 + HasVEX_4V + HasEVEX_K;
@ -1103,6 +1114,7 @@ namespace X86II {
case X86II::MRMSrcRegOp4: case X86II::MRMSrcRegOp4:
case X86II::MRMSrcRegCC: case X86II::MRMSrcRegCC:
case X86II::MRMXrCC: case X86II::MRMXrCC:
case X86II::MRMr0:
case X86II::MRMXr: case X86II::MRMXr:
case X86II::MRM0r: case X86II::MRM1r: case X86II::MRM0r: case X86II::MRM1r:
case X86II::MRM2r: case X86II::MRM3r: case X86II::MRM2r: case X86II::MRM3r:

40
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View File

@ -78,7 +78,8 @@ private:
void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField, void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
uint64_t TSFlags, bool HasREX, uint64_t StartByte, uint64_t TSFlags, bool HasREX, uint64_t StartByte,
raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI,
bool ForceSIB = false) const;
bool emitPrefixImpl(unsigned &CurOp, const MCInst &MI, bool emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
const MCSubtargetInfo &STI, raw_ostream &OS) const; const MCSubtargetInfo &STI, raw_ostream &OS) const;
@ -382,7 +383,8 @@ void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
uint64_t TSFlags, bool HasREX, uint64_t TSFlags, bool HasREX,
uint64_t StartByte, raw_ostream &OS, uint64_t StartByte, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI,
bool ForceSIB) const {
const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp); const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
const MCOperand &Scale = MI.getOperand(Op + X86::AddrScaleAmt); const MCOperand &Scale = MI.getOperand(Op + X86::AddrScaleAmt);
@ -395,7 +397,8 @@ void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
assert(STI.hasFeature(X86::Mode64Bit) && assert(STI.hasFeature(X86::Mode64Bit) &&
"Rip-relative addressing requires 64-bit mode"); "Rip-relative addressing requires 64-bit mode");
assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); assert(IndexReg.getReg() == 0 && !ForceSIB &&
"Invalid rip-relative address");
emitByte(modRMByte(0, RegOpcodeField, 5), OS); emitByte(modRMByte(0, RegOpcodeField, 5), OS);
unsigned Opcode = MI.getOpcode(); unsigned Opcode = MI.getOpcode();
@ -510,7 +513,7 @@ void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
// 2-7) and absolute references. // 2-7) and absolute references.
if ( // The SIB byte must be used if there is an index register. if ( // The SIB byte must be used if there is an index register.
IndexReg.getReg() == 0 && !ForceSIB && IndexReg.getReg() == 0 &&
// The SIB byte must be used if the base is ESP/RSP/R12, all of which // The SIB byte must be used if the base is ESP/RSP/R12, all of which
// encode to an R/M value of 4, which indicates that a SIB byte is // encode to an R/M value of 4, which indicates that a SIB byte is
// present. // present.
@ -883,9 +886,11 @@ void X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
switch (TSFlags & X86II::FormMask) { switch (TSFlags & X86II::FormMask) {
default: default:
llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!"); llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!");
case X86II::MRM_C0:
case X86II::RawFrm: case X86II::RawFrm:
case X86II::PrefixByte: case X86II::PrefixByte:
break; break;
case X86II::MRMDestMemFSIB:
case X86II::MRMDestMem: { case X86II::MRMDestMem: {
// MRMDestMem instructions forms: // MRMDestMem instructions forms:
// MemAddr, src1(ModR/M) // MemAddr, src1(ModR/M)
@ -916,6 +921,7 @@ void X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
EVEX_R2 = ~(RegEnc >> 4) & 1; EVEX_R2 = ~(RegEnc >> 4) & 1;
break; break;
} }
case X86II::MRMSrcMemFSIB:
case X86II::MRMSrcMem: { case X86II::MRMSrcMem: {
// MRMSrcMem instructions forms: // MRMSrcMem instructions forms:
// src1(ModR/M), MemAddr // src1(ModR/M), MemAddr
@ -1097,6 +1103,15 @@ void X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
EncodeRC = true; EncodeRC = true;
break; break;
} }
case X86II::MRMr0: {
// MRMr0 instructions forms:
// 11:rrr:000
// dst(ModR/M)
unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
VEX_R = ~(RegEnc >> 3) & 1;
EVEX_R2 = ~(RegEnc >> 4) & 1;
break;
}
case X86II::MRM0r: case X86II::MRM0r:
case X86II::MRM1r: case X86II::MRM1r:
case X86II::MRM2r: case X86II::MRM2r:
@ -1267,6 +1282,11 @@ bool X86MCCodeEmitter::emitREXPrefix(int MemOperand, const MCInst &MI,
case X86II::MRM7r: case X86II::MRM7r:
REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B
break; break;
case X86II::MRMr0:
REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R
break;
case X86II::MRMDestMemFSIB:
llvm_unreachable("FSIB format never need REX prefix!");
} }
if (REX && UsesHighByteReg) if (REX && UsesHighByteReg)
report_fatal_error( report_fatal_error(
@ -1481,6 +1501,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
CurOp = SrcRegNum + 1; CurOp = SrcRegNum + 1;
break; break;
} }
case X86II::MRMDestMemFSIB:
case X86II::MRMDestMem: { case X86II::MRMDestMem: {
emitByte(BaseOpcode, OS); emitByte(BaseOpcode, OS);
unsigned SrcRegNum = CurOp + X86::AddrNumOperands; unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
@ -1491,8 +1512,9 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
++SrcRegNum; ++SrcRegNum;
bool ForceSIB = (Form == X86II::MRMDestMemFSIB);
emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(SrcRegNum)), TSFlags, emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(SrcRegNum)), TSFlags,
HasREX, StartByte, OS, Fixups, STI); HasREX, StartByte, OS, Fixups, STI, ForceSIB);
CurOp = SrcRegNum + 1; CurOp = SrcRegNum + 1;
break; break;
} }
@ -1553,6 +1575,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
getX86RegNum(MI.getOperand(FirstOp)), OS); getX86RegNum(MI.getOperand(FirstOp)), OS);
break; break;
} }
case X86II::MRMSrcMemFSIB:
case X86II::MRMSrcMem: { case X86II::MRMSrcMem: {
unsigned FirstMemOp = CurOp + 1; unsigned FirstMemOp = CurOp + 1;
@ -1564,8 +1587,9 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
emitByte(BaseOpcode, OS); emitByte(BaseOpcode, OS);
bool ForceSIB = (Form == X86II::MRMSrcMemFSIB);
emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)), emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
TSFlags, HasREX, StartByte, OS, Fixups, STI); TSFlags, HasREX, StartByte, OS, Fixups, STI, ForceSIB);
CurOp = FirstMemOp + X86::AddrNumOperands; CurOp = FirstMemOp + X86::AddrNumOperands;
if (HasVEX_I8Reg) if (HasVEX_I8Reg)
I8RegNum = getX86RegEncoding(MI, CurOp++); I8RegNum = getX86RegEncoding(MI, CurOp++);
@ -1637,6 +1661,10 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
emitRegModRMByte(MI.getOperand(CurOp++), emitRegModRMByte(MI.getOperand(CurOp++),
(Form == X86II::MRMXr) ? 0 : Form - X86II::MRM0r, OS); (Form == X86II::MRMXr) ? 0 : Form - X86II::MRM0r, OS);
break; break;
case X86II::MRMr0:
emitByte(BaseOpcode, OS);
emitByte(modRMByte(3, getX86RegNum(MI.getOperand(CurOp++)),0), OS);
break;
case X86II::MRMXmCC: { case X86II::MRMXmCC: {
unsigned FirstMemOp = CurOp; unsigned FirstMemOp = CurOp;

8
lib/Target/X86/X86.td
View File

@ -249,6 +249,14 @@ def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
// target-feature attribute. // target-feature attribute.
def FeatureDeprecatedMPX : SubtargetFeature<"mpx", "DeprecatedHasMPX", "false", def FeatureDeprecatedMPX : SubtargetFeature<"mpx", "DeprecatedHasMPX", "false",
"Deprecated. Support MPX instructions">; "Deprecated. Support MPX instructions">;
def FeatureAMXTILE : SubtargetFeature<"amx-tile", "HasAMXTILE", "true",
"Support AMX-TILE instructions">;
def FeatureAMXINT8 : SubtargetFeature<"amx-int8", "HasAMXINT8", "true",
"Support AMX-INT8 instructions",
[FeatureAMXTILE]>;
def FeatureAMXBF16 : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true",
"Support AMX-BF16 instructions",
[FeatureAMXTILE]>;
def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
"Use LEA for adjusting the stack pointer">; "Use LEA for adjusting the stack pointer">;
def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb", def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",

76
lib/Target/X86/X86InstrAMX.td Normal file
View File

@ -0,0 +1,76 @@
//===---- X86InstrAMX.td - AMX Instruction Set Extension --*- tablegen -*--===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file describes the instructions that make up the Intel AMX instruction
// set.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// AMX instructions
let Predicates = [HasAMXTILE, In64BitMode] in {
let SchedRW = [WriteSystem] in {
let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
"ldtilecfg\t$src", []>, VEX, T8PS;
def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
"sttilecfg\t$src", []>, VEX, T8PD;
def TILELOADD : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
(ins sibmem:$src),
"tileloadd\t{$src, $dst|$dst, $src}", []>,
VEX, T8XD;
def TILELOADDT1 : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
(ins sibmem:$src),
"tileloaddt1\t{$src, $dst|$dst, $src}", []>,
VEX, T8PD;
let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),
"tilerelease", []>, VEX, T8PS;
def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs),
(ins sibmem:$dst, TILE:$src),
"tilestored\t{$src, $dst|$dst, $src}", []>,
VEX, T8XS;
def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
"tilezero\t$dst", []>,
VEX, T8XD;
} // SchedRW
} // HasAMXTILE
let Predicates = [HasAMXINT8, In64BitMode] in {
let SchedRW = [WriteSystem] in {
let Constraints = "$src1 = $dst" in {
def TDPBSSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
(ins TILE:$src1, TILE:$src2, TILE:$src3),
"tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
VEX_4V, T8XD;
def TDPBSUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
(ins TILE:$src1, TILE:$src2, TILE:$src3),
"tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
VEX_4V, T8XS;
def TDPBUSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
(ins TILE:$src1, TILE:$src2, TILE:$src3),
"tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
VEX_4V, T8PD;
def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
(ins TILE:$src1, TILE:$src2, TILE:$src3),
"tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
VEX_4V, T8PS;
}
}
} // HasAMXTILE
let Predicates = [HasAMXBF16, In64BitMode] in {
let SchedRW = [WriteSystem] in {
let Constraints = "$src1 = $dst" in
def TDPBF16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
(ins TILE:$src1, TILE:$src2, TILE:$src3),
"tdpbf16ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[]>, VEX_4V, T8XS;
}
} // HasAMXTILE, HasAMXBF16

3
lib/Target/X86/X86InstrFormats.td
View File

@ -28,6 +28,9 @@ def RawFrmImm8 : Format<7>;
def RawFrmImm16 : Format<8>; def RawFrmImm16 : Format<8>;
def AddCCFrm : Format<9>; def AddCCFrm : Format<9>;
def PrefixByte : Format<10>; def PrefixByte : Format<10>;
def MRMr0 : Format<21>;
def MRMSrcMemFSIB : Format<22>;
def MRMDestMemFSIB : Format<23>;
def MRMDestMem : Format<24>; def MRMDestMem : Format<24>;
def MRMSrcMem : Format<25>; def MRMSrcMem : Format<25>;
def MRMSrcMem4VOp3 : Format<26>; def MRMSrcMem4VOp3 : Format<26>;

10
lib/Target/X86/X86InstrInfo.td
View File

@ -361,6 +361,8 @@ let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in {
def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; } def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; }
def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; } def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; }
def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; } def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; }
def X86SibMemOperand : AsmOperandClass { let Name = "SibMem"; }
} }
def X86AbsMemAsmOperand : AsmOperandClass { def X86AbsMemAsmOperand : AsmOperandClass {
@ -392,6 +394,8 @@ def X86any_fcmp : PatFrags<(ops node:$lhs, node:$rhs),
// restrict to only unsized memory. // restrict to only unsized memory.
def opaquemem : X86MemOperand<"printMemReference">; def opaquemem : X86MemOperand<"printMemReference">;
def sibmem: X86MemOperand<"printMemReference", X86SibMemOperand>;
def i8mem : X86MemOperand<"printbytemem", X86Mem8AsmOperand>; def i8mem : X86MemOperand<"printbytemem", X86Mem8AsmOperand>;
def i16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand>; def i16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand>;
def i32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>; def i32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>;
@ -955,6 +959,9 @@ def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">;
def HasENQCMD : Predicate<"Subtarget->hasENQCMD()">; def HasENQCMD : Predicate<"Subtarget->hasENQCMD()">;
def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">; def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">;
def HasTSXLDTRK : Predicate<"Subtarget->hasTSXLDTRK()">; def HasTSXLDTRK : Predicate<"Subtarget->hasTSXLDTRK()">;
def HasAMXTILE : Predicate<"Subtarget->hasAMXTILE()">;
def HasAMXBF16 : Predicate<"Subtarget->hasAMXBF16()">;
def HasAMXINT8 : Predicate<"Subtarget->hasAMXINT8()">;
def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
AssemblerPredicate<(all_of (not Mode64Bit)), "Not 64-bit mode">; AssemblerPredicate<(all_of (not Mode64Bit)), "Not 64-bit mode">;
def In64BitMode : Predicate<"Subtarget->is64Bit()">, def In64BitMode : Predicate<"Subtarget->is64Bit()">,
@ -3070,6 +3077,9 @@ include "X86InstrSVM.td"
include "X86InstrTSX.td" include "X86InstrTSX.td"
include "X86InstrSGX.td" include "X86InstrSGX.td"
// AMX instructions
include "X86InstrAMX.td"
// System instructions. // System instructions.
include "X86InstrSystem.td" include "X86InstrSystem.td"

15
lib/Target/X86/X86RegisterInfo.td
View File

@ -265,6 +265,16 @@ let SubRegIndices = [sub_ymm] in {
} }
} }
// Tile "registers".
def TMM0: X86Reg<"tmm0", 0>;
def TMM1: X86Reg<"tmm1", 1>;
def TMM2: X86Reg<"tmm2", 2>;
def TMM3: X86Reg<"tmm3", 3>;
def TMM4: X86Reg<"tmm4", 4>;
def TMM5: X86Reg<"tmm5", 5>;
def TMM6: X86Reg<"tmm6", 6>;
def TMM7: X86Reg<"tmm7", 7>;
// Mask Registers, used by AVX-512 instructions. // Mask Registers, used by AVX-512 instructions.
def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>; def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>;
def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, 94, 94]>; def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, 94, 94]>;
@ -621,3 +631,8 @@ def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
// Bound registers // Bound registers
def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>; def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>;
// Tiles
let isAllocatable = 0 in
def TILE : RegisterClass<"X86", [untyped], 0,
(sequence "TMM%u", 0, 7)> {let Size = 8192;}

8
lib/Target/X86/X86Subtarget.h
View File

@ -403,6 +403,11 @@ protected:
/// Processor supports TSXLDTRK instruction /// Processor supports TSXLDTRK instruction
bool HasTSXLDTRK = false; bool HasTSXLDTRK = false;
/// Processor has AMX support
bool HasAMXTILE = false;
bool HasAMXBF16 = false;
bool HasAMXINT8 = false;
/// Processor has a single uop BEXTR implementation. /// Processor has a single uop BEXTR implementation.
bool HasFastBEXTR = false; bool HasFastBEXTR = false;
@ -735,6 +740,9 @@ public:
bool useRetpolineIndirectBranches() const { bool useRetpolineIndirectBranches() const {
return UseRetpolineIndirectBranches; return UseRetpolineIndirectBranches;
} }
bool hasAMXTILE() const { return HasAMXTILE; }
bool hasAMXBF16() const { return HasAMXBF16; }
bool hasAMXINT8() const { return HasAMXINT8; }
bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; } bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
// These are generic getters that OR together all of the thunk types // These are generic getters that OR together all of the thunk types

2
test/CodeGen/X86/ipra-reg-usage.ll
View File

@ -3,7 +3,7 @@
target triple = "x86_64-unknown-unknown" target triple = "x86_64-unknown-unknown"
declare void @bar1() declare void @bar1()
define preserve_allcc void @foo()#0 { define preserve_allcc void @foo()#0 {
; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $fpcw $fpsw $fs $gs $hip $ip $mxcsr $rip $riz $ss $ssp $bnd0 $bnd1 $bnd2 $bnd3 $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11bh $r11d $r11w $r11wh ; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $fpcw $fpsw $fs $gs $hip $ip $mxcsr $rip $riz $ss $ssp $bnd0 $bnd1 $bnd2 $bnd3 $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11bh $r11d $r11w $r11wh
call void @bar1() call void @bar1()
call void @bar2() call void @bar2()
ret void ret void

25
test/MC/Disassembler/X86/AMX/x86-64-amx-bf16-att.txt Normal file
View File

@ -0,0 +1,25 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s
# CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x5a,0x5c,0xf5
# CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x72,0x5c,0xda
# CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x5a,0x5c,0xf5
# CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x72,0x5c,0xda
# CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x5a,0x5c,0xf5
# CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x72,0x5c,0xda
# CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x5a,0x5c,0xf5
# CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x72,0x5c,0xda

25
test/MC/Disassembler/X86/AMX/x86-64-amx-bf16-intel.txt Normal file
View File

@ -0,0 +1,25 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s
# CHECK: tdpbf16ps tmm6, tmm5, tmm4
0xc4,0xe2,0x5a,0x5c,0xf5
# CHECK: tdpbf16ps tmm3, tmm2, tmm1
0xc4,0xe2,0x72,0x5c,0xda
# CHECK: tdpbf16ps tmm6, tmm5, tmm4
0xc4,0xe2,0x5a,0x5c,0xf5
# CHECK: tdpbf16ps tmm3, tmm2, tmm1
0xc4,0xe2,0x72,0x5c,0xda
# CHECK: tdpbf16ps tmm6, tmm5, tmm4
0xc4,0xe2,0x5a,0x5c,0xf5
# CHECK: tdpbf16ps tmm3, tmm2, tmm1
0xc4,0xe2,0x72,0x5c,0xda
# CHECK: tdpbf16ps tmm6, tmm5, tmm4
0xc4,0xe2,0x5a,0x5c,0xf5
# CHECK: tdpbf16ps tmm3, tmm2, tmm1
0xc4,0xe2,0x72,0x5c,0xda

4
test/MC/Disassembler/X86/AMX/x86-64-amx-error.txt Normal file
View File

@ -0,0 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 2>&1 | FileCheck %s
# CHECK: invalid instruction encoding
0xc4,0xe2,0x1a,0x5c,0xf5

97
test/MC/Disassembler/X86/AMX/x86-64-amx-int8-att.txt Normal file
View File

@ -0,0 +1,97 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s
# CHECK: tdpbssd %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x5b,0x5e,0xf5
# CHECK: tdpbssd %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x73,0x5e,0xda
# CHECK: tdpbsud %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x5a,0x5e,0xf5
# CHECK: tdpbsud %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x72,0x5e,0xda
# CHECK: tdpbusd %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x59,0x5e,0xf5
# CHECK: tdpbusd %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x71,0x5e,0xda
# CHECK: tdpbuud %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x58,0x5e,0xf5
# CHECK: tdpbuud %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x70,0x5e,0xda
# CHECK: tdpbssd %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x5b,0x5e,0xf5
# CHECK: tdpbssd %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x73,0x5e,0xda
# CHECK: tdpbsud %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x5a,0x5e,0xf5
# CHECK: tdpbsud %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x72,0x5e,0xda
# CHECK: tdpbusd %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x59,0x5e,0xf5
# CHECK: tdpbusd %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x71,0x5e,0xda
# CHECK: tdpbuud %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x58,0x5e,0xf5
# CHECK: tdpbuud %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x70,0x5e,0xda
# CHECK: tdpbssd %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x5b,0x5e,0xf5
# CHECK: tdpbssd %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x73,0x5e,0xda
# CHECK: tdpbsud %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x5a,0x5e,0xf5
# CHECK: tdpbsud %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x72,0x5e,0xda
# CHECK: tdpbusd %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x59,0x5e,0xf5
# CHECK: tdpbusd %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x71,0x5e,0xda
# CHECK: tdpbuud %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x58,0x5e,0xf5
# CHECK: tdpbuud %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x70,0x5e,0xda
# CHECK: tdpbssd %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x5b,0x5e,0xf5
# CHECK: tdpbssd %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x73,0x5e,0xda
# CHECK: tdpbsud %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x5a,0x5e,0xf5
# CHECK: tdpbsud %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x72,0x5e,0xda
# CHECK: tdpbusd %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x59,0x5e,0xf5
# CHECK: tdpbusd %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x71,0x5e,0xda
# CHECK: tdpbuud %tmm4, %tmm5, %tmm6
0xc4,0xe2,0x58,0x5e,0xf5
# CHECK: tdpbuud %tmm1, %tmm2, %tmm3
0xc4,0xe2,0x70,0x5e,0xda

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# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s
# CHECK: tdpbssd tmm6, tmm5, tmm4
0xc4,0xe2,0x5b,0x5e,0xf5
# CHECK: tdpbssd tmm3, tmm2, tmm1
0xc4,0xe2,0x73,0x5e,0xda
# CHECK: tdpbsud tmm6, tmm5, tmm4
0xc4,0xe2,0x5a,0x5e,0xf5
# CHECK: tdpbsud tmm3, tmm2, tmm1
0xc4,0xe2,0x72,0x5e,0xda
# CHECK: tdpbusd tmm6, tmm5, tmm4
0xc4,0xe2,0x59,0x5e,0xf5
# CHECK: tdpbusd tmm3, tmm2, tmm1
0xc4,0xe2,0x71,0x5e,0xda
# CHECK: tdpbuud tmm6, tmm5, tmm4
0xc4,0xe2,0x58,0x5e,0xf5
# CHECK: tdpbuud tmm3, tmm2, tmm1
0xc4,0xe2,0x70,0x5e,0xda
# CHECK: tdpbssd tmm6, tmm5, tmm4
0xc4,0xe2,0x5b,0x5e,0xf5
# CHECK: tdpbssd tmm3, tmm2, tmm1
0xc4,0xe2,0x73,0x5e,0xda
# CHECK: tdpbsud tmm6, tmm5, tmm4
0xc4,0xe2,0x5a,0x5e,0xf5
# CHECK: tdpbsud tmm3, tmm2, tmm1
0xc4,0xe2,0x72,0x5e,0xda
# CHECK: tdpbusd tmm6, tmm5, tmm4
0xc4,0xe2,0x59,0x5e,0xf5
# CHECK: tdpbusd tmm3, tmm2, tmm1
0xc4,0xe2,0x71,0x5e,0xda
# CHECK: tdpbuud tmm6, tmm5, tmm4
0xc4,0xe2,0x58,0x5e,0xf5
# CHECK: tdpbuud tmm3, tmm2, tmm1
0xc4,0xe2,0x70,0x5e,0xda
# CHECK: tdpbssd tmm6, tmm5, tmm4
0xc4,0xe2,0x5b,0x5e,0xf5
# CHECK: tdpbssd tmm3, tmm2, tmm1
0xc4,0xe2,0x73,0x5e,0xda
# CHECK: tdpbsud tmm6, tmm5, tmm4
0xc4,0xe2,0x5a,0x5e,0xf5
# CHECK: tdpbsud tmm3, tmm2, tmm1
0xc4,0xe2,0x72,0x5e,0xda
# CHECK: tdpbusd tmm6, tmm5, tmm4
0xc4,0xe2,0x59,0x5e,0xf5
# CHECK: tdpbusd tmm3, tmm2, tmm1
0xc4,0xe2,0x71,0x5e,0xda
# CHECK: tdpbuud tmm6, tmm5, tmm4
0xc4,0xe2,0x58,0x5e,0xf5
# CHECK: tdpbuud tmm3, tmm2, tmm1
0xc4,0xe2,0x70,0x5e,0xda
# CHECK: tdpbssd tmm6, tmm5, tmm4
0xc4,0xe2,0x5b,0x5e,0xf5
# CHECK: tdpbssd tmm3, tmm2, tmm1
0xc4,0xe2,0x73,0x5e,0xda
# CHECK: tdpbsud tmm6, tmm5, tmm4
0xc4,0xe2,0x5a,0x5e,0xf5
# CHECK: tdpbsud tmm3, tmm2, tmm1
0xc4,0xe2,0x72,0x5e,0xda
# CHECK: tdpbusd tmm6, tmm5, tmm4
0xc4,0xe2,0x59,0x5e,0xf5
# CHECK: tdpbusd tmm3, tmm2, tmm1
0xc4,0xe2,0x71,0x5e,0xda
# CHECK: tdpbuud tmm6, tmm5, tmm4
0xc4,0xe2,0x58,0x5e,0xf5
# CHECK: tdpbuud tmm3, tmm2, tmm1
0xc4,0xe2,0x70,0x5e,0xda

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# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s
# CHECK: tilerelease
0xc4,0xe2,0x78,0x49,0xc0
# CHECK: tilezero %tmm6
0xc4,0xe2,0x7b,0x49,0xf0
# CHECK: tilezero %tmm3
0xc4,0xe2,0x7b,0x49,0xd8
# CHECK: tilezero %tmm6
0xc4,0xe2,0x7b,0x49,0xf0
# CHECK: tilezero %tmm3
0xc4,0xe2,0x7b,0x49,0xd8
# CHECK: ldtilecfg 268435456(%rbp,%r14,8)
0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
# CHECK: ldtilecfg 291(%r8,%rax,4)
0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00
# CHECK: ldtilecfg (%rip)
0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00
# CHECK: ldtilecfg -2048(,%rbp,2)
0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
# CHECK: sttilecfg 268435456(%rbp,%r14,8)
0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
# CHECK: sttilecfg 291(%r8,%rax,4)
0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00
# CHECK: sttilecfg (%rip)
0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00
# CHECK: sttilecfg -2048(,%rbp,2)
0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
# CHECK: tileloadd 268435456(%rbp,%r14,8), %tmm6
0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
# CHECK: tileloadd 291(%r8,%rax,4), %tmm3
0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
# CHECK: tileloadd -32(,%rbp,2), %tmm3
0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
# CHECK: tileloadd 64(%rbx), %tmm4
0xc4,0xe2,0x7b,0x4b,0x64,0x23,0x40
# CHECK: tileloaddt1 268435456(%rbp,%r14,8), %tmm6
0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
# CHECK: tileloaddt1 291(%r8,%rax,4), %tmm3
0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
# CHECK: tileloaddt1 -32(,%rbp,2), %tmm3
0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
# CHECK: tileloaddt1 16(%rbp), %tmm6
0xc4,0xe2,0x79,0x4b,0x74,0x25,0x10
# CHECK: tilerelease
0xc4,0xe2,0x78,0x49,0xc0
# CHECK: tilestored %tmm6, 268435456(%rbp,%r14,8)
0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
# CHECK: tilestored %tmm3, 291(%r8,%rax,4)
0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
# CHECK: tilestored %tmm3, -32(,%rbp,2)
0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
# CHECK: tilezero %tmm6
0xc4,0xe2,0x7b,0x49,0xf0
# CHECK: tilezero %tmm3
0xc4,0xe2,0x7b,0x49,0xd8
# CHECK: ldtilecfg 268435456(%rbp,%r14,8)
0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
# CHECK: ldtilecfg 291(%r8,%rax,4)
0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00
# CHECK: ldtilecfg (%rip)
0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00
# CHECK: ldtilecfg -2048(,%rbp,2)
0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
# CHECK: sttilecfg 268435456(%rbp,%r14,8)
0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
# CHECK: sttilecfg 291(%r8,%rax,4)
0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00
# CHECK: sttilecfg (%rip)
0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00
# CHECK: sttilecfg -2048(,%rbp,2)
0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
# CHECK: tileloadd 268435456(%rbp,%r14,8), %tmm6
0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
# CHECK: tileloadd 291(%r8,%rax,4), %tmm3
0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
# CHECK: tileloadd -32(,%rbp,2), %tmm3
0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
# CHECK: tileloaddt1 268435456(%rbp,%r14,8), %tmm6
0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
# CHECK: tileloaddt1 291(%r8,%rax,4), %tmm3
0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
# CHECK: tileloaddt1 -32(,%rbp,2), %tmm3
0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
# CHECK: tilerelease
0xc4,0xe2,0x78,0x49,0xc0
# CHECK: tilestored %tmm6, 268435456(%rbp,%r14,8)
0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
# CHECK: tilestored %tmm3, 291(%r8,%rax,4)
0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
# CHECK: tilestored %tmm3, -32(,%rbp,2)
0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
# CHECK: tilestored %tmm3, (%r8)
0xc4,0xc2,0x7a,0x4b,0x1c,0x20
# CHECK: tilezero %tmm6
0xc4,0xe2,0x7b,0x49,0xf0
# CHECK: tilezero %tmm3
0xc4,0xe2,0x7b,0x49,0xd8

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# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s
# CHECK: tilerelease
0xc4,0xe2,0x78,0x49,0xc0
# CHECK: tilezero tmm6
0xc4,0xe2,0x7b,0x49,0xf0
# CHECK: tilezero tmm3
0xc4,0xe2,0x7b,0x49,0xd8
# CHECK: tilerelease
0xc4,0xe2,0x78,0x49,0xc0
# CHECK: tilezero tmm6
0xc4,0xe2,0x7b,0x49,0xf0
# CHECK: tilezero tmm3
0xc4,0xe2,0x7b,0x49,0xd8
# CHECK: ldtilecfg [rbp + 8*r14 + 268435456]
0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
# CHECK: ldtilecfg [r8 + 4*rax + 291]
0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00
# CHECK: ldtilecfg [rip]
0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00
# CHECK: ldtilecfg [2*rbp - 2048]
0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
# CHECK: sttilecfg [rbp + 8*r14 + 268435456]
0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
# CHECK: sttilecfg [r8 + 4*rax + 291]
0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00
# CHECK: sttilecfg [rip]
0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00
# CHECK: sttilecfg [2*rbp - 2048]
0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
# CHECK: tileloadd tmm6, [rbp + 8*r14 + 268435456]
0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
# CHECK: tileloadd tmm3, [r8 + 4*rax + 291]
0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
# CHECK: tileloadd tmm3, [2*rbp - 32]
0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
# CHECK: tileloadd tmm4, [rbx + 64]
0xc4,0xe2,0x7b,0x4b,0x64,0x23,0x40
# CHECK: tileloaddt1 tmm6, [rbp + 8*r14 + 268435456]
0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
# CHECK: tileloaddt1 tmm3, [r8 + 4*rax + 291]
0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
# CHECK: tileloaddt1 tmm3, [2*rbp - 32]
0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
# CHECK: tileloaddt1 tmm6, [rbp + 16]
0xc4,0xe2,0x79,0x4b,0x74,0x25,0x10
# CHECK: tilerelease
0xc4,0xe2,0x78,0x49,0xc0
# CHECK: tilestored [rbp + 8*r14 + 268435456], tmm6
0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
# CHECK: tilestored [r8 + 4*rax + 291], tmm3
0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
# CHECK: tilestored [2*rbp - 32], tmm3
0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
# CHECK: tilestored [r8], tmm3
0xc4,0xc2,0x7a,0x4b,0x1c,0x20
# CHECK: tilezero tmm6
0xc4,0xe2,0x7b,0x49,0xf0
# CHECK: tilezero tmm3
0xc4,0xe2,0x7b,0x49,0xd8
# CHECK: ldtilecfg [rbp + 8*r14 + 268435456]
0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
# CHECK: ldtilecfg [r8 + 4*rax + 291]
0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00
# CHECK: ldtilecfg [rip]
0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00
# CHECK: ldtilecfg [2*rbp - 2048]
0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
# CHECK: sttilecfg [rbp + 8*r14 + 268435456]
0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10
# CHECK: sttilecfg [r8 + 4*rax + 291]
0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00
# CHECK: sttilecfg [rip]
0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00
# CHECK: sttilecfg [2*rbp - 2048]
0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff
# CHECK: tileloadd tmm6, [rbp + 8*r14 + 268435456]
0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
# CHECK: tileloadd tmm3, [r8 + 4*rax + 291]
0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
# CHECK: tileloadd tmm3, [2*rbp - 32]
0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
# CHECK: tileloaddt1 tmm6, [rbp + 8*r14 + 268435456]
0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
# CHECK: tileloaddt1 tmm3, [r8 + 4*rax + 291]
0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
# CHECK: tileloaddt1 tmm3, [2*rbp - 32]
0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
# CHECK: tilerelease
0xc4,0xe2,0x78,0x49,0xc0
# CHECK: tilestored [rbp + 8*r14 + 268435456], tmm6
0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10
# CHECK: tilestored [r8 + 4*rax + 291], tmm3
0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00
# CHECK: tilestored [2*rbp - 32], tmm3
0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff
# CHECK: tilezero tmm6
0xc4,0xe2,0x7b,0x49,0xf0
# CHECK: tilezero tmm3
0xc4,0xe2,0x7b,0x49,0xd8

34
test/MC/X86/AMX/x86-64-amx-bf16-att.s Normal file
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// RUN: llvm-mc -triple x86_64-unknown-unknown -show-encoding %s | FileCheck %s
// some AMX instruction must use SIB.
// CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
tdpbf16ps %tmm4, %tmm5, %tmm6
// CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
tdpbf16ps %tmm1, %tmm2, %tmm3
// CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
tdpbf16ps %tmm4, %tmm5, %tmm6
// CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
tdpbf16ps %tmm1, %tmm2, %tmm3
// CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
tdpbf16ps %tmm4, %tmm5, %tmm6
// CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
tdpbf16ps %tmm1, %tmm2, %tmm3
// CHECK: tdpbf16ps %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
tdpbf16ps %tmm4, %tmm5, %tmm6
// CHECK: tdpbf16ps %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
tdpbf16ps %tmm1, %tmm2, %tmm3

33
test/MC/X86/AMX/x86-64-amx-bf16-intel.s Normal file
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// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
// CHECK: tdpbf16ps tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
tdpbf16ps tmm6, tmm5, tmm4
// CHECK: tdpbf16ps tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
tdpbf16ps tmm3, tmm2, tmm1
// CHECK: tdpbf16ps tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
tdpbf16ps tmm6, tmm5, tmm4
// CHECK: tdpbf16ps tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
tdpbf16ps tmm3, tmm2, tmm1
// CHECK: tdpbf16ps tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
tdpbf16ps tmm6, tmm5, tmm4
// CHECK: tdpbf16ps tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
tdpbf16ps tmm3, tmm2, tmm1
// CHECK: tdpbf16ps tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5c,0xf5]
tdpbf16ps tmm6, tmm5, tmm4
// CHECK: tdpbf16ps tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x72,0x5c,0xda]
tdpbf16ps tmm3, tmm2, tmm1

10
test/MC/X86/AMX/x86-64-amx-error.s Normal file
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// RUN: not llvm-mc -triple x86_64-unknown-unknown %s -o /dev/null 2>&1 | FileCheck %s
// CHECK: invalid operand for instruction
tileloadd (%rip), %tmm0
// CHECK: invalid operand for instruction
tileloaddt1 1(%rip), %tmm1
// CHECK: invalid operand for instruction
tilestored %tmm2, (%rip)

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test/MC/X86/AMX/x86-64-amx-int8-att.s Normal file
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// RUN: llvm-mc -triple x86_64-unknown-unknown -show-encoding %s | FileCheck %s
// some AMX instruction must use SIB.
// CHECK: tdpbssd %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
tdpbssd %tmm4, %tmm5, %tmm6
// CHECK: tdpbssd %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
tdpbssd %tmm1, %tmm2, %tmm3
// CHECK: tdpbsud %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
tdpbsud %tmm4, %tmm5, %tmm6
// CHECK: tdpbsud %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
tdpbsud %tmm1, %tmm2, %tmm3
// CHECK: tdpbusd %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
tdpbusd %tmm4, %tmm5, %tmm6
// CHECK: tdpbusd %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
tdpbusd %tmm1, %tmm2, %tmm3
// CHECK: tdpbuud %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
tdpbuud %tmm4, %tmm5, %tmm6
// CHECK: tdpbuud %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
tdpbuud %tmm1, %tmm2, %tmm3
// CHECK: tdpbssd %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
tdpbssd %tmm4, %tmm5, %tmm6
// CHECK: tdpbssd %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
tdpbssd %tmm1, %tmm2, %tmm3
// CHECK: tdpbsud %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
tdpbsud %tmm4, %tmm5, %tmm6
// CHECK: tdpbsud %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
tdpbsud %tmm1, %tmm2, %tmm3
// CHECK: tdpbusd %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
tdpbusd %tmm4, %tmm5, %tmm6
// CHECK: tdpbusd %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
tdpbusd %tmm1, %tmm2, %tmm3
// CHECK: tdpbuud %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
tdpbuud %tmm4, %tmm5, %tmm6
// CHECK: tdpbuud %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
tdpbuud %tmm1, %tmm2, %tmm3
// CHECK: tdpbssd %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
tdpbssd %tmm4, %tmm5, %tmm6
// CHECK: tdpbssd %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
tdpbssd %tmm1, %tmm2, %tmm3
// CHECK: tdpbsud %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
tdpbsud %tmm4, %tmm5, %tmm6
// CHECK: tdpbsud %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
tdpbsud %tmm1, %tmm2, %tmm3
// CHECK: tdpbusd %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
tdpbusd %tmm4, %tmm5, %tmm6
// CHECK: tdpbusd %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
tdpbusd %tmm1, %tmm2, %tmm3
// CHECK: tdpbuud %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
tdpbuud %tmm4, %tmm5, %tmm6
// CHECK: tdpbuud %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
tdpbuud %tmm1, %tmm2, %tmm3
// CHECK: tdpbssd %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
tdpbssd %tmm4, %tmm5, %tmm6
// CHECK: tdpbssd %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
tdpbssd %tmm1, %tmm2, %tmm3
// CHECK: tdpbsud %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
tdpbsud %tmm4, %tmm5, %tmm6
// CHECK: tdpbsud %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
tdpbsud %tmm1, %tmm2, %tmm3
// CHECK: tdpbusd %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
tdpbusd %tmm4, %tmm5, %tmm6
// CHECK: tdpbusd %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
tdpbusd %tmm1, %tmm2, %tmm3
// CHECK: tdpbuud %tmm4, %tmm5, %tmm6
// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
tdpbuud %tmm4, %tmm5, %tmm6
// CHECK: tdpbuud %tmm1, %tmm2, %tmm3
// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
tdpbuud %tmm1, %tmm2, %tmm3

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test/MC/X86/AMX/x86-64-amx-int8-intel.s Normal file
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// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
// CHECK: tdpbssd tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
tdpbssd tmm6, tmm5, tmm4
// CHECK: tdpbssd tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
tdpbssd tmm3, tmm2, tmm1
// CHECK: tdpbsud tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
tdpbsud tmm6, tmm5, tmm4
// CHECK: tdpbsud tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
tdpbsud tmm3, tmm2, tmm1
// CHECK: tdpbusd tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
tdpbusd tmm6, tmm5, tmm4
// CHECK: tdpbusd tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
tdpbusd tmm3, tmm2, tmm1
// CHECK: tdpbuud tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
tdpbuud tmm6, tmm5, tmm4
// CHECK: tdpbuud tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
tdpbuud tmm3, tmm2, tmm1
// CHECK: tdpbssd tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
tdpbssd tmm6, tmm5, tmm4
// CHECK: tdpbssd tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
tdpbssd tmm3, tmm2, tmm1
// CHECK: tdpbsud tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
tdpbsud tmm6, tmm5, tmm4
// CHECK: tdpbsud tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
tdpbsud tmm3, tmm2, tmm1
// CHECK: tdpbusd tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
tdpbusd tmm6, tmm5, tmm4
// CHECK: tdpbusd tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
tdpbusd tmm3, tmm2, tmm1
// CHECK: tdpbuud tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
tdpbuud tmm6, tmm5, tmm4
// CHECK: tdpbuud tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
tdpbuud tmm3, tmm2, tmm1
// CHECK: tdpbssd tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
tdpbssd tmm6, tmm5, tmm4
// CHECK: tdpbssd tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
tdpbssd tmm3, tmm2, tmm1
// CHECK: tdpbsud tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
tdpbsud tmm6, tmm5, tmm4
// CHECK: tdpbsud tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
tdpbsud tmm3, tmm2, tmm1
// CHECK: tdpbusd tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
tdpbusd tmm6, tmm5, tmm4
// CHECK: tdpbusd tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
tdpbusd tmm3, tmm2, tmm1
// CHECK: tdpbuud tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
tdpbuud tmm6, tmm5, tmm4
// CHECK: tdpbuud tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
tdpbuud tmm3, tmm2, tmm1
// CHECK: tdpbssd tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x5b,0x5e,0xf5]
tdpbssd tmm6, tmm5, tmm4
// CHECK: tdpbssd tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x73,0x5e,0xda]
tdpbssd tmm3, tmm2, tmm1
// CHECK: tdpbsud tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x5a,0x5e,0xf5]
tdpbsud tmm6, tmm5, tmm4
// CHECK: tdpbsud tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x72,0x5e,0xda]
tdpbsud tmm3, tmm2, tmm1
// CHECK: tdpbusd tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x59,0x5e,0xf5]
tdpbusd tmm6, tmm5, tmm4
// CHECK: tdpbusd tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x71,0x5e,0xda]
tdpbusd tmm3, tmm2, tmm1
// CHECK: tdpbuud tmm6, tmm5, tmm4
// CHECK: encoding: [0xc4,0xe2,0x58,0x5e,0xf5]
tdpbuud tmm6, tmm5, tmm4
// CHECK: tdpbuud tmm3, tmm2, tmm1
// CHECK: encoding: [0xc4,0xe2,0x70,0x5e,0xda]
tdpbuud tmm3, tmm2, tmm1

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test/MC/X86/AMX/x86-64-amx-tile-att.s Normal file
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// RUN: llvm-mc -triple x86_64-unknown-unknown -show-encoding %s | FileCheck %s
// some AMX instruction must use SIB.
// CHECK: tilerelease
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
tilerelease
// CHECK: tilezero %tmm6
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
tilezero %tmm6
// CHECK: tilezero %tmm3
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
tilezero %tmm3
// CHECK: tilerelease
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
tilerelease
// CHECK: tilezero %tmm6
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
tilezero %tmm6
// CHECK: tilezero %tmm3
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
tilezero %tmm3
// CHECK: ldtilecfg 268435456(%rbp,%r14,8)
// CHECK: encoding: [0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
ldtilecfg 268435456(%rbp,%r14,8)
// CHECK: ldtilecfg 291(%r8,%rax,4)
// CHECK: encoding: [0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
ldtilecfg 291(%r8,%rax,4)
// CHECK: ldtilecfg (%rip)
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00]
ldtilecfg (%rip)
// CHECK: ldtilecfg -2048(,%rbp,2)
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
ldtilecfg -2048(,%rbp,2)
// CHECK: sttilecfg 268435456(%rbp,%r14,8)
// CHECK: encoding: [0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
sttilecfg 268435456(%rbp,%r14,8)
// CHECK: sttilecfg 291(%r8,%rax,4)
// CHECK: encoding: [0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
sttilecfg 291(%r8,%rax,4)
// CHECK: sttilecfg (%rip)
// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00]
sttilecfg (%rip)
// CHECK: sttilecfg -2048(,%rbp,2)
// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
sttilecfg -2048(,%rbp,2)
// CHECK: tileloadd 268435456(%rbp,%r14,8), %tmm6
// CHECK: encoding: [0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
tileloadd 268435456(%rbp,%r14,8), %tmm6
// CHECK: tileloadd 291(%r8,%rax,4), %tmm3
// CHECK: encoding: [0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
tileloadd 291(%r8,%rax,4), %tmm3
// CHECK: tileloadd 64(%rbx), %tmm4
// CHECK: encoding: [0xc4,0xe2,0x7b,0x4b,0x64,0x23,0x40]
tileloadd 64(%rbx), %tmm4
// CHECK: tileloadd -32(,%rbp,2), %tmm3
// CHECK: encoding: [0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tileloadd -32(,%rbp,2), %tmm3
// CHECK: tileloaddt1 268435456(%rbp,%r14,8), %tmm6
// CHECK: encoding: [0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
tileloaddt1 268435456(%rbp,%r14,8), %tmm6
// CHECK: tileloaddt1 291(%r8,%rax,4), %tmm3
// CHECK: encoding: [0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
tileloaddt1 291(%r8,%rax,4), %tmm3
// CHECK: tileloaddt1 -32(,%rbp,2), %tmm3
// CHECK: encoding: [0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tileloaddt1 -32(,%rbp,2), %tmm3
// CHECK: tileloaddt1 16(%rbp), %tmm6
// CHECK: encoding: [0xc4,0xe2,0x79,0x4b,0x74,0x25,0x10]
tileloaddt1 16(%rbp), %tmm6
// CHECK: tilerelease
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
tilerelease
// CHECK: tilestored %tmm6, 268435456(%rbp,%r14,8)
// CHECK: encoding: [0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
tilestored %tmm6, 268435456(%rbp,%r14,8)
// CHECK: tilestored %tmm3, 291(%r8,%rax,4)
// CHECK: encoding: [0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
tilestored %tmm3, 291(%r8,%rax,4)
// CHECK: tilestored %tmm3, -32(,%rbp,2)
// CHECK: encoding: [0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tilestored %tmm3, -32(,%rbp,2)
// CHECK: tilestored %tmm3, (%r8)
// CHECK: encoding: [0xc4,0xc2,0x7a,0x4b,0x1c,0x20]
tilestored %tmm3, (%r8)
// CHECK: tilezero %tmm6
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
tilezero %tmm6
// CHECK: tilezero %tmm3
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
tilezero %tmm3
// CHECK: ldtilecfg 268435456(%rbp,%r14,8)
// CHECK: encoding: [0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
ldtilecfg 268435456(%rbp,%r14,8)
// CHECK: ldtilecfg 291(%r8,%rax,4)
// CHECK: encoding: [0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
ldtilecfg 291(%r8,%rax,4)
// CHECK: ldtilecfg (%rip)
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00]
ldtilecfg (%rip)
// CHECK: ldtilecfg -2048(,%rbp,2)
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
ldtilecfg -2048(,%rbp,2)
// CHECK: sttilecfg 268435456(%rbp,%r14,8)
// CHECK: encoding: [0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
sttilecfg 268435456(%rbp,%r14,8)
// CHECK: sttilecfg 291(%r8,%rax,4)
// CHECK: encoding: [0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
sttilecfg 291(%r8,%rax,4)
// CHECK: sttilecfg (%rip)
// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00]
sttilecfg (%rip)
// CHECK: sttilecfg -2048(,%rbp,2)
// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
sttilecfg -2048(,%rbp,2)
// CHECK: tileloadd 268435456(%rbp,%r14,8), %tmm6
// CHECK: encoding: [0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
tileloadd 268435456(%rbp,%r14,8), %tmm6
// CHECK: tileloadd 291(%r8,%rax,4), %tmm3
// CHECK: encoding: [0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
tileloadd 291(%r8,%rax,4), %tmm3
// CHECK: tileloadd -32(,%rbp,2), %tmm3
// CHECK: encoding: [0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tileloadd -32(,%rbp,2), %tmm3
// CHECK: tileloaddt1 268435456(%rbp,%r14,8), %tmm6
// CHECK: encoding: [0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
tileloaddt1 268435456(%rbp,%r14,8), %tmm6
// CHECK: tileloaddt1 291(%r8,%rax,4), %tmm3
// CHECK: encoding: [0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
tileloaddt1 291(%r8,%rax,4), %tmm3
// CHECK: tileloaddt1 -32(,%rbp,2), %tmm3
// CHECK: encoding: [0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tileloaddt1 -32(,%rbp,2), %tmm3
// CHECK: tilerelease
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
tilerelease
// CHECK: tilestored %tmm6, 268435456(%rbp,%r14,8)
// CHECK: encoding: [0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
tilestored %tmm6, 268435456(%rbp,%r14,8)
// CHECK: tilestored %tmm3, 291(%r8,%rax,4)
// CHECK: encoding: [0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
tilestored %tmm3, 291(%r8,%rax,4)
// CHECK: tilestored %tmm3, -32(,%rbp,2)
// CHECK: encoding: [0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tilestored %tmm3, -32(,%rbp,2)
// CHECK: tilezero %tmm6
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
tilezero %tmm6
// CHECK: tilezero %tmm3
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
tilezero %tmm3

197
test/MC/X86/AMX/x86-64-amx-tile-intel.s Normal file
View File

@ -0,0 +1,197 @@
// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
// CHECK: tilerelease
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
tilerelease
// CHECK: tilezero tmm6
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
tilezero tmm6
// CHECK: tilezero tmm3
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
tilezero tmm3
// CHECK: tilerelease
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
tilerelease
// CHECK: tilezero tmm6
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
tilezero tmm6
// CHECK: tilezero tmm3
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
tilezero tmm3
// CHECK: ldtilecfg [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
ldtilecfg [rbp + 8*r14 + 268435456]
// CHECK: ldtilecfg [r8 + 4*rax + 291]
// CHECK: encoding: [0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
ldtilecfg [r8 + 4*rax + 291]
// CHECK: ldtilecfg [rip]
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00]
ldtilecfg [rip]
// CHECK: ldtilecfg [2*rbp - 2048]
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
ldtilecfg [2*rbp - 2048]
// CHECK: sttilecfg [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
sttilecfg [rbp + 8*r14 + 268435456]
// CHECK: sttilecfg [r8 + 4*rax + 291]
// CHECK: encoding: [0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
sttilecfg [r8 + 4*rax + 291]
// CHECK: sttilecfg [rip]
// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00]
sttilecfg [rip]
// CHECK: sttilecfg [2*rbp - 2048]
// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
sttilecfg [2*rbp - 2048]
// CHECK: tileloadd tmm6, [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
tileloadd tmm6, [rbp + 8*r14 + 268435456]
// CHECK: tileloadd tmm3, [r8 + 4*rax + 291]
// CHECK: encoding: [0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
tileloadd tmm3, [r8 + 4*rax + 291]
// CHECK: tileloadd tmm3, [2*rbp - 32]
// CHECK: encoding: [0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tileloadd tmm3, [2*rbp - 32]
// CHECK: tileloadd tmm4, [rbx + 64]
// CHECK: encoding: [0xc4,0xe2,0x7b,0x4b,0x64,0x23,0x40]
tileloadd tmm4, [rbx + 64]
// CHECK: tileloaddt1 tmm6, [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
tileloaddt1 tmm6, [rbp + 8*r14 + 268435456]
// CHECK: tileloaddt1 tmm3, [r8 + 4*rax + 291]
// CHECK: encoding: [0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
tileloaddt1 tmm3, [r8 + 4*rax + 291]
// CHECK: tileloaddt1 tmm3, [2*rbp - 32]
// CHECK: encoding: [0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tileloaddt1 tmm3, [2*rbp - 32]
// CHECK: tileloaddt1 tmm6, [rbp + 16]
// CHECK: encoding: [0xc4,0xe2,0x79,0x4b,0x74,0x25,0x10]
tileloaddt1 tmm6, [rbp + 16]
// CHECK: tilerelease
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
tilerelease
// CHECK: tilestored [rbp + 8*r14 + 268435456], tmm6
// CHECK: encoding: [0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
tilestored [rbp + 8*r14 + 268435456], tmm6
// CHECK: tilestored [r8 + 4*rax + 291], tmm3
// CHECK: encoding: [0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
tilestored [r8 + 4*rax + 291], tmm3
// CHECK: tilestored [2*rbp - 32], tmm3
// CHECK: encoding: [0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tilestored [2*rbp - 32], tmm3
// CHECK: tilestored [r8], tmm3
// CHECK: encoding: [0xc4,0xc2,0x7a,0x4b,0x1c,0x20]
tilestored [r8], tmm3
// CHECK: tilezero tmm6
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
tilezero tmm6
// CHECK: tilezero tmm3
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
tilezero tmm3
// CHECK: ldtilecfg [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0xc4,0xa2,0x78,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
ldtilecfg [rbp + 8*r14 + 268435456]
// CHECK: ldtilecfg [r8 + 4*rax + 291]
// CHECK: encoding: [0xc4,0xc2,0x78,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
ldtilecfg [r8 + 4*rax + 291]
// CHECK: ldtilecfg [rip]
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x05,0x00,0x00,0x00,0x00]
ldtilecfg [rip]
// CHECK: ldtilecfg [2*rbp - 2048]
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
ldtilecfg [2*rbp - 2048]
// CHECK: sttilecfg [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0xc4,0xa2,0x79,0x49,0x84,0xf5,0x00,0x00,0x00,0x10]
sttilecfg [rbp + 8*r14 + 268435456]
// CHECK: sttilecfg [r8 + 4*rax + 291]
// CHECK: encoding: [0xc4,0xc2,0x79,0x49,0x84,0x80,0x23,0x01,0x00,0x00]
sttilecfg [r8 + 4*rax + 291]
// CHECK: sttilecfg [rip]
// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x05,0x00,0x00,0x00,0x00]
sttilecfg [rip]
// CHECK: sttilecfg [2*rbp - 2048]
// CHECK: encoding: [0xc4,0xe2,0x79,0x49,0x04,0x6d,0x00,0xf8,0xff,0xff]
sttilecfg [2*rbp - 2048]
// CHECK: tileloadd tmm6, [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0xc4,0xa2,0x7b,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
tileloadd tmm6, [rbp + 8*r14 + 268435456]
// CHECK: tileloadd tmm3, [r8 + 4*rax + 291]
// CHECK: encoding: [0xc4,0xc2,0x7b,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
tileloadd tmm3, [r8 + 4*rax + 291]
// CHECK: tileloadd tmm3, [2*rbp - 32]
// CHECK: encoding: [0xc4,0xe2,0x7b,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tileloadd tmm3, [2*rbp - 32]
// CHECK: tileloaddt1 tmm6, [rbp + 8*r14 + 268435456]
// CHECK: encoding: [0xc4,0xa2,0x79,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
tileloaddt1 tmm6, [rbp + 8*r14 + 268435456]
// CHECK: tileloaddt1 tmm3, [r8 + 4*rax + 291]
// CHECK: encoding: [0xc4,0xc2,0x79,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
tileloaddt1 tmm3, [r8 + 4*rax + 291]
// CHECK: tileloaddt1 tmm3, [2*rbp - 32]
// CHECK: encoding: [0xc4,0xe2,0x79,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tileloaddt1 tmm3, [2*rbp - 32]
// CHECK: tilerelease
// CHECK: encoding: [0xc4,0xe2,0x78,0x49,0xc0]
tilerelease
// CHECK: tilestored [rbp + 8*r14 + 268435456], tmm6
// CHECK: encoding: [0xc4,0xa2,0x7a,0x4b,0xb4,0xf5,0x00,0x00,0x00,0x10]
tilestored [rbp + 8*r14 + 268435456], tmm6
// CHECK: tilestored [r8 + 4*rax + 291], tmm3
// CHECK: encoding: [0xc4,0xc2,0x7a,0x4b,0x9c,0x80,0x23,0x01,0x00,0x00]
tilestored [r8 + 4*rax + 291], tmm3
// CHECK: tilestored [2*rbp - 32], tmm3
// CHECK: encoding: [0xc4,0xe2,0x7a,0x4b,0x1c,0x6d,0xe0,0xff,0xff,0xff]
tilestored [2*rbp - 32], tmm3
// CHECK: tilezero tmm6
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xf0]
tilezero tmm6
// CHECK: tilezero tmm3
// CHECK: encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
tilezero tmm3

1
tools/llvm-exegesis/lib/X86/Target.cpp
View File

@ -40,6 +40,7 @@ static const char *isInvalidMemoryInstr(const Instruction &Instr) {
case X86II::MRMSrcRegOp4: case X86II::MRMSrcRegOp4:
case X86II::MRMSrcRegCC: case X86II::MRMSrcRegCC:
case X86II::MRMXrCC: case X86II::MRMXrCC:
case X86II::MRMr0:
case X86II::MRMXr: case X86II::MRMXr:
case X86II::MRM0r: case X86II::MRM0r:
case X86II::MRM1r: case X86II::MRM1r:

15
utils/TableGen/X86DisassemblerTables.cpp
View File

@ -595,6 +595,7 @@ static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
bool satisfiesOneEntry = true; bool satisfiesOneEntry = true;
bool satisfiesSplitRM = true; bool satisfiesSplitRM = true;
bool satisfiesSplitReg = true; bool satisfiesSplitReg = true;
bool satisfiesSplitRegM = true;
bool satisfiesSplitMisc = true; bool satisfiesSplitMisc = true;
for (unsigned index = 0; index < 256; ++index) { for (unsigned index = 0; index < 256; ++index) {
@ -616,6 +617,10 @@ static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
if (((index & 0xc0) != 0xc0) && if (((index & 0xc0) != 0xc0) &&
(decision.instructionIDs[index] != decision.instructionIDs[index&0x38])) (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
satisfiesSplitMisc = false; satisfiesSplitMisc = false;
if (((index & 0xc0) == 0xc0) &&
(decision.instructionIDs[index] != decision.instructionIDs[index&0xc7]))
satisfiesSplitRegM = false;
} }
if (satisfiesOneEntry) if (satisfiesOneEntry)
@ -627,6 +632,9 @@ static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
if (satisfiesSplitReg && satisfiesSplitMisc) if (satisfiesSplitReg && satisfiesSplitMisc)
return MODRM_SPLITREG; return MODRM_SPLITREG;
if (satisfiesSplitRegM)
return MODRM_SPLITREGM;
if (satisfiesSplitMisc) if (satisfiesSplitMisc)
return MODRM_SPLITMISC; return MODRM_SPLITMISC;
@ -691,6 +699,10 @@ void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
for (unsigned index = 0xc0; index < 256; index += 8) for (unsigned index = 0xc0; index < 256; index += 8)
ModRMDecision.push_back(decision.instructionIDs[index]); ModRMDecision.push_back(decision.instructionIDs[index]);
break; break;
case MODRM_SPLITREGM:
for (unsigned index = 0xc0; index < 256; index += 8)
ModRMDecision.push_back(decision.instructionIDs[index]);
break;
case MODRM_SPLITMISC: case MODRM_SPLITMISC:
for (unsigned index = 0; index < 64; index += 8) for (unsigned index = 0; index < 64; index += 8)
ModRMDecision.push_back(decision.instructionIDs[index]); ModRMDecision.push_back(decision.instructionIDs[index]);
@ -732,6 +744,9 @@ void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
case MODRM_SPLITREG: case MODRM_SPLITREG:
sEntryNumber += 16; sEntryNumber += 16;
break; break;
case MODRM_SPLITREGM:
sEntryNumber += 8;
break;
case MODRM_SPLITMISC: case MODRM_SPLITMISC:
sEntryNumber += 8 + 64; sEntryNumber += 8 + 64;
break; break;

2
utils/TableGen/X86ModRMFilters.cpp
View File

@ -18,4 +18,6 @@ void ModFilter::anchor() { }
void ExtendedFilter::anchor() { } void ExtendedFilter::anchor() { }
void ExtendedRMFilter::anchor() { }
void ExactFilter::anchor() { } void ExactFilter::anchor() { }

23
utils/TableGen/X86ModRMFilters.h
View File

@ -108,6 +108,29 @@ public:
} }
}; };
/// ExtendedRMFilter - Extended opcodes are classified based on the value of the
/// mod field [bits 7-6] and the value of the nnn field [bits 2-0].
class ExtendedRMFilter : public ModRMFilter {
void anchor() override;
bool R;
uint8_t NNN;
public:
/// Constructor
///
/// \param r True if the mod field must be set to 11; false otherwise.
/// The name is explained at ModFilter.
/// \param nnn The required value of the nnn field.
ExtendedRMFilter(bool r, uint8_t nnn) :
ModRMFilter(),
R(r),
NNN(nnn) {
}
bool accepts(uint8_t modRM) const override {
return ((R && ((modRM & 0xc0) == 0xc0)) &&
((modRM & 0x7) == NNN));
}
};
/// ExactFilter - The occasional extended opcode (such as VMCALL or MONITOR) /// ExactFilter - The occasional extended opcode (such as VMCALL or MONITOR)
/// requires the ModR/M byte to have a specific value. /// requires the ModR/M byte to have a specific value.
class ExactFilter : public ModRMFilter { class ExactFilter : public ModRMFilter {

23
utils/TableGen/X86RecognizableInstr.cpp
View File

@ -352,10 +352,13 @@ void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
// The scaling factor for AVX512 compressed displacement encoding is an // The scaling factor for AVX512 compressed displacement encoding is an
// instruction attribute. Adjust the ModRM encoding type to include the // instruction attribute. Adjust the ModRM encoding type to include the
// scale for compressed displacement. // scale for compressed displacement.
if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB) ||CD8_Scale == 0) if ((encoding != ENCODING_RM &&
encoding != ENCODING_VSIB &&
encoding != ENCODING_SIB) ||CD8_Scale == 0)
return; return;
encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) ||
(encoding == ENCODING_SIB) ||
(encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) &&
"Invalid CDisp scaling"); "Invalid CDisp scaling");
} }
@ -519,6 +522,7 @@ void RecognizableInstr::emitInstructionSpecifier() {
HANDLE_OPTIONAL(immediate) HANDLE_OPTIONAL(immediate)
break; break;
case X86Local::MRMDestMem: case X86Local::MRMDestMem:
case X86Local::MRMDestMemFSIB:
// Operand 1 is a memory operand (possibly SIB-extended) // Operand 1 is a memory operand (possibly SIB-extended)
// Operand 2 is a register operand in the Reg/Opcode field. // Operand 2 is a register operand in the Reg/Opcode field.
// - In AVX, there is a register operand in the VEX.vvvv field here - // - In AVX, there is a register operand in the VEX.vvvv field here -
@ -589,6 +593,7 @@ void RecognizableInstr::emitInstructionSpecifier() {
HANDLE_OPERAND(opcodeModifier) HANDLE_OPERAND(opcodeModifier)
break; break;
case X86Local::MRMSrcMem: case X86Local::MRMSrcMem:
case X86Local::MRMSrcMemFSIB:
// Operand 1 is a register operand in the Reg/Opcode field. // Operand 1 is a register operand in the Reg/Opcode field.
// Operand 2 is a memory operand (possibly SIB-extended) // Operand 2 is a memory operand (possibly SIB-extended)
// - In AVX, there is a register operand in the VEX.vvvv field here - // - In AVX, there is a register operand in the VEX.vvvv field here -
@ -641,6 +646,10 @@ void RecognizableInstr::emitInstructionSpecifier() {
HANDLE_OPERAND(rmRegister) HANDLE_OPERAND(rmRegister)
HANDLE_OPERAND(opcodeModifier) HANDLE_OPERAND(opcodeModifier)
break; break;
case X86Local::MRMr0:
// Operand 1 is a register operand in the R/M field.
HANDLE_OPERAND(roRegister)
break;
case X86Local::MRMXr: case X86Local::MRMXr:
case X86Local::MRM0r: case X86Local::MRM0r:
case X86Local::MRM1r: case X86Local::MRM1r:
@ -772,7 +781,9 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
filter = std::make_unique<ModFilter>(true); filter = std::make_unique<ModFilter>(true);
break; break;
case X86Local::MRMDestMem: case X86Local::MRMDestMem:
case X86Local::MRMDestMemFSIB:
case X86Local::MRMSrcMem: case X86Local::MRMSrcMem:
case X86Local::MRMSrcMemFSIB:
case X86Local::MRMSrcMem4VOp3: case X86Local::MRMSrcMem4VOp3:
case X86Local::MRMSrcMemOp4: case X86Local::MRMSrcMemOp4:
case X86Local::MRMSrcMemCC: case X86Local::MRMSrcMemCC:
@ -792,6 +803,9 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
case X86Local::MRM6X: case X86Local::MRM7X: case X86Local::MRM6X: case X86Local::MRM7X:
filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X); filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X);
break; break;
case X86Local::MRMr0:
filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0);
break;
case X86Local::MRM0m: case X86Local::MRM1m: case X86Local::MRM0m: case X86Local::MRM1m:
case X86Local::MRM2m: case X86Local::MRM3m: case X86Local::MRM2m: case X86Local::MRM3m:
case X86Local::MRM4m: case X86Local::MRM5m: case X86Local::MRM4m: case X86Local::MRM5m:
@ -911,6 +925,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("i64imm", TYPE_IMM) TYPE("i64imm", TYPE_IMM)
TYPE("anymem", TYPE_M) TYPE("anymem", TYPE_M)
TYPE("opaquemem", TYPE_M) TYPE("opaquemem", TYPE_M)
TYPE("sibmem", TYPE_MSIB)
TYPE("SEGMENT_REG", TYPE_SEGMENTREG) TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
TYPE("DEBUG_REG", TYPE_DEBUGREG) TYPE("DEBUG_REG", TYPE_DEBUGREG)
TYPE("CONTROL_REG", TYPE_CONTROLREG) TYPE("CONTROL_REG", TYPE_CONTROLREG)
@ -969,6 +984,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("vz256mem", TYPE_MVSIBZ) TYPE("vz256mem", TYPE_MVSIBZ)
TYPE("vz512mem", TYPE_MVSIBZ) TYPE("vz512mem", TYPE_MVSIBZ)
TYPE("BNDR", TYPE_BNDR) TYPE("BNDR", TYPE_BNDR)
TYPE("TILE", TYPE_TMM)
errs() << "Unhandled type string " << s << "\n"; errs() << "Unhandled type string " << s << "\n";
llvm_unreachable("Unhandled type string"); llvm_unreachable("Unhandled type string");
} }
@ -1008,6 +1024,7 @@ RecognizableInstr::immediateEncodingFromString(const std::string &s,
ENCODING("VR128X", ENCODING_IB) ENCODING("VR128X", ENCODING_IB)
ENCODING("VR256X", ENCODING_IB) ENCODING("VR256X", ENCODING_IB)
ENCODING("VR512", ENCODING_IB) ENCODING("VR512", ENCODING_IB)
ENCODING("TILE", ENCODING_IB)
errs() << "Unhandled immediate encoding " << s << "\n"; errs() << "Unhandled immediate encoding " << s << "\n";
llvm_unreachable("Unhandled immediate encoding"); llvm_unreachable("Unhandled immediate encoding");
} }
@ -1046,6 +1063,7 @@ RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
ENCODING("VK8PAIR", ENCODING_RM) ENCODING("VK8PAIR", ENCODING_RM)
ENCODING("VK16PAIR", ENCODING_RM) ENCODING("VK16PAIR", ENCODING_RM)
ENCODING("BNDR", ENCODING_RM) ENCODING("BNDR", ENCODING_RM)
ENCODING("TILE", ENCODING_RM)
errs() << "Unhandled R/M register encoding " << s << "\n"; errs() << "Unhandled R/M register encoding " << s << "\n";
llvm_unreachable("Unhandled R/M register encoding"); llvm_unreachable("Unhandled R/M register encoding");
} }
@ -1092,6 +1110,7 @@ RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
ENCODING("VK32WM", ENCODING_REG) ENCODING("VK32WM", ENCODING_REG)
ENCODING("VK64WM", ENCODING_REG) ENCODING("VK64WM", ENCODING_REG)
ENCODING("BNDR", ENCODING_REG) ENCODING("BNDR", ENCODING_REG)
ENCODING("TILE", ENCODING_REG)
errs() << "Unhandled reg/opcode register encoding " << s << "\n"; errs() << "Unhandled reg/opcode register encoding " << s << "\n";
llvm_unreachable("Unhandled reg/opcode register encoding"); llvm_unreachable("Unhandled reg/opcode register encoding");
} }
@ -1123,6 +1142,7 @@ RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
ENCODING("VK4PAIR", ENCODING_VVVV) ENCODING("VK4PAIR", ENCODING_VVVV)
ENCODING("VK8PAIR", ENCODING_VVVV) ENCODING("VK8PAIR", ENCODING_VVVV)
ENCODING("VK16PAIR", ENCODING_VVVV) ENCODING("VK16PAIR", ENCODING_VVVV)
ENCODING("TILE", ENCODING_VVVV)
errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
llvm_unreachable("Unhandled VEX.vvvv register encoding"); llvm_unreachable("Unhandled VEX.vvvv register encoding");
} }
@ -1163,6 +1183,7 @@ RecognizableInstr::memoryEncodingFromString(const std::string &s,
ENCODING("lea64mem", ENCODING_RM) ENCODING("lea64mem", ENCODING_RM)
ENCODING("anymem", ENCODING_RM) ENCODING("anymem", ENCODING_RM)
ENCODING("opaquemem", ENCODING_RM) ENCODING("opaquemem", ENCODING_RM)
ENCODING("sibmem", ENCODING_SIB)
ENCODING("vx64mem", ENCODING_VSIB) ENCODING("vx64mem", ENCODING_VSIB)
ENCODING("vx128mem", ENCODING_VSIB) ENCODING("vx128mem", ENCODING_VSIB)
ENCODING("vx256mem", ENCODING_VSIB) ENCODING("vx256mem", ENCODING_VSIB)

3
utils/TableGen/X86RecognizableInstr.h
View File

@ -103,6 +103,9 @@ namespace X86Local {
RawFrmImm16 = 8, RawFrmImm16 = 8,
AddCCFrm = 9, AddCCFrm = 9,
PrefixByte = 10, PrefixByte = 10,
MRMr0 = 21,
MRMSrcMemFSIB = 22,
MRMDestMemFSIB = 23,
MRMDestMem = 24, MRMDestMem = 24,
MRMSrcMem = 25, MRMSrcMem = 25,
MRMSrcMem4VOp3 = 26, MRMSrcMem4VOp3 = 26,