From 2ae002a01cf9749094c394a7d041662c717a6eae Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Tue, 24 Apr 2018 17:11:37 +0000 Subject: [PATCH] Reland "[mips] Guard traps for microMIPS correctly" This is part of fixing the instruction predicates for MIPS. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44212 This patch relands r327409, hopefully without the problematic part of the tests that cause FileCheck to assert on the windows expensive checks bot. llvm-svn: 330741 --- lib/Target/Mips/MicroMipsInstrInfo.td | 23 ++++++++------ lib/Target/Mips/MipsInstrInfo.td | 44 +++++++++++++++------------ test/MC/Mips/mips2/valid.s | 36 +++++++++++----------- test/MC/Mips/mips3/valid.s | 36 +++++++++++----------- test/MC/Mips/mips32/valid.s | 36 +++++++++++----------- test/MC/Mips/mips32r2/valid.s | 36 +++++++++++----------- test/MC/Mips/mips32r3/valid.s | 36 +++++++++++----------- test/MC/Mips/mips32r5/valid.s | 36 +++++++++++----------- test/MC/Mips/mips4/valid.s | 36 +++++++++++----------- test/MC/Mips/mips5/valid.s | 36 +++++++++++----------- test/MC/Mips/mips64/valid.s | 36 +++++++++++----------- test/MC/Mips/mips64r2/valid.s | 36 +++++++++++----------- test/MC/Mips/mips64r3/valid.s | 36 +++++++++++----------- test/MC/Mips/mips64r5/valid.s | 36 +++++++++++----------- 14 files changed, 255 insertions(+), 244 deletions(-) diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index f1fec5ccd3a..29bc658d6e5 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -959,7 +959,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { GPR32Opnd>, BGEZAL_FM_MM<0x11>; } def B_MM : UncondBranch, IsBranch, ISA_MICROMIPS; -let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { +let DecoderNamespace = "MicroMips" in { + let Predicates = [InMicroMips] in { /// Control Instructions def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM; @@ -973,18 +974,22 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { ISA_MIPS32R2; def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>, ISA_MIPS32R2; + } /// Trap Instructions - def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>; - def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4, II_TGE>, TEQ_FM_MM<0x08>; + def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>, + ISA_MICROMIPS; + def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4, II_TGE>, TEQ_FM_MM<0x08>, + ISA_MICROMIPS; def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4, II_TGEU>, - TEQ_FM_MM<0x10>; - def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4, II_TLT>, TEQ_FM_MM<0x20>; + TEQ_FM_MM<0x10>, ISA_MICROMIPS; + def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4, II_TLT>, TEQ_FM_MM<0x20>, + ISA_MICROMIPS; def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4, II_TLTU>, - TEQ_FM_MM<0x28>; - def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4, II_TNE>, TEQ_FM_MM<0x30>; -} -let DecoderNamespace = "MicroMips" in { + TEQ_FM_MM<0x28>, ISA_MICROMIPS; + def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4, II_TNE>, TEQ_FM_MM<0x30>, + ISA_MICROMIPS; + def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM_MM<0x0e>, ISA_MICROMIPS32_NOT_MIPS32R6; def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM_MM<0x09>, diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index b65f1ab8bff..265ed4d5a46 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -2054,26 +2054,32 @@ let DecoderNamespace = "COP3_" in { } let AdditionalPredicates = [NotInMicroMips] in { - def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>, ISA_MIPS2; - def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10, II_TGE>, TEQ_FM<0x30>, ISA_MIPS2; - def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>, ISA_MIPS2; - def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10, II_TLT>, TEQ_FM<0x32>, ISA_MIPS2; - def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10, II_TLTU>, TEQ_FM<0x33>, ISA_MIPS2; - def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm10, II_TNE>, TEQ_FM<0x36>, ISA_MIPS2; -} + def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>, + ISA_MIPS2; + def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10, II_TGE>, TEQ_FM<0x30>, + ISA_MIPS2; + def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>, + ISA_MIPS2; + def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10, II_TLT>, TEQ_FM<0x32>, + ISA_MIPS2; + def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10, II_TLTU>, TEQ_FM<0x33>, + ISA_MIPS2; + def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm10, II_TNE>, TEQ_FM<0x36>, + ISA_MIPS2; -def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM<0xc>, - ISA_MIPS2_NOT_32R6_64R6; -def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM<0x8>, - ISA_MIPS2_NOT_32R6_64R6; -def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>, TEQI_FM<0x9>, - ISA_MIPS2_NOT_32R6_64R6; -def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM<0xa>, - ISA_MIPS2_NOT_32R6_64R6; -def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>, TEQI_FM<0xb>, - ISA_MIPS2_NOT_32R6_64R6; -def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM<0xe>, - ISA_MIPS2_NOT_32R6_64R6; + def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM<0xc>, + ISA_MIPS2_NOT_32R6_64R6; + def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM<0x8>, + ISA_MIPS2_NOT_32R6_64R6; + def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>, TEQI_FM<0x9>, + ISA_MIPS2_NOT_32R6_64R6; + def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM<0xa>, + ISA_MIPS2_NOT_32R6_64R6; + def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>, TEQI_FM<0xb>, + ISA_MIPS2_NOT_32R6_64R6; + def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM<0xe>, + ISA_MIPS2_NOT_32R6_64R6; +} let AdditionalPredicates = [NotInMicroMips] in { def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>; diff --git a/test/MC/Mips/mips2/valid.s b/test/MC/Mips/mips2/valid.s index c5bf50f5ecc..bb6acd79acc 100644 --- a/test/MC/Mips/mips2/valid.s +++ b/test/MC/Mips/mips2/valid.s @@ -178,15 +178,15 @@ a: sync 0 # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] - teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] - teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] - teqi $s5,-17504 - tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] - tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] - tgei $s1,5025 - tgeiu $sp,-28621 - tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] - tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] + teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] + teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0] + tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] + tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1] + tgeiu $sp, -28621 # CHECK: tgeiu $sp, -28621 # encoding: [0x07,0xa9,0x90,0x33] + tgeu $22, $gp # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20, $14, 379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] # CHECK-NEXT: #