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AArch64/GlobalISel: Cleanup unnecessary size checks in call lowering
The CCValAssign types should now be accurate, so these are no longer necessary.
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6df259fb43
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@ -161,8 +161,6 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
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MachinePointerInfo &MPO, CCValAssign &VA) override {
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MachinePointerInfo &MPO, CCValAssign &VA) override {
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MachineFunction &MF = MIRBuilder.getMF();
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MachineFunction &MF = MIRBuilder.getMF();
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// The reported memory location may be wider than the value.
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const LLT RealRegTy = MRI.getType(ValVReg);
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LLT ValTy(VA.getValVT());
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LLT ValTy(VA.getValVT());
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LLT LocTy(VA.getLocVT());
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LLT LocTy(VA.getLocVT());
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@ -173,15 +171,7 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
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auto MMO = MF.getMachineMemOperand(
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auto MMO = MF.getMachineMemOperand(
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MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, LocTy,
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MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, LocTy,
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inferAlignFromPtrInfo(MF, MPO));
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inferAlignFromPtrInfo(MF, MPO));
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if (RealRegTy.getSizeInBits() == ValTy.getSizeInBits()) {
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// No extension information, or no extension necessary. Load into the
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// incoming parameter type directly.
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MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
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MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
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} else {
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auto Tmp = MIRBuilder.buildLoad(LocTy, Addr, *MMO);
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MIRBuilder.buildTrunc(ValVReg, Tmp);
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}
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}
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}
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/// How the physical register gets marked varies between formal
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/// How the physical register gets marked varies between formal
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@ -302,10 +292,6 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
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}
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}
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ValVReg = extendRegister(ValVReg, VA, MaxSize);
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ValVReg = extendRegister(ValVReg, VA, MaxSize);
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const LLT RegTy = MRI.getType(ValVReg);
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if (RegTy.getSizeInBits() < LocVT.getSizeInBits())
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ValVReg = MIRBuilder.buildTrunc(RegTy, ValVReg).getReg(0);
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} else {
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} else {
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// The store does not cover the full allocated stack slot.
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// The store does not cover the full allocated stack slot.
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MemTy = LLT(VA.getValVT());
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MemTy = LLT(VA.getValVT());
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