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AArch64/GlobalISel: Cleanup unnecessary size checks in call lowering

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The CCValAssign types should now be accurate, so these are no longer
necessary.
This commit is contained in:
Matt Arsenault 2021-07-16 11:10:41 -04:00
parent 6df259fb43
commit 2b17cee2de
1 changed files with 1 additions and 15 deletions
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16
lib/Target/AArch64/GISel/AArch64CallLowering.cpp
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@ -161,8 +161,6 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
MachinePointerInfo &MPO, CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
// The reported memory location may be wider than the value.
const LLT RealRegTy = MRI.getType(ValVReg);
LLT ValTy(VA.getValVT());
LLT LocTy(VA.getLocVT());
@ -173,15 +171,7 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
auto MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, LocTy,
inferAlignFromPtrInfo(MF, MPO));
if (RealRegTy.getSizeInBits() == ValTy.getSizeInBits()) {
// No extension information, or no extension necessary. Load into the
// incoming parameter type directly.
MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
} else {
auto Tmp = MIRBuilder.buildLoad(LocTy, Addr, *MMO);
MIRBuilder.buildTrunc(ValVReg, Tmp);
}
MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
}
/// How the physical register gets marked varies between formal
@ -302,10 +292,6 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
}
ValVReg = extendRegister(ValVReg, VA, MaxSize);
const LLT RegTy = MRI.getType(ValVReg);
if (RegTy.getSizeInBits() < LocVT.getSizeInBits())
ValVReg = MIRBuilder.buildTrunc(RegTy, ValVReg).getReg(0);
} else {
// The store does not cover the full allocated stack slot.
MemTy = LLT(VA.getValVT());