RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00
Code Issues Projects Releases Wiki Activity

Sink codegen optimization level into MCCodeGenInfo along side relocation model

Browse Source 
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.

llvm-svn: 144788
This commit is contained in:
Evan Cheng 2011-11-16 08:38:26 +00:00
parent dbab14b8ea
commit 2b239cbcf6
46 changed files with 344 additions and 313 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
include/llvm/CodeGen/MachineFunctionAnalysis.h
View File

@ -26,17 +26,14 @@ class MachineFunction;
struct MachineFunctionAnalysis : public FunctionPass { struct MachineFunctionAnalysis : public FunctionPass {
private: private:
const TargetMachine &TM; const TargetMachine &TM;
CodeGenOpt::Level OptLevel;
MachineFunction *MF; MachineFunction *MF;
unsigned NextFnNum; unsigned NextFnNum;
public: public:
static char ID; static char ID;
explicit MachineFunctionAnalysis(const TargetMachine &tm, explicit MachineFunctionAnalysis(const TargetMachine &tm);
CodeGenOpt::Level OL = CodeGenOpt::Default);
~MachineFunctionAnalysis(); ~MachineFunctionAnalysis();
MachineFunction &getMF() const { return *MF; } MachineFunction &getMF() const { return *MF; }
CodeGenOpt::Level getOptLevel() const { return OptLevel; }
virtual const char* getPassName() const { virtual const char* getPassName() const {
return "Machine Function Analysis"; return "Machine Function Analysis";

9
include/llvm/MC/MCCodeGenInfo.h
View File

@ -28,13 +28,20 @@ namespace llvm {
/// ///
CodeModel::Model CMModel; CodeModel::Model CMModel;
/// OptLevel - Optimization level.
///
CodeGenOpt::Level OptLevel;
public: public:
void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default, void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default,
CodeModel::Model CM = CodeModel::Default); CodeModel::Model CM = CodeModel::Default,
CodeGenOpt::Level OL = CodeGenOpt::Default);
Reloc::Model getRelocationModel() const { return RelocationModel; } Reloc::Model getRelocationModel() const { return RelocationModel; }
CodeModel::Model getCodeModel() const { return CMModel; } CodeModel::Model getCodeModel() const { return CMModel; }
CodeGenOpt::Level getOptLevel() const { return OptLevel; }
}; };
} // namespace llvm } // namespace llvm

10
include/llvm/Support/CodeGen.h
View File

@ -27,6 +27,16 @@ namespace llvm {
enum Model { Default, JITDefault, Small, Kernel, Medium, Large }; enum Model { Default, JITDefault, Small, Kernel, Medium, Large };
} }
// Code generation optimization level.
namespace CodeGenOpt {
enum Level {
None, // -O0
Less, // -O1
Default, // -O2, -Os
Aggressive // -O3
};
}
} // end llvm namespace } // end llvm namespace
#endif #endif

33
include/llvm/Support/TargetRegistry.h
View File

@ -74,7 +74,8 @@ namespace llvm {
StringRef TT); StringRef TT);
typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT, typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT,
Reloc::Model RM, Reloc::Model RM,
CodeModel::Model CM); CodeModel::Model CM,
CodeGenOpt::Level OL);
typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo*Info); typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo*Info);
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT); typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
@ -86,7 +87,8 @@ namespace llvm {
StringRef CPU, StringRef CPU,
StringRef Features, StringRef Features,
Reloc::Model RM, Reloc::Model RM,
CodeModel::Model CM); CodeModel::Model CM,
CodeGenOpt::Level OL);
typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM, typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM,
MCStreamer &Streamer); MCStreamer &Streamer);
typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, StringRef TT); typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, StringRef TT);
@ -145,8 +147,8 @@ namespace llvm {
/// registered. /// registered.
MCAsmInfoCtorFnTy MCAsmInfoCtorFn; MCAsmInfoCtorFnTy MCAsmInfoCtorFn;
/// MCCodeGenInfoCtorFn - Constructor function for this target's MCCodeGenInfo, /// MCCodeGenInfoCtorFn - Constructor function for this target's
/// if registered. /// MCCodeGenInfo, if registered.
MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn; MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn;
/// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo, /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo,
@ -277,10 +279,11 @@ namespace llvm {
/// createMCCodeGenInfo - Create a MCCodeGenInfo implementation. /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
/// ///
MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM, MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM,
CodeModel::Model CM) const { CodeModel::Model CM,
CodeGenOpt::Level OL) const {
if (!MCCodeGenInfoCtorFn) if (!MCCodeGenInfoCtorFn)
return 0; return 0;
return MCCodeGenInfoCtorFn(Triple, RM, CM); return MCCodeGenInfoCtorFn(Triple, RM, CM, OL);
} }
/// createMCInstrInfo - Create a MCInstrInfo implementation. /// createMCInstrInfo - Create a MCInstrInfo implementation.
@ -331,12 +334,13 @@ namespace llvm {
/// either the target triple from the module, or the target triple of the /// either the target triple from the module, or the target triple of the
/// host if that does not exist. /// host if that does not exist.
TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU, TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU,
StringRef Features, StringRef Features,
Reloc::Model RM = Reloc::Default, Reloc::Model RM = Reloc::Default,
CodeModel::Model CM = CodeModel::Default) const { CodeModel::Model CM = CodeModel::Default,
CodeGenOpt::Level OL = CodeGenOpt::Default) const {
if (!TargetMachineCtorFn) if (!TargetMachineCtorFn)
return 0; return 0;
return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM); return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM, OL);
} }
/// createMCAsmBackend - Create a target specific assembly parser. /// createMCAsmBackend - Create a target specific assembly parser.
@ -843,8 +847,8 @@ namespace llvm {
TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator); TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator);
} }
private: private:
static MCCodeGenInfo *Allocator(StringRef TT, static MCCodeGenInfo *Allocator(StringRef TT, Reloc::Model RM,
Reloc::Model RM, CodeModel::Model CM) { CodeModel::Model CM, CodeGenOpt::Level OL) {
return new MCCodeGenInfoImpl(); return new MCCodeGenInfoImpl();
} }
}; };
@ -1014,8 +1018,9 @@ namespace llvm {
static TargetMachine *Allocator(const Target &T, StringRef TT, static TargetMachine *Allocator(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, Reloc::Model RM,
CodeModel::Model CM) { CodeModel::Model CM,
return new TargetMachineImpl(T, TT, CPU, FS, RM, CM); CodeGenOpt::Level OL) {
return new TargetMachineImpl(T, TT, CPU, FS, RM, CM, OL);
} }
}; };

42
include/llvm/Target/TargetMachine.h
View File

@ -43,16 +43,6 @@ class TargetSubtargetInfo;
class formatted_raw_ostream; class formatted_raw_ostream;
class raw_ostream; class raw_ostream;
// Code generation optimization level.
namespace CodeGenOpt {
enum Level {
None, // -O0
Less, // -O1
Default, // -O2, -Os
Aggressive // -O3
};
}
namespace Sched { namespace Sched {
enum Preference { enum Preference {
None, // No preference None, // No preference
@ -212,6 +202,10 @@ public:
/// medium, large, and target default. /// medium, large, and target default.
CodeModel::Model getCodeModel() const; CodeModel::Model getCodeModel() const;
/// getOptLevel - Returns the optimization level: None, Less,
/// Default, or Aggressive.
CodeGenOpt::Level getOptLevel() const;
/// getAsmVerbosityDefault - Returns the default value of asm verbosity. /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
/// ///
static bool getAsmVerbosityDefault(); static bool getAsmVerbosityDefault();
@ -255,7 +249,6 @@ public:
virtual bool addPassesToEmitFile(PassManagerBase &, virtual bool addPassesToEmitFile(PassManagerBase &,
formatted_raw_ostream &, formatted_raw_ostream &,
CodeGenFileType, CodeGenFileType,
CodeGenOpt::Level,
bool = true) { bool = true) {
return true; return true;
} }
@ -268,7 +261,6 @@ public:
/// ///
virtual bool addPassesToEmitMachineCode(PassManagerBase &, virtual bool addPassesToEmitMachineCode(PassManagerBase &,
JITCodeEmitter &, JITCodeEmitter &,
CodeGenOpt::Level,
bool = true) { bool = true) {
return true; return true;
} }
@ -281,7 +273,6 @@ public:
virtual bool addPassesToEmitMC(PassManagerBase &, virtual bool addPassesToEmitMC(PassManagerBase &,
MCContext *&, MCContext *&,
raw_ostream &, raw_ostream &,
CodeGenOpt::Level,
bool = true) { bool = true) {
return true; return true;
} }
@ -294,24 +285,23 @@ class LLVMTargetMachine : public TargetMachine {
protected: // Can only create subclasses. protected: // Can only create subclasses.
LLVMTargetMachine(const Target &T, StringRef TargetTriple, LLVMTargetMachine(const Target &T, StringRef TargetTriple,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
private: private:
/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
/// both emitting to assembly files or machine code output. /// both emitting to assembly files or machine code output.
/// ///
bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level, bool addCommonCodeGenPasses(PassManagerBase &,
bool DisableVerify, MCContext *&OutCtx); bool DisableVerify, MCContext *&OutCtx);
public: public:
/// addPassesToEmitFile - Add passes to the specified pass manager to get the /// addPassesToEmitFile - Add passes to the specified pass manager to get the
/// specified file emitted. Typically this will involve several steps of code /// specified file emitted. Typically this will involve several steps of code
/// generation. If OptLevel is None, the code generator should emit code as /// generation.
/// fast as possible, though the generated code may be less efficient.
virtual bool addPassesToEmitFile(PassManagerBase &PM, virtual bool addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out, formatted_raw_ostream &Out,
CodeGenFileType FileType, CodeGenFileType FileType,
CodeGenOpt::Level,
bool DisableVerify = true); bool DisableVerify = true);
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
@ -322,7 +312,6 @@ public:
/// ///
virtual bool addPassesToEmitMachineCode(PassManagerBase &PM, virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
JITCodeEmitter &MCE, JITCodeEmitter &MCE,
CodeGenOpt::Level,
bool DisableVerify = true); bool DisableVerify = true);
/// addPassesToEmitMC - Add passes to the specified pass manager to get /// addPassesToEmitMC - Add passes to the specified pass manager to get
@ -333,27 +322,26 @@ public:
virtual bool addPassesToEmitMC(PassManagerBase &PM, virtual bool addPassesToEmitMC(PassManagerBase &PM,
MCContext *&Ctx, MCContext *&Ctx,
raw_ostream &OS, raw_ostream &OS,
CodeGenOpt::Level OptLevel,
bool DisableVerify = true); bool DisableVerify = true);
/// Target-Independent Code Generator Pass Configuration Options. /// Target-Independent Code Generator Pass Configuration Options.
/// addPreISelPasses - This method should add any "last minute" LLVM->LLVM /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
/// passes (which are run just before instruction selector). /// passes (which are run just before instruction selector).
virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) { virtual bool addPreISel(PassManagerBase &) {
return true; return true;
} }
/// addInstSelector - This method should install an instruction selector pass, /// addInstSelector - This method should install an instruction selector pass,
/// which converts from LLVM code to machine instructions. /// which converts from LLVM code to machine instructions.
virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) { virtual bool addInstSelector(PassManagerBase &) {
return true; return true;
} }
/// addPreRegAlloc - This method may be implemented by targets that want to /// addPreRegAlloc - This method may be implemented by targets that want to
/// run passes immediately before register allocation. This should return /// run passes immediately before register allocation. This should return
/// true if -print-machineinstrs should print after these passes. /// true if -print-machineinstrs should print after these passes.
virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) { virtual bool addPreRegAlloc(PassManagerBase &) {
return false; return false;
} }
@ -361,7 +349,7 @@ public:
/// to run passes after register allocation but before prolog-epilog /// to run passes after register allocation but before prolog-epilog
/// insertion. This should return true if -print-machineinstrs should print /// insertion. This should return true if -print-machineinstrs should print
/// after these passes. /// after these passes.
virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) { virtual bool addPostRegAlloc(PassManagerBase &) {
return false; return false;
} }
@ -369,14 +357,14 @@ public:
/// run passes after prolog-epilog insertion and before the second instruction /// run passes after prolog-epilog insertion and before the second instruction
/// scheduling pass. This should return true if -print-machineinstrs should /// scheduling pass. This should return true if -print-machineinstrs should
/// print after these passes. /// print after these passes.
virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) { virtual bool addPreSched2(PassManagerBase &) {
return false; return false;
} }
/// addPreEmitPass - This pass may be implemented by targets that want to run /// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return /// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes. /// true if -print-machineinstrs should print out the code after the passes.
virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) { virtual bool addPreEmitPass(PassManagerBase &) {
return false; return false;
} }
@ -384,7 +372,7 @@ public:
/// addCodeEmitter - This pass should be overridden by the target to add a /// addCodeEmitter - This pass should be overridden by the target to add a
/// code emitter, if supported. If this is not supported, 'true' should be /// code emitter, if supported. If this is not supported, 'true' should be
/// returned. /// returned.
virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level, virtual bool addCodeEmitter(PassManagerBase &,
JITCodeEmitter &) { JITCodeEmitter &) {
return true; return true;
} }

58
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -114,9 +114,10 @@ EnableFastISelOption("fast-isel", cl::Hidden,
LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple, LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: TargetMachine(T, Triple, CPU, FS) { : TargetMachine(T, Triple, CPU, FS) {
CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM); CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
AsmInfo = T.createMCAsmInfo(Triple); AsmInfo = T.createMCAsmInfo(Triple);
// TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0, // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
// and if the old one gets included then MCAsmInfo will be NULL and // and if the old one gets included then MCAsmInfo will be NULL and
@ -130,11 +131,10 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out, formatted_raw_ostream &Out,
CodeGenFileType FileType, CodeGenFileType FileType,
CodeGenOpt::Level OptLevel,
bool DisableVerify) { bool DisableVerify) {
// Add common CodeGen passes. // Add common CodeGen passes.
MCContext *Context = 0; MCContext *Context = 0;
if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context)) if (addCommonCodeGenPasses(PM, DisableVerify, Context))
return true; return true;
assert(Context != 0 && "Failed to get MCContext"); assert(Context != 0 && "Failed to get MCContext");
@ -219,14 +219,13 @@ bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
/// ///
bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
JITCodeEmitter &JCE, JITCodeEmitter &JCE,
CodeGenOpt::Level OptLevel,
bool DisableVerify) { bool DisableVerify) {
// Add common CodeGen passes. // Add common CodeGen passes.
MCContext *Ctx = 0; MCContext *Ctx = 0;
if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx)) if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
return true; return true;
addCodeEmitter(PM, OptLevel, JCE); addCodeEmitter(PM, JCE);
PM.add(createGCInfoDeleter()); PM.add(createGCInfoDeleter());
return false; // success! return false; // success!
@ -240,10 +239,9 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
MCContext *&Ctx, MCContext *&Ctx,
raw_ostream &Out, raw_ostream &Out,
CodeGenOpt::Level OptLevel,
bool DisableVerify) { bool DisableVerify) {
// Add common CodeGen passes. // Add common CodeGen passes.
if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx)) if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
return true; return true;
if (hasMCSaveTempLabels()) if (hasMCSaveTempLabels())
@ -295,7 +293,6 @@ static void printAndVerify(PassManagerBase &PM,
/// emitting to assembly files or machine code output. /// emitting to assembly files or machine code output.
/// ///
bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool DisableVerify, bool DisableVerify,
MCContext *&OutContext) { MCContext *&OutContext) {
// Standard LLVM-Level Passes. // Standard LLVM-Level Passes.
@ -313,7 +310,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
PM.add(createVerifierPass()); PM.add(createVerifierPass());
// Run loop strength reduction before anything else. // Run loop strength reduction before anything else.
if (OptLevel != CodeGenOpt::None && !DisableLSR) { if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
PM.add(createLoopStrengthReducePass(getTargetLowering())); PM.add(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR) if (PrintLSR)
PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs())); PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
@ -349,12 +346,12 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
break; break;
} }
if (OptLevel != CodeGenOpt::None && !DisableCGP) if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
PM.add(createCodeGenPreparePass(getTargetLowering())); PM.add(createCodeGenPreparePass(getTargetLowering()));
PM.add(createStackProtectorPass(getTargetLowering())); PM.add(createStackProtectorPass(getTargetLowering()));
addPreISel(PM, OptLevel); addPreISel(PM);
if (PrintISelInput) if (PrintISelInput)
PM.add(createPrintFunctionPass("\n\n" PM.add(createPrintFunctionPass("\n\n"
@ -377,15 +374,16 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref. OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
// Set up a MachineFunction for the rest of CodeGen to work on. // Set up a MachineFunction for the rest of CodeGen to work on.
PM.add(new MachineFunctionAnalysis(*this, OptLevel)); PM.add(new MachineFunctionAnalysis(*this));
// Enable FastISel with -fast, but allow that to be overridden. // Enable FastISel with -fast, but allow that to be overridden.
if (EnableFastISelOption == cl::BOU_TRUE || if (EnableFastISelOption == cl::BOU_TRUE ||
(OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE)) (getOptLevel() == CodeGenOpt::None &&
EnableFastISelOption != cl::BOU_FALSE))
EnableFastISel = true; EnableFastISel = true;
// Ask the target for an isel. // Ask the target for an isel.
if (addInstSelector(PM, OptLevel)) if (addInstSelector(PM))
return true; return true;
// Print the instruction selected machine code... // Print the instruction selected machine code...
@ -395,21 +393,21 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
PM.add(createExpandISelPseudosPass()); PM.add(createExpandISelPseudosPass());
// Pre-ra tail duplication. // Pre-ra tail duplication.
if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) { if (getOptLevel() != CodeGenOpt::None && !DisableEarlyTailDup) {
PM.add(createTailDuplicatePass(true)); PM.add(createTailDuplicatePass(true));
printAndVerify(PM, "After Pre-RegAlloc TailDuplicate"); printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
} }
// Optimize PHIs before DCE: removing dead PHI cycles may make more // Optimize PHIs before DCE: removing dead PHI cycles may make more
// instructions dead. // instructions dead.
if (OptLevel != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
PM.add(createOptimizePHIsPass()); PM.add(createOptimizePHIsPass());
// If the target requests it, assign local variables to stack slots relative // If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible. // to one another and simplify frame index references where possible.
PM.add(createLocalStackSlotAllocationPass()); PM.add(createLocalStackSlotAllocationPass());
if (OptLevel != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
// With optimization, dead code should already be eliminated. However // With optimization, dead code should already be eliminated. However
// there is one known exception: lowered code for arguments that are only // there is one known exception: lowered code for arguments that are only
// used by tail calls, where the tail calls reuse the incoming stack // used by tail calls, where the tail calls reuse the incoming stack
@ -431,15 +429,15 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
} }
// Run pre-ra passes. // Run pre-ra passes.
if (addPreRegAlloc(PM, OptLevel)) if (addPreRegAlloc(PM))
printAndVerify(PM, "After PreRegAlloc passes"); printAndVerify(PM, "After PreRegAlloc passes");
// Perform register allocation. // Perform register allocation.
PM.add(createRegisterAllocator(OptLevel)); PM.add(createRegisterAllocator(getOptLevel()));
printAndVerify(PM, "After Register Allocation"); printAndVerify(PM, "After Register Allocation");
// Perform stack slot coloring and post-ra machine LICM. // Perform stack slot coloring and post-ra machine LICM.
if (OptLevel != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
// FIXME: Re-enable coloring with register when it's capable of adding // FIXME: Re-enable coloring with register when it's capable of adding
// kill markers. // kill markers.
if (!DisableSSC) if (!DisableSSC)
@ -453,7 +451,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
} }
// Run post-ra passes. // Run post-ra passes.
if (addPostRegAlloc(PM, OptLevel)) if (addPostRegAlloc(PM))
printAndVerify(PM, "After PostRegAlloc passes"); printAndVerify(PM, "After PostRegAlloc passes");
PM.add(createExpandPostRAPseudosPass()); PM.add(createExpandPostRAPseudosPass());
@ -464,23 +462,23 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
printAndVerify(PM, "After PrologEpilogCodeInserter"); printAndVerify(PM, "After PrologEpilogCodeInserter");
// Run pre-sched2 passes. // Run pre-sched2 passes.
if (addPreSched2(PM, OptLevel)) if (addPreSched2(PM))
printAndVerify(PM, "After PreSched2 passes"); printAndVerify(PM, "After PreSched2 passes");
// Second pass scheduler. // Second pass scheduler.
if (OptLevel != CodeGenOpt::None && !DisablePostRA) { if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) {
PM.add(createPostRAScheduler(OptLevel)); PM.add(createPostRAScheduler(getOptLevel()));
printAndVerify(PM, "After PostRAScheduler"); printAndVerify(PM, "After PostRAScheduler");
} }
// Branch folding must be run after regalloc and prolog/epilog insertion. // Branch folding must be run after regalloc and prolog/epilog insertion.
if (OptLevel != CodeGenOpt::None && !DisableBranchFold) { if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
printNoVerify(PM, "After BranchFolding"); printNoVerify(PM, "After BranchFolding");
} }
// Tail duplication. // Tail duplication.
if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) { if (getOptLevel() != CodeGenOpt::None && !DisableTailDuplicate) {
PM.add(createTailDuplicatePass(false)); PM.add(createTailDuplicatePass(false));
printNoVerify(PM, "After TailDuplicate"); printNoVerify(PM, "After TailDuplicate");
} }
@ -490,7 +488,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
if (PrintGCInfo) if (PrintGCInfo)
PM.add(createGCInfoPrinter(dbgs())); PM.add(createGCInfoPrinter(dbgs()));
if (OptLevel != CodeGenOpt::None && !DisableCodePlace) { if (getOptLevel() != CodeGenOpt::None && !DisableCodePlace) {
if (EnableBlockPlacement) { if (EnableBlockPlacement) {
// MachineBlockPlacement is an experimental pass which is disabled by // MachineBlockPlacement is an experimental pass which is disabled by
// default currently. Eventually it should subsume CodePlacementOpt, so // default currently. Eventually it should subsume CodePlacementOpt, so
@ -509,7 +507,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
} }
} }
if (addPreEmitPass(PM, OptLevel)) if (addPreEmitPass(PM))
printNoVerify(PM, "After PreEmit passes"); printNoVerify(PM, "After PreEmit passes");
return false; return false;

5
lib/CodeGen/MachineFunctionAnalysis.cpp
View File

@ -19,9 +19,8 @@ using namespace llvm;
char MachineFunctionAnalysis::ID = 0; char MachineFunctionAnalysis::ID = 0;
MachineFunctionAnalysis::MachineFunctionAnalysis(const TargetMachine &tm, MachineFunctionAnalysis::MachineFunctionAnalysis(const TargetMachine &tm) :
CodeGenOpt::Level OL) : FunctionPass(ID), TM(tm), MF(0) {
FunctionPass(ID), TM(tm), OptLevel(OL), MF(0) {
initializeMachineModuleInfoPass(*PassRegistry::getPassRegistry()); initializeMachineModuleInfoPass(*PassRegistry::getPassRegistry());
} }

2
lib/ExecutionEngine/MCJIT/MCJIT.cpp
View File

@ -64,7 +64,7 @@ MCJIT::MCJIT(Module *m, TargetMachine *tm, TargetJITInfo &tji,
// Turn the machine code intermediate representation into bytes in memory // Turn the machine code intermediate representation into bytes in memory
// that may be executed. // that may be executed.
if (TM->addPassesToEmitMC(PM, Ctx, OS, CodeGenOpt::Default, false)) { if (TM->addPassesToEmitMC(PM, Ctx, OS, false)) {
report_fatal_error("Target does not support MC emission!"); report_fatal_error("Target does not support MC emission!");
} }

4
lib/MC/MCCodeGenInfo.cpp
View File

@ -15,7 +15,9 @@
#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCCodeGenInfo.h"
using namespace llvm; using namespace llvm;
void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM) { void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) {
RelocationModel = RM; RelocationModel = RM;
CMModel = CM; CMModel = CM;
OptLevel = OL;
} }

43
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -38,8 +38,9 @@ extern "C" void LLVMInitializeARMTarget() {
/// ///
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM), CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS), Subtarget(TT, CPU, FS),
JITInfo(), JITInfo(),
InstrItins(Subtarget.getInstrItineraryData()) { InstrItins(Subtarget.getInstrItineraryData()) {
@ -50,8 +51,9 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
: ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget), CodeGenOpt::Level OL)
: ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM, OL), InstrInfo(Subtarget),
DataLayout(Subtarget.isAPCS_ABI() ? DataLayout(Subtarget.isAPCS_ABI() ?
std::string("e-p:32:32-f64:32:64-i64:32:64-" std::string("e-p:32:32-f64:32:64-i64:32:64-"
"v128:32:128-v64:32:64-n32-S32") : "v128:32:128-v64:32:64-n32-S32") :
@ -71,8 +73,9 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
: ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), CodeGenOpt::Level OL)
: ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM, OL),
InstrInfo(Subtarget.hasThumb2() InstrInfo(Subtarget.hasThumb2()
? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
: ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
@ -95,34 +98,30 @@ ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
: (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) { : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
} }
bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM, bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) { if (getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
if (OptLevel != CodeGenOpt::None && EnableGlobalMerge)
PM.add(createGlobalMergePass(getTargetLowering())); PM.add(createGlobalMergePass(getTargetLowering()));
return false; return false;
} }
bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM, bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) { PM.add(createARMISelDag(*this, getOptLevel()));
PM.add(createARMISelDag(*this, OptLevel));
return false; return false;
} }
bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM, bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1. // FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) if (getOptLevel() != CodeGenOpt::None && !Subtarget.isThumb1Only())
PM.add(createARMLoadStoreOptimizationPass(true)); PM.add(createARMLoadStoreOptimizationPass(true));
if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9()) if (getOptLevel() != CodeGenOpt::None && Subtarget.isCortexA9())
PM.add(createMLxExpansionPass()); PM.add(createMLxExpansionPass());
return true; return true;
} }
bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM, bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1. // FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
if (!Subtarget.isThumb1Only()) if (!Subtarget.isThumb1Only())
PM.add(createARMLoadStoreOptimizationPass()); PM.add(createARMLoadStoreOptimizationPass());
if (Subtarget.hasNEON()) if (Subtarget.hasNEON())
@ -133,7 +132,7 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
// proper scheduling. // proper scheduling.
PM.add(createARMExpandPseudoPass()); PM.add(createARMExpandPseudoPass());
if (OptLevel != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
if (!Subtarget.isThumb1Only()) if (!Subtarget.isThumb1Only())
PM.add(createIfConverterPass()); PM.add(createIfConverterPass());
} }
@ -143,8 +142,7 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
return true; return true;
} }
bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb()) if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
PM.add(createThumb2SizeReductionPass()); PM.add(createThumb2SizeReductionPass());
@ -153,7 +151,6 @@ bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
} }
bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
JITCodeEmitter &JCE) { JITCodeEmitter &JCE) {
// Machine code emitter pass for ARM. // Machine code emitter pass for ARM.
PM.add(createARMJITCodeEmitterPass(*this, JCE)); PM.add(createARMJITCodeEmitterPass(*this, JCE));

22
lib/Target/ARM/ARMTargetMachine.h
View File

@ -41,7 +41,8 @@ private:
public: public:
ARMBaseTargetMachine(const Target &T, StringRef TT, ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
virtual ARMJITInfo *getJITInfo() { return &JITInfo; } virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; } virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
@ -50,13 +51,12 @@ public:
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addPreISel(PassManagerBase &PM);
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addInstSelector(PassManagerBase &PM);
virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addPreRegAlloc(PassManagerBase &PM);
virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addPreSched2(PassManagerBase &PM);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addPreEmitPass(PassManagerBase &PM);
virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE);
JITCodeEmitter &MCE);
}; };
/// ARMTargetMachine - ARM target machine. /// ARMTargetMachine - ARM target machine.
@ -71,7 +71,8 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
public: public:
ARMTargetMachine(const Target &T, StringRef TT, ARMTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
virtual const ARMRegisterInfo *getRegisterInfo() const { virtual const ARMRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
@ -111,7 +112,8 @@ class ThumbTargetMachine : public ARMBaseTargetMachine {
public: public:
ThumbTargetMachine(const Target &T, StringRef TT, ThumbTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
/// returns either Thumb1RegisterInfo or Thumb2RegisterInfo /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
virtual const ARMBaseRegisterInfo *getRegisterInfo() const { virtual const ARMBaseRegisterInfo *getRegisterInfo() const {

5
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@ -129,14 +129,15 @@ static MCAsmInfo *createARMMCAsmInfo(const Target &T, StringRef TT) {
} }
static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) { CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo(); MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default) { if (RM == Reloc::Default) {
Triple TheTriple(TT); Triple TheTriple(TT);
// Default relocation model on Darwin is PIC, not DynamicNoPIC. // Default relocation model on Darwin is PIC, not DynamicNoPIC.
RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC; RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
} }
X->InitMCCodeGenInfo(RM, CM); X->InitMCCodeGenInfo(RM, CM, OL);
return X; return X;
} }

1
lib/Target/CBackend/CBackend.cpp
View File

@ -3604,7 +3604,6 @@ void CWriter::visitExtractValueInst(ExtractValueInst &EVI) {
bool CTargetMachine::addPassesToEmitFile(PassManagerBase &PM, bool CTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &o, formatted_raw_ostream &o,
CodeGenFileType FileType, CodeGenFileType FileType,
CodeGenOpt::Level OptLevel,
bool DisableVerify) { bool DisableVerify) {
if (FileType != TargetMachine::CGFT_AssemblyFile) return true; if (FileType != TargetMachine::CGFT_AssemblyFile) return true;

4
lib/Target/CBackend/CTargetMachine.h
View File

@ -22,13 +22,13 @@ namespace llvm {
struct CTargetMachine : public TargetMachine { struct CTargetMachine : public TargetMachine {
CTargetMachine(const Target &T, StringRef TT, CTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: TargetMachine(T, TT, CPU, FS) {} : TargetMachine(T, TT, CPU, FS) {}
virtual bool addPassesToEmitFile(PassManagerBase &PM, virtual bool addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out, formatted_raw_ostream &Out,
CodeGenFileType FileType, CodeGenFileType FileType,
CodeGenOpt::Level OptLevel,
bool DisableVerify); bool DisableVerify);
virtual const TargetData *getTargetData() const { return 0; } virtual const TargetData *getTargetData() const { return 0; }

5
lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp
View File

@ -62,11 +62,12 @@ static MCAsmInfo *createSPUMCAsmInfo(const Target &T, StringRef TT) {
} }
static MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) { CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo(); MCCodeGenInfo *X = new MCCodeGenInfo();
// For the time being, use static relocations, since there's really no // For the time being, use static relocations, since there's really no
// support for PIC yet. // support for PIC yet.
X->InitMCCodeGenInfo(Reloc::Static, CM); X->InitMCCodeGenInfo(Reloc::Static, CM, OL);
return X; return X;
} }

10
lib/Target/CellSPU/SPUTargetMachine.cpp
View File

@ -34,8 +34,9 @@ SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const {
SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT, SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM), CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS), Subtarget(TT, CPU, FS),
DataLayout(Subtarget.getTargetDataString()), DataLayout(Subtarget.getTargetDataString()),
InstrInfo(*this), InstrInfo(*this),
@ -49,8 +50,7 @@ SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT,
// Pass Pipeline Configuration // Pass Pipeline Configuration
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
bool SPUTargetMachine::addInstSelector(PassManagerBase &PM, bool SPUTargetMachine::addInstSelector(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
// Install an instruction selector. // Install an instruction selector.
PM.add(createSPUISelDag(*this)); PM.add(createSPUISelDag(*this));
return false; return false;
@ -58,7 +58,7 @@ bool SPUTargetMachine::addInstSelector(PassManagerBase &PM,
// passes to run just before printing the assembly // passes to run just before printing the assembly
bool SPUTargetMachine:: bool SPUTargetMachine::
addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { addPreEmitPass(PassManagerBase &PM) {
// load the TCE instruction scheduler, if available via // load the TCE instruction scheduler, if available via
// loaded plugins // loaded plugins
typedef llvm::FunctionPass* (*BuilderFunc)(const char*); typedef llvm::FunctionPass* (*BuilderFunc)(const char*);

8
lib/Target/CellSPU/SPUTargetMachine.h
View File

@ -40,7 +40,8 @@ class SPUTargetMachine : public LLVMTargetMachine {
public: public:
SPUTargetMachine(const Target &T, StringRef TT, SPUTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
/// Return the subtarget implementation object /// Return the subtarget implementation object
virtual const SPUSubtarget *getSubtargetImpl() const { virtual const SPUSubtarget *getSubtargetImpl() const {
@ -81,9 +82,8 @@ public:
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, virtual bool addInstSelector(PassManagerBase &PM);
CodeGenOpt::Level OptLevel); virtual bool addPreEmitPass(PassManagerBase &);
virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level);
}; };
} // end namespace llvm } // end namespace llvm

1
lib/Target/CppBackend/CPPBackend.cpp
View File

@ -2065,7 +2065,6 @@ char CppWriter::ID = 0;
bool CPPTargetMachine::addPassesToEmitFile(PassManagerBase &PM, bool CPPTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &o, formatted_raw_ostream &o,
CodeGenFileType FileType, CodeGenFileType FileType,
CodeGenOpt::Level OptLevel,
bool DisableVerify) { bool DisableVerify) {
if (FileType != TargetMachine::CGFT_AssemblyFile) return true; if (FileType != TargetMachine::CGFT_AssemblyFile) return true;
PM.add(new CppWriter(o)); PM.add(new CppWriter(o));

4
lib/Target/CppBackend/CPPTargetMachine.h
View File

@ -24,13 +24,13 @@ class formatted_raw_ostream;
struct CPPTargetMachine : public TargetMachine { struct CPPTargetMachine : public TargetMachine {
CPPTargetMachine(const Target &T, StringRef TT, CPPTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: TargetMachine(T, TT, CPU, FS) {} : TargetMachine(T, TT, CPU, FS) {}
virtual bool addPassesToEmitFile(PassManagerBase &PM, virtual bool addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out, formatted_raw_ostream &Out,
CodeGenFileType FileType, CodeGenFileType FileType,
CodeGenOpt::Level OptLevel,
bool DisableVerify); bool DisableVerify);
virtual const TargetData *getTargetData() const { return 0; } virtual const TargetData *getTargetData() const { return 0; }

11
lib/Target/MBlaze/MBlazeTargetMachine.cpp
View File

@ -34,8 +34,9 @@ extern "C" void LLVMInitializeMBlazeTarget() {
MBlazeTargetMachine:: MBlazeTargetMachine::
MBlazeTargetMachine(const Target &T, StringRef TT, MBlazeTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM): Reloc::Model RM, CodeModel::Model CM,
LLVMTargetMachine(T, TT, CPU, FS, RM, CM), CodeGenOpt::Level OL):
LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS), Subtarget(TT, CPU, FS),
DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"), DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
InstrInfo(*this), InstrInfo(*this),
@ -46,8 +47,7 @@ MBlazeTargetMachine(const Target &T, StringRef TT,
// Install an instruction selector pass using // Install an instruction selector pass using
// the ISelDag to gen MBlaze code. // the ISelDag to gen MBlaze code.
bool MBlazeTargetMachine::addInstSelector(PassManagerBase &PM, bool MBlazeTargetMachine::addInstSelector(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
PM.add(createMBlazeISelDag(*this)); PM.add(createMBlazeISelDag(*this));
return false; return false;
} }
@ -55,8 +55,7 @@ bool MBlazeTargetMachine::addInstSelector(PassManagerBase &PM,
// Implemented by targets that want to run passes immediately before // Implemented by targets that want to run passes immediately before
// machine code is emitted. return true if -print-machineinstrs should // machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes. // print out the code after the passes.
bool MBlazeTargetMachine::addPreEmitPass(PassManagerBase &PM, bool MBlazeTargetMachine::addPreEmitPass(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
PM.add(createMBlazeDelaySlotFillerPass(*this)); PM.add(createMBlazeDelaySlotFillerPass(*this));
return true; return true;
} }

7
lib/Target/MBlaze/MBlazeTargetMachine.h
View File

@ -43,7 +43,8 @@ namespace llvm {
public: public:
MBlazeTargetMachine(const Target &T, StringRef TT, MBlazeTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
virtual const MBlazeInstrInfo *getInstrInfo() const virtual const MBlazeInstrInfo *getInstrInfo() const
{ return &InstrInfo; } { return &InstrInfo; }
@ -77,8 +78,8 @@ namespace llvm {
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level Opt); virtual bool addInstSelector(PassManagerBase &PM);
virtual bool addPreEmitPass(PassManagerBase &PM,CodeGenOpt::Level Opt); virtual bool addPreEmitPass(PassManagerBase &PM);
}; };
} // End llvm namespace } // End llvm namespace

5
lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp
View File

@ -62,13 +62,14 @@ static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
} }
static MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) { CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo(); MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default) if (RM == Reloc::Default)
RM = Reloc::Static; RM = Reloc::Static;
if (CM == CodeModel::Default) if (CM == CodeModel::Default)
CM = CodeModel::Small; CM = CodeModel::Small;
X->InitMCCodeGenInfo(RM, CM); X->InitMCCodeGenInfo(RM, CM, OL);
return X; return X;
} }

5
lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
View File

@ -51,9 +51,10 @@ static MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU,
} }
static MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) { CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo(); MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM, CM); X->InitMCCodeGenInfo(RM, CM, OL);
return X; return X;
} }

13
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -28,8 +28,9 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T,
StringRef TT, StringRef TT,
StringRef CPU, StringRef CPU,
StringRef FS, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM), CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS), Subtarget(TT, CPU, FS),
// FIXME: Check TargetData string. // FIXME: Check TargetData string.
DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"), DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),
@ -37,15 +38,13 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T,
FrameLowering(Subtarget) { } FrameLowering(Subtarget) { }
bool MSP430TargetMachine::addInstSelector(PassManagerBase &PM, bool MSP430TargetMachine::addInstSelector(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
// Install an instruction selector. // Install an instruction selector.
PM.add(createMSP430ISelDag(*this, OptLevel)); PM.add(createMSP430ISelDag(*this, getOptLevel()));
return false; return false;
} }
bool MSP430TargetMachine::addPreEmitPass(PassManagerBase &PM, bool MSP430TargetMachine::addPreEmitPass(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
// Must run branch selection immediately preceding the asm printer. // Must run branch selection immediately preceding the asm printer.
PM.add(createMSP430BranchSelectionPass()); PM.add(createMSP430BranchSelectionPass());
return false; return false;

7
lib/Target/MSP430/MSP430TargetMachine.h
View File

@ -40,7 +40,8 @@ class MSP430TargetMachine : public LLVMTargetMachine {
public: public:
MSP430TargetMachine(const Target &T, StringRef TT, MSP430TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
virtual const TargetFrameLowering *getFrameLowering() const { virtual const TargetFrameLowering *getFrameLowering() const {
return &FrameLowering; return &FrameLowering;
@ -61,8 +62,8 @@ public:
return &TSInfo; return &TSInfo;
} }
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addInstSelector(PassManagerBase &PM);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addPreEmitPass(PassManagerBase &PM);
}; // MSP430TargetMachine. }; // MSP430TargetMachine.
} // end namespace llvm } // end namespace llvm

5
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
View File

@ -63,11 +63,12 @@ static MCAsmInfo *createMipsMCAsmInfo(const Target &T, StringRef TT) {
} }
static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) { CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo(); MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default) if (RM == Reloc::Default)
RM = Reloc::PIC_; RM = Reloc::PIC_;
X->InitMCCodeGenInfo(RM, CM); X->InitMCCodeGenInfo(RM, CM, OL);
return X; return X;
} }

34
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -36,8 +36,9 @@ MipsTargetMachine::
MipsTargetMachine(const Target &T, StringRef TT, MipsTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool isLittle): bool isLittle):
LLVMTargetMachine(T, TT, CPU, FS, RM, CM), LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS, isLittle), Subtarget(TT, CPU, FS, isLittle),
DataLayout(isLittle ? DataLayout(isLittle ?
(Subtarget.isABI_N64() ? (Subtarget.isABI_N64() ?
@ -54,31 +55,35 @@ MipsTargetMachine(const Target &T, StringRef TT,
MipsebTargetMachine:: MipsebTargetMachine::
MipsebTargetMachine(const Target &T, StringRef TT, MipsebTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) : Reloc::Model RM, CodeModel::Model CM,
MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {} CodeGenOpt::Level OL) :
MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {}
MipselTargetMachine:: MipselTargetMachine::
MipselTargetMachine(const Target &T, StringRef TT, MipselTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) : Reloc::Model RM, CodeModel::Model CM,
MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {} CodeGenOpt::Level OL) :
MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {}
Mips64ebTargetMachine:: Mips64ebTargetMachine::
Mips64ebTargetMachine(const Target &T, StringRef TT, Mips64ebTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) : Reloc::Model RM, CodeModel::Model CM,
MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {} CodeGenOpt::Level OL) :
MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {}
Mips64elTargetMachine:: Mips64elTargetMachine::
Mips64elTargetMachine(const Target &T, StringRef TT, Mips64elTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) : Reloc::Model RM, CodeModel::Model CM,
MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {} CodeGenOpt::Level OL) :
MipsTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {}
// Install an instruction selector pass using // Install an instruction selector pass using
// the ISelDag to gen Mips code. // the ISelDag to gen Mips code.
bool MipsTargetMachine:: bool MipsTargetMachine::
addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel) addInstSelector(PassManagerBase &PM)
{ {
PM.add(createMipsISelDag(*this)); PM.add(createMipsISelDag(*this));
return false; return false;
@ -88,14 +93,14 @@ addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
// machine code is emitted. return true if -print-machineinstrs should // machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes. // print out the code after the passes.
bool MipsTargetMachine:: bool MipsTargetMachine::
addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) addPreEmitPass(PassManagerBase &PM)
{ {
PM.add(createMipsDelaySlotFillerPass(*this)); PM.add(createMipsDelaySlotFillerPass(*this));
return true; return true;
} }
bool MipsTargetMachine:: bool MipsTargetMachine::
addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { addPreRegAlloc(PassManagerBase &PM) {
// Do not restore $gp if target is Mips64. // Do not restore $gp if target is Mips64.
// In N32/64, $gp is a callee-saved register. // In N32/64, $gp is a callee-saved register.
if (!Subtarget.hasMips64()) if (!Subtarget.hasMips64())
@ -104,14 +109,13 @@ addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
} }
bool MipsTargetMachine:: bool MipsTargetMachine::
addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { addPostRegAlloc(PassManagerBase &PM) {
PM.add(createMipsExpandPseudoPass(*this)); PM.add(createMipsExpandPseudoPass(*this));
return true; return true;
} }
bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM, bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel, JITCodeEmitter &JCE) {
JITCodeEmitter &JCE) {
// Machine code emitter pass for Mips. // Machine code emitter pass for Mips.
PM.add(createMipsJITCodeEmitterPass(*this, JCE)); PM.add(createMipsJITCodeEmitterPass(*this, JCE));
return false; return false;

25
lib/Target/Mips/MipsTargetMachine.h
View File

@ -40,6 +40,7 @@ namespace llvm {
MipsTargetMachine(const Target &T, StringRef TT, MipsTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool isLittle); bool isLittle);
virtual const MipsInstrInfo *getInstrInfo() const virtual const MipsInstrInfo *getInstrInfo() const
@ -67,15 +68,11 @@ namespace llvm {
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, virtual bool addInstSelector(PassManagerBase &PM);
CodeGenOpt::Level OptLevel); virtual bool addPreEmitPass(PassManagerBase &PM);
virtual bool addPreEmitPass(PassManagerBase &PM, virtual bool addPreRegAlloc(PassManagerBase &PM);
CodeGenOpt::Level OptLevel); virtual bool addPostRegAlloc(PassManagerBase &);
virtual bool addPreRegAlloc(PassManagerBase &PM,
CodeGenOpt::Level OptLevel);
virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level);
virtual bool addCodeEmitter(PassManagerBase &PM, virtual bool addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
JITCodeEmitter &JCE); JITCodeEmitter &JCE);
}; };
@ -86,7 +83,8 @@ class MipsebTargetMachine : public MipsTargetMachine {
public: public:
MipsebTargetMachine(const Target &T, StringRef TT, MipsebTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
}; };
/// MipselTargetMachine - Mips32 little endian target machine. /// MipselTargetMachine - Mips32 little endian target machine.
@ -95,7 +93,8 @@ class MipselTargetMachine : public MipsTargetMachine {
public: public:
MipselTargetMachine(const Target &T, StringRef TT, MipselTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
}; };
/// Mips64ebTargetMachine - Mips64 big endian target machine. /// Mips64ebTargetMachine - Mips64 big endian target machine.
@ -104,7 +103,8 @@ class Mips64ebTargetMachine : public MipsTargetMachine {
public: public:
Mips64ebTargetMachine(const Target &T, StringRef TT, Mips64ebTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
}; };
/// Mips64elTargetMachine - Mips64 little endian target machine. /// Mips64elTargetMachine - Mips64 little endian target machine.
@ -113,7 +113,8 @@ class Mips64elTargetMachine : public MipsTargetMachine {
public: public:
Mips64elTargetMachine(const Target &T, StringRef TT, Mips64elTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
}; };
} // End llvm namespace } // End llvm namespace

5
lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp
View File

@ -52,9 +52,10 @@ static MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU,
} }
static MCCodeGenInfo *createPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) { CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo(); MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM, CM); X->InitMCCodeGenInfo(RM, CM, OL);
return X; return X;
} }

67
lib/Target/PTX/PTXTargetMachine.cpp
View File

@ -88,8 +88,9 @@ namespace {
PTXTargetMachine::PTXTargetMachine(const Target &T, PTXTargetMachine::PTXTargetMachine(const Target &T,
StringRef TT, StringRef CPU, StringRef FS, StringRef TT, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool is64Bit) bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM), : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
DataLayout(is64Bit ? DataLayout64 : DataLayout32), DataLayout(is64Bit ? DataLayout64 : DataLayout32),
Subtarget(TT, CPU, FS, is64Bit), Subtarget(TT, CPU, FS, is64Bit),
FrameLowering(Subtarget), FrameLowering(Subtarget),
@ -100,39 +101,38 @@ PTXTargetMachine::PTXTargetMachine(const Target &T,
PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT, PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
: PTXTargetMachine(T, TT, CPU, FS, RM, CM, false) { CodeGenOpt::Level OL)
: PTXTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
} }
PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT, PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
: PTXTargetMachine(T, TT, CPU, FS, RM, CM, true) { CodeGenOpt::Level OL)
: PTXTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
} }
bool PTXTargetMachine::addInstSelector(PassManagerBase &PM, bool PTXTargetMachine::addInstSelector(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) { PM.add(createPTXISelDag(*this, getOptLevel()));
PM.add(createPTXISelDag(*this, OptLevel));
return false; return false;
} }
bool PTXTargetMachine::addPostRegAlloc(PassManagerBase &PM, bool PTXTargetMachine::addPostRegAlloc(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
// PTXMFInfoExtract must after register allocation! // PTXMFInfoExtract must after register allocation!
//PM.add(createPTXMFInfoExtract(*this, OptLevel)); //PM.add(createPTXMFInfoExtract(*this));
return false; return false;
} }
bool PTXTargetMachine::addPassesToEmitFile(PassManagerBase &PM, bool PTXTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out, formatted_raw_ostream &Out,
CodeGenFileType FileType, CodeGenFileType FileType,
CodeGenOpt::Level OptLevel,
bool DisableVerify) { bool DisableVerify) {
// This is mostly based on LLVMTargetMachine::addPassesToEmitFile // This is mostly based on LLVMTargetMachine::addPassesToEmitFile
// Add common CodeGen passes. // Add common CodeGen passes.
MCContext *Context = 0; MCContext *Context = 0;
if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context)) if (addCommonCodeGenPasses(PM, DisableVerify, Context))
return true; return true;
assert(Context != 0 && "Failed to get MCContext"); assert(Context != 0 && "Failed to get MCContext");
@ -192,7 +192,6 @@ bool PTXTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
} }
bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool DisableVerify, bool DisableVerify,
MCContext *&OutContext) { MCContext *&OutContext) {
// Add standard LLVM codegen passes. // Add standard LLVM codegen passes.
@ -214,7 +213,7 @@ bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
PM.add(createVerifierPass()); PM.add(createVerifierPass());
// Run loop strength reduction before anything else. // Run loop strength reduction before anything else.
if (OptLevel != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
PM.add(createLoopStrengthReducePass(getTargetLowering())); PM.add(createLoopStrengthReducePass(getTargetLowering()));
//PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs())); //PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
} }
@ -228,12 +227,12 @@ bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
// The lower invoke pass may create unreachable code. Remove it. // The lower invoke pass may create unreachable code. Remove it.
PM.add(createUnreachableBlockEliminationPass()); PM.add(createUnreachableBlockEliminationPass());
if (OptLevel != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
PM.add(createCodeGenPreparePass(getTargetLowering())); PM.add(createCodeGenPreparePass(getTargetLowering()));
PM.add(createStackProtectorPass(getTargetLowering())); PM.add(createStackProtectorPass(getTargetLowering()));
addPreISel(PM, OptLevel); addPreISel(PM);
//PM.add(createPrintFunctionPass("\n\n" //PM.add(createPrintFunctionPass("\n\n"
// "*** Final LLVM Code input to ISel ***\n", // "*** Final LLVM Code input to ISel ***\n",
@ -255,10 +254,10 @@ bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref. OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
// Set up a MachineFunction for the rest of CodeGen to work on. // Set up a MachineFunction for the rest of CodeGen to work on.
PM.add(new MachineFunctionAnalysis(*this, OptLevel)); PM.add(new MachineFunctionAnalysis(*this));
// Ask the target for an isel. // Ask the target for an isel.
if (addInstSelector(PM, OptLevel)) if (addInstSelector(PM))
return true; return true;
// Print the instruction selected machine code... // Print the instruction selected machine code...
@ -268,21 +267,21 @@ bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
PM.add(createExpandISelPseudosPass()); PM.add(createExpandISelPseudosPass());
// Pre-ra tail duplication. // Pre-ra tail duplication.
if (OptLevel != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
PM.add(createTailDuplicatePass(true)); PM.add(createTailDuplicatePass(true));
printAndVerify(PM, "After Pre-RegAlloc TailDuplicate"); printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
} }
// Optimize PHIs before DCE: removing dead PHI cycles may make more // Optimize PHIs before DCE: removing dead PHI cycles may make more
// instructions dead. // instructions dead.
if (OptLevel != CodeGenOpt::None) if (getOptLevel() != CodeGenOpt::None)
PM.add(createOptimizePHIsPass()); PM.add(createOptimizePHIsPass());
// If the target requests it, assign local variables to stack slots relative // If the target requests it, assign local variables to stack slots relative
// to one another and simplify frame index references where possible. // to one another and simplify frame index references where possible.
PM.add(createLocalStackSlotAllocationPass()); PM.add(createLocalStackSlotAllocationPass());
if (OptLevel != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
// With optimization, dead code should already be eliminated. However // With optimization, dead code should already be eliminated. However
// there is one known exception: lowered code for arguments that are only // there is one known exception: lowered code for arguments that are only
// used by tail calls, where the tail calls reuse the incoming stack // used by tail calls, where the tail calls reuse the incoming stack
@ -300,7 +299,7 @@ bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
} }
// Run pre-ra passes. // Run pre-ra passes.
if (addPreRegAlloc(PM, OptLevel)) if (addPreRegAlloc(PM))
printAndVerify(PM, "After PreRegAlloc passes"); printAndVerify(PM, "After PreRegAlloc passes");
// Perform register allocation. // Perform register allocation.
@ -308,7 +307,7 @@ bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
printAndVerify(PM, "After Register Allocation"); printAndVerify(PM, "After Register Allocation");
// Perform stack slot coloring and post-ra machine LICM. // Perform stack slot coloring and post-ra machine LICM.
if (OptLevel != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
// FIXME: Re-enable coloring with register when it's capable of adding // FIXME: Re-enable coloring with register when it's capable of adding
// kill markers. // kill markers.
PM.add(createStackSlotColoringPass(false)); PM.add(createStackSlotColoringPass(false));
@ -322,7 +321,7 @@ bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
} }
// Run post-ra passes. // Run post-ra passes.
if (addPostRegAlloc(PM, OptLevel)) if (addPostRegAlloc(PM))
printAndVerify(PM, "After PostRegAlloc passes"); printAndVerify(PM, "After PostRegAlloc passes");
PM.add(createExpandPostRAPseudosPass()); PM.add(createExpandPostRAPseudosPass());
@ -333,23 +332,23 @@ bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
printAndVerify(PM, "After PrologEpilogCodeInserter"); printAndVerify(PM, "After PrologEpilogCodeInserter");
// Run pre-sched2 passes. // Run pre-sched2 passes.
if (addPreSched2(PM, OptLevel)) if (addPreSched2(PM))
printAndVerify(PM, "After PreSched2 passes"); printAndVerify(PM, "After PreSched2 passes");
// Second pass scheduler. // Second pass scheduler.
if (OptLevel != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
PM.add(createPostRAScheduler(OptLevel)); PM.add(createPostRAScheduler(getOptLevel()));
printAndVerify(PM, "After PostRAScheduler"); printAndVerify(PM, "After PostRAScheduler");
} }
// Branch folding must be run after regalloc and prolog/epilog insertion. // Branch folding must be run after regalloc and prolog/epilog insertion.
if (OptLevel != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
printNoVerify(PM, "After BranchFolding"); printNoVerify(PM, "After BranchFolding");
} }
// Tail duplication. // Tail duplication.
if (OptLevel != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
PM.add(createTailDuplicatePass(false)); PM.add(createTailDuplicatePass(false));
printNoVerify(PM, "After TailDuplicate"); printNoVerify(PM, "After TailDuplicate");
} }
@ -359,16 +358,16 @@ bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
//if (PrintGCInfo) //if (PrintGCInfo)
// PM.add(createGCInfoPrinter(dbgs())); // PM.add(createGCInfoPrinter(dbgs()));
if (OptLevel != CodeGenOpt::None) { if (getOptLevel() != CodeGenOpt::None) {
PM.add(createCodePlacementOptPass()); PM.add(createCodePlacementOptPass());
printNoVerify(PM, "After CodePlacementOpt"); printNoVerify(PM, "After CodePlacementOpt");
} }
if (addPreEmitPass(PM, OptLevel)) if (addPreEmitPass(PM))
printNoVerify(PM, "After PreEmit passes"); printNoVerify(PM, "After PreEmit passes");
PM.add(createPTXMFInfoExtract(*this, OptLevel)); PM.add(createPTXMFInfoExtract(*this, getOptLevel()));
PM.add(createPTXFPRoundingModePass(*this, OptLevel)); PM.add(createPTXFPRoundingModePass(*this, getOptLevel()));
return false; return false;
} }

18
lib/Target/PTX/PTXTargetMachine.h
View File

@ -37,6 +37,7 @@ class PTXTargetMachine : public LLVMTargetMachine {
PTXTargetMachine(const Target &T, StringRef TT, PTXTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool is64Bit); bool is64Bit);
virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const TargetData *getTargetData() const { return &DataLayout; }
@ -58,22 +59,18 @@ class PTXTargetMachine : public LLVMTargetMachine {
virtual const PTXSubtarget *getSubtargetImpl() const { return &Subtarget; } virtual const PTXSubtarget *getSubtargetImpl() const { return &Subtarget; }
virtual bool addInstSelector(PassManagerBase &PM, virtual bool addInstSelector(PassManagerBase &PM);
CodeGenOpt::Level OptLevel); virtual bool addPostRegAlloc(PassManagerBase &PM);
virtual bool addPostRegAlloc(PassManagerBase &PM,
CodeGenOpt::Level OptLevel);
// We override this method to supply our own set of codegen passes. // We override this method to supply our own set of codegen passes.
virtual bool addPassesToEmitFile(PassManagerBase &, virtual bool addPassesToEmitFile(PassManagerBase &,
formatted_raw_ostream &, formatted_raw_ostream &,
CodeGenFileType, CodeGenFileType,
CodeGenOpt::Level,
bool = true); bool = true);
// Emission of machine code through JITCodeEmitter is not supported. // Emission of machine code through JITCodeEmitter is not supported.
virtual bool addPassesToEmitMachineCode(PassManagerBase &, virtual bool addPassesToEmitMachineCode(PassManagerBase &,
JITCodeEmitter &, JITCodeEmitter &,
CodeGenOpt::Level,
bool = true) { bool = true) {
return true; return true;
} }
@ -82,14 +79,13 @@ class PTXTargetMachine : public LLVMTargetMachine {
virtual bool addPassesToEmitMC(PassManagerBase &, virtual bool addPassesToEmitMC(PassManagerBase &,
MCContext *&, MCContext *&,
raw_ostream &, raw_ostream &,
CodeGenOpt::Level,
bool = true) { bool = true) {
return true; return true;
} }
private: private:
bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level, bool addCommonCodeGenPasses(PassManagerBase &,
bool DisableVerify, MCContext *&OutCtx); bool DisableVerify, MCContext *&OutCtx);
}; // class PTXTargetMachine }; // class PTXTargetMachine
@ -99,7 +95,8 @@ public:
PTX32TargetMachine(const Target &T, StringRef TT, PTX32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
}; // class PTX32TargetMachine }; // class PTX32TargetMachine
class PTX64TargetMachine : public PTXTargetMachine { class PTX64TargetMachine : public PTXTargetMachine {
@ -107,7 +104,8 @@ public:
PTX64TargetMachine(const Target &T, StringRef TT, PTX64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
}; // class PTX32TargetMachine }; // class PTX32TargetMachine
} // namespace llvm } // namespace llvm

5
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
View File

@ -76,7 +76,8 @@ static MCAsmInfo *createPPCMCAsmInfo(const Target &T, StringRef TT) {
} }
static MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) { CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo(); MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default) { if (RM == Reloc::Default) {
@ -86,7 +87,7 @@ static MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM,
else else
RM = Reloc::Static; RM = Reloc::Static;
} }
X->InitMCCodeGenInfo(RM, CM); X->InitMCCodeGenInfo(RM, CM, OL);
return X; return X;
} }

1
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -18,7 +18,6 @@
#include "MCTargetDesc/PPCPredicates.h" #include "MCTargetDesc/PPCPredicates.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/SelectionDAGISel.h"

20
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -29,8 +29,9 @@ extern "C" void LLVMInitializePowerPCTarget() {
PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool is64Bit) bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM), : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS, is64Bit), Subtarget(TT, CPU, FS, is64Bit),
DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
FrameLowering(Subtarget), JITInfo(*this, is64Bit), FrameLowering(Subtarget), JITInfo(*this, is64Bit),
@ -44,15 +45,17 @@ bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
: PPCTargetMachine(T, TT, CPU, FS, RM, CM, false) { CodeGenOpt::Level OL)
: PPCTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
} }
PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
: PPCTargetMachine(T, TT, CPU, FS, RM, CM, true) { CodeGenOpt::Level OL)
: PPCTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
} }
@ -60,22 +63,19 @@ PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
// Pass Pipeline Configuration // Pass Pipeline Configuration
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool PPCTargetMachine::addInstSelector(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
// Install an instruction selector. // Install an instruction selector.
PM.add(createPPCISelDag(*this)); PM.add(createPPCISelDag(*this));
return false; return false;
} }
bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
// Must run branch selection immediately preceding the asm printer. // Must run branch selection immediately preceding the asm printer.
PM.add(createPPCBranchSelectionPass()); PM.add(createPPCBranchSelectionPass());
return false; return false;
} }
bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
JITCodeEmitter &JCE) { JITCodeEmitter &JCE) {
// FIXME: This should be moved to TargetJITInfo!! // FIXME: This should be moved to TargetJITInfo!!
if (Subtarget.isPPC64()) if (Subtarget.isPPC64())

15
lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -42,7 +42,8 @@ class PPCTargetMachine : public LLVMTargetMachine {
public: public:
PPCTargetMachine(const Target &T, StringRef TT, PPCTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM, bool is64Bit); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64Bit);
virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const PPCFrameLowering *getFrameLowering() const { virtual const PPCFrameLowering *getFrameLowering() const {
@ -66,9 +67,9 @@ public:
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addInstSelector(PassManagerBase &PM);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addPreEmitPass(PassManagerBase &PM);
virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, virtual bool addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE); JITCodeEmitter &JCE);
virtual bool getEnableTailMergeDefault() const; virtual bool getEnableTailMergeDefault() const;
}; };
@ -79,7 +80,8 @@ class PPC32TargetMachine : public PPCTargetMachine {
public: public:
PPC32TargetMachine(const Target &T, StringRef TT, PPC32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
}; };
/// PPC64TargetMachine - PowerPC 64-bit target machine. /// PPC64TargetMachine - PowerPC 64-bit target machine.
@ -88,7 +90,8 @@ class PPC64TargetMachine : public PPCTargetMachine {
public: public:
PPC64TargetMachine(const Target &T, StringRef TT, PPC64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
}; };
} // end namespace llvm } // end namespace llvm

5
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
View File

@ -50,9 +50,10 @@ static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
} }
static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) { CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo(); MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM, CM); X->InitMCCodeGenInfo(RM, CM, OL);
return X; return X;
} }

19
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -27,16 +27,16 @@ extern "C" void LLVMInitializeSparcTarget() {
SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool is64bit) bool is64bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM), : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS, is64bit), Subtarget(TT, CPU, FS, is64bit),
DataLayout(Subtarget.getDataLayout()), DataLayout(Subtarget.getDataLayout()),
TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
FrameLowering(Subtarget) { FrameLowering(Subtarget) {
} }
bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, bool SparcTargetMachine::addInstSelector(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
PM.add(createSparcISelDag(*this)); PM.add(createSparcISelDag(*this));
return false; return false;
} }
@ -44,8 +44,7 @@ bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
/// addPreEmitPass - This pass may be implemented by targets that want to run /// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return /// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes. /// true if -print-machineinstrs should print out the code after the passes.
bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM){
CodeGenOpt::Level OptLevel){
PM.add(createSparcFPMoverPass(*this)); PM.add(createSparcFPMoverPass(*this));
PM.add(createSparcDelaySlotFillerPass(*this)); PM.add(createSparcDelaySlotFillerPass(*this));
return true; return true;
@ -54,13 +53,15 @@ bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
StringRef TT, StringRef CPU, StringRef TT, StringRef CPU,
StringRef FS, Reloc::Model RM, StringRef FS, Reloc::Model RM,
CodeModel::Model CM) CodeModel::Model CM,
: SparcTargetMachine(T, TT, CPU, FS, RM, CM, false) { CodeGenOpt::Level OL)
: SparcTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
} }
SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
StringRef TT, StringRef CPU, StringRef TT, StringRef CPU,
StringRef FS, Reloc::Model RM, StringRef FS, Reloc::Model RM,
CodeModel::Model CM) CodeModel::Model CM,
: SparcTargetMachine(T, TT, CPU, FS, RM, CM, true) { CodeGenOpt::Level OL)
: SparcTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
} }

13
lib/Target/Sparc/SparcTargetMachine.h
View File

@ -35,7 +35,8 @@ class SparcTargetMachine : public LLVMTargetMachine {
public: public:
SparcTargetMachine(const Target &T, StringRef TT, SparcTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM, bool is64bit); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64bit);
virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameLowering *getFrameLowering() const { virtual const TargetFrameLowering *getFrameLowering() const {
@ -54,8 +55,8 @@ public:
virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const TargetData *getTargetData() const { return &DataLayout; }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addInstSelector(PassManagerBase &PM);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addPreEmitPass(PassManagerBase &PM);
}; };
/// SparcV8TargetMachine - Sparc 32-bit target machine /// SparcV8TargetMachine - Sparc 32-bit target machine
@ -64,7 +65,8 @@ class SparcV8TargetMachine : public SparcTargetMachine {
public: public:
SparcV8TargetMachine(const Target &T, StringRef TT, SparcV8TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
}; };
/// SparcV9TargetMachine - Sparc 64-bit target machine /// SparcV9TargetMachine - Sparc 64-bit target machine
@ -73,7 +75,8 @@ class SparcV9TargetMachine : public SparcTargetMachine {
public: public:
SparcV9TargetMachine(const Target &T, StringRef TT, SparcV9TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
}; };
} // end namespace llvm } // end namespace llvm

8
lib/Target/TargetMachine.cpp
View File

@ -226,6 +226,14 @@ CodeModel::Model TargetMachine::getCodeModel() const {
return CodeGenInfo->getCodeModel(); return CodeGenInfo->getCodeModel();
} }
/// getOptLevel - Returns the optimization level: None, Less,
/// Default, or Aggressive.
CodeGenOpt::Level TargetMachine::getOptLevel() const {
if (!CodeGenInfo)
return CodeGenOpt::Default;
return CodeGenInfo->getOptLevel();
}
bool TargetMachine::getAsmVerbosityDefault() { bool TargetMachine::getAsmVerbosityDefault() {
return AsmVerbosityDefault; return AsmVerbosityDefault;
} }

5
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
View File

@ -385,7 +385,8 @@ static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
} }
static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) { CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo(); MCCodeGenInfo *X = new MCCodeGenInfo();
Triple T(TT); Triple T(TT);
@ -429,7 +430,7 @@ static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
// 64-bit JIT places everything in the same buffer except external funcs. // 64-bit JIT places everything in the same buffer except external funcs.
CM = is64Bit ? CodeModel::Large : CodeModel::Small; CM = is64Bit ? CodeModel::Large : CodeModel::Small;
X->InitMCCodeGenInfo(RM, CM); X->InitMCCodeGenInfo(RM, CM, OL);
return X; return X;
} }

30
lib/Target/X86/X86TargetMachine.cpp
View File

@ -31,8 +31,9 @@ extern "C" void LLVMInitializeX86Target() {
X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT, X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
: X86TargetMachine(T, TT, CPU, FS, RM, CM, false), CodeGenOpt::Level OL)
: X86TargetMachine(T, TT, CPU, FS, RM, CM, OL, false),
DataLayout(getSubtargetImpl()->isTargetDarwin() ? DataLayout(getSubtargetImpl()->isTargetDarwin() ?
"e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-" "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
"n8:16:32-S128" : "n8:16:32-S128" :
@ -51,8 +52,9 @@ X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT, X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
: X86TargetMachine(T, TT, CPU, FS, RM, CM, true), CodeGenOpt::Level OL)
: X86TargetMachine(T, TT, CPU, FS, RM, CM, OL, true),
DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-" DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
"n8:16:32:64-S128"), "n8:16:32:64-S128"),
InstrInfo(*this), InstrInfo(*this),
@ -66,8 +68,9 @@ X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool is64Bit) bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM), : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit), Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit),
FrameLowering(*this, Subtarget), FrameLowering(*this, Subtarget),
ELFWriterInfo(is64Bit, true) { ELFWriterInfo(is64Bit, true) {
@ -108,10 +111,9 @@ UseVZeroUpper("x86-use-vzeroupper",
// Pass Pipeline Configuration // Pass Pipeline Configuration
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
bool X86TargetMachine::addInstSelector(PassManagerBase &PM, bool X86TargetMachine::addInstSelector(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
// Install an instruction selector. // Install an instruction selector.
PM.add(createX86ISelDag(*this, OptLevel)); PM.add(createX86ISelDag(*this, getOptLevel()));
// For 32-bit, prepend instructions to set the "global base reg" for PIC. // For 32-bit, prepend instructions to set the "global base reg" for PIC.
if (!Subtarget.is64Bit()) if (!Subtarget.is64Bit())
@ -120,22 +122,19 @@ bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
return false; return false;
} }
bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
PM.add(createX86MaxStackAlignmentHeuristicPass()); PM.add(createX86MaxStackAlignmentHeuristicPass());
return false; // -print-machineinstr shouldn't print after this. return false; // -print-machineinstr shouldn't print after this.
} }
bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
PM.add(createX86FloatingPointStackifierPass()); PM.add(createX86FloatingPointStackifierPass());
return true; // -print-machineinstr should print after this. return true; // -print-machineinstr should print after this.
} }
bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM, bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
bool ShouldPrint = false; bool ShouldPrint = false;
if (OptLevel != CodeGenOpt::None && Subtarget.hasXMMInt()) { if (getOptLevel() != CodeGenOpt::None && Subtarget.hasXMMInt()) {
PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass)); PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
ShouldPrint = true; ShouldPrint = true;
} }
@ -149,7 +148,6 @@ bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM,
} }
bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
JITCodeEmitter &JCE) { JITCodeEmitter &JCE) {
PM.add(createX86JITCodeEmitterPass(*this, JCE)); PM.add(createX86JITCodeEmitterPass(*this, JCE));

17
lib/Target/X86/X86TargetMachine.h
View File

@ -40,6 +40,7 @@ public:
X86TargetMachine(const Target &T, StringRef TT, X86TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool is64Bit); bool is64Bit);
virtual const X86InstrInfo *getInstrInfo() const { virtual const X86InstrInfo *getInstrInfo() const {
@ -66,11 +67,11 @@ public:
} }
// Set up the pass pipeline. // Set up the pass pipeline.
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addInstSelector(PassManagerBase &PM);
virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addPreRegAlloc(PassManagerBase &PM);
virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addPostRegAlloc(PassManagerBase &PM);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addPreEmitPass(PassManagerBase &PM);
virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, virtual bool addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE); JITCodeEmitter &JCE);
}; };
@ -85,7 +86,8 @@ class X86_32TargetMachine : public X86TargetMachine {
public: public:
X86_32TargetMachine(const Target &T, StringRef TT, X86_32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual const X86TargetLowering *getTargetLowering() const { virtual const X86TargetLowering *getTargetLowering() const {
return &TLInfo; return &TLInfo;
@ -112,7 +114,8 @@ class X86_64TargetMachine : public X86TargetMachine {
public: public:
X86_64TargetMachine(const Target &T, StringRef TT, X86_64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual const X86TargetLowering *getTargetLowering() const { virtual const X86TargetLowering *getTargetLowering() const {
return &TLInfo; return &TLInfo;

5
lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
View File

@ -61,9 +61,10 @@ static MCAsmInfo *createXCoreMCAsmInfo(const Target &T, StringRef TT) {
} }
static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM) { CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo(); MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM, CM); X->InitMCCodeGenInfo(RM, CM, OL);
return X; return X;
} }

8
lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -21,8 +21,9 @@ using namespace llvm;
/// ///
XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM) Reloc::Model RM, CodeModel::Model CM,
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM), CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
Subtarget(TT, CPU, FS), Subtarget(TT, CPU, FS),
DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-" DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
"i16:16:32-i32:32:32-i64:32:32-n32"), "i16:16:32-i32:32:32-i64:32:32-n32"),
@ -32,8 +33,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
TSInfo(*this) { TSInfo(*this) {
} }
bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM, bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM) {
CodeGenOpt::Level OptLevel) {
PM.add(createXCoreISelDag(*this)); PM.add(createXCoreISelDag(*this));
return false; return false;
} }

5
lib/Target/XCore/XCoreTargetMachine.h
View File

@ -34,7 +34,8 @@ class XCoreTargetMachine : public LLVMTargetMachine {
public: public:
XCoreTargetMachine(const Target &T, StringRef TT, XCoreTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
Reloc::Model RM, CodeModel::Model CM); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const XCoreFrameLowering *getFrameLowering() const { virtual const XCoreFrameLowering *getFrameLowering() const {
@ -55,7 +56,7 @@ public:
virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const TargetData *getTargetData() const { return &DataLayout; }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addInstSelector(PassManagerBase &PM);
}; };
} // end namespace llvm } // end namespace llvm

28
tools/llc/llc.cpp
View File

@ -306,10 +306,22 @@ int main(int argc, char **argv) {
FeaturesStr = Features.getString(); FeaturesStr = Features.getString();
} }
CodeGenOpt::Level OLvl = CodeGenOpt::Default;
switch (OptLevel) {
default:
errs() << argv[0] << ": invalid optimization level.\n";
return 1;
case ' ': break;
case '0': OLvl = CodeGenOpt::None; break;
case '1': OLvl = CodeGenOpt::Less; break;
case '2': OLvl = CodeGenOpt::Default; break;
case '3': OLvl = CodeGenOpt::Aggressive; break;
}
std::auto_ptr<TargetMachine> std::auto_ptr<TargetMachine>
target(TheTarget->createTargetMachine(TheTriple.getTriple(), target(TheTarget->createTargetMachine(TheTriple.getTriple(),
MCPU, FeaturesStr, MCPU, FeaturesStr,
RelocModel, CMModel)); RelocModel, CMModel, OLvl));
assert(target.get() && "Could not allocate target machine!"); assert(target.get() && "Could not allocate target machine!");
TargetMachine &Target = *target.get(); TargetMachine &Target = *target.get();
@ -332,18 +344,6 @@ int main(int argc, char **argv) {
(GetOutputStream(TheTarget->getName(), TheTriple.getOS(), argv[0])); (GetOutputStream(TheTarget->getName(), TheTriple.getOS(), argv[0]));
if (!Out) return 1; if (!Out) return 1;
CodeGenOpt::Level OLvl = CodeGenOpt::Default;
switch (OptLevel) {
default:
errs() << argv[0] << ": invalid optimization level.\n";
return 1;
case ' ': break;
case '0': OLvl = CodeGenOpt::None; break;
case '1': OLvl = CodeGenOpt::Less; break;
case '2': OLvl = CodeGenOpt::Default; break;
case '3': OLvl = CodeGenOpt::Aggressive; break;
}
// Build up all of the passes that we want to do to the module. // Build up all of the passes that we want to do to the module.
PassManager PM; PassManager PM;
@ -368,7 +368,7 @@ int main(int argc, char **argv) {
formatted_raw_ostream FOS(Out->os()); formatted_raw_ostream FOS(Out->os());
// Ask the target to add backend passes as necessary. // Ask the target to add backend passes as necessary.
if (Target.addPassesToEmitFile(PM, FOS, FileType, OLvl, NoVerify)) { if (Target.addPassesToEmitFile(PM, FOS, FileType, NoVerify)) {
errs() << argv[0] << ": target does not support generation of this" errs() << argv[0] << ": target does not support generation of this"
<< " file type!\n"; << " file type!\n";
return 1; return 1;