diff --git a/test/MC/RISCV/rv32a-valid.s b/test/MC/RISCV/rv32a-valid.s index fe53fab80ad..9b1b9f92c4c 100644 --- a/test/MC/RISCV/rv32a-valid.s +++ b/test/MC/RISCV/rv32a-valid.s @@ -1,148 +1,148 @@ # RUN: llvm-mc %s -triple=riscv32 -mattr=+a -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+a < %s \ -# RUN: | llvm-objdump -mattr=+a -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+a < %s \ -# RUN: | llvm-objdump -mattr=+a -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a < %s \ +# RUN: | llvm-objdump -mattr=+a -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \ +# RUN: | llvm-objdump -mattr=+a -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s -# CHECK-INST: lr.w t0, (t1) -# CHECK: encoding: [0xaf,0x22,0x03,0x10] +# CHECK-ASM-AND-OBJ: lr.w t0, (t1) +# CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10] lr.w t0, (t1) -# CHECK-INST: lr.w.aq t1, (t2) -# CHECK: encoding: [0x2f,0xa3,0x03,0x14] +# CHECK-ASM-AND-OBJ: lr.w.aq t1, (t2) +# CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14] lr.w.aq t1, (t2) -# CHECK-INST: lr.w.rl t2, (t3) -# CHECK: encoding: [0xaf,0x23,0x0e,0x12] +# CHECK-ASM-AND-OBJ: lr.w.rl t2, (t3) +# CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12] lr.w.rl t2, (t3) -# CHECK-INST: lr.w.aqrl t3, (t4) -# CHECK: encoding: [0x2f,0xae,0x0e,0x16] +# CHECK-ASM-AND-OBJ: lr.w.aqrl t3, (t4) +# CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16] lr.w.aqrl t3, (t4) -# CHECK-INST: sc.w t6, t5, (t4) -# CHECK: encoding: [0xaf,0xaf,0xee,0x19] +# CHECK-ASM-AND-OBJ: sc.w t6, t5, (t4) +# CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19] sc.w t6, t5, (t4) -# CHECK-INST: sc.w.aq t5, t4, (t3) -# CHECK: encoding: [0x2f,0x2f,0xde,0x1d] +# CHECK-ASM-AND-OBJ: sc.w.aq t5, t4, (t3) +# CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d] sc.w.aq t5, t4, (t3) -# CHECK-INST: sc.w.rl t4, t3, (t2) -# CHECK: encoding: [0xaf,0xae,0xc3,0x1b] +# CHECK-ASM-AND-OBJ: sc.w.rl t4, t3, (t2) +# CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b] sc.w.rl t4, t3, (t2) -# CHECK-INST: sc.w.aqrl t3, t2, (t1) -# CHECK: encoding: [0x2f,0x2e,0x73,0x1e] +# CHECK-ASM-AND-OBJ: sc.w.aqrl t3, t2, (t1) +# CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e] sc.w.aqrl t3, t2, (t1) -# CHECK-INST: amoswap.w a4, ra, (s0) -# CHECK: encoding: [0x2f,0x27,0x14,0x08] +# CHECK-ASM-AND-OBJ: amoswap.w a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x08] amoswap.w a4, ra, (s0) -# CHECK-INST: amoadd.w a1, a2, (a3) -# CHECK: encoding: [0xaf,0xa5,0xc6,0x00] +# CHECK-ASM-AND-OBJ: amoadd.w a1, a2, (a3) +# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x00] amoadd.w a1, a2, (a3) -# CHECK-INST: amoxor.w a2, a3, (a4) -# CHECK: encoding: [0x2f,0x26,0xd7,0x20] +# CHECK-ASM-AND-OBJ: amoxor.w a2, a3, (a4) +# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x20] amoxor.w a2, a3, (a4) -# CHECK-INST: amoand.w a3, a4, (a5) -# CHECK: encoding: [0xaf,0xa6,0xe7,0x60] +# CHECK-ASM-AND-OBJ: amoand.w a3, a4, (a5) +# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x60] amoand.w a3, a4, (a5) -# CHECK-INST: amoor.w a4, a5, (a6) -# CHECK: encoding: [0x2f,0x27,0xf8,0x40] +# CHECK-ASM-AND-OBJ: amoor.w a4, a5, (a6) +# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x40] amoor.w a4, a5, (a6) -# CHECK-INST: amomin.w a5, a6, (a7) -# CHECK: encoding: [0xaf,0xa7,0x08,0x81] +# CHECK-ASM-AND-OBJ: amomin.w a5, a6, (a7) +# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x81] amomin.w a5, a6, (a7) -# CHECK-INST: amomax.w s7, s6, (s5) -# CHECK: encoding: [0xaf,0xab,0x6a,0xa1] +# CHECK-ASM-AND-OBJ: amomax.w s7, s6, (s5) +# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa1] amomax.w s7, s6, (s5) -# CHECK-INST: amominu.w s6, s5, (s4) -# CHECK: encoding: [0x2f,0x2b,0x5a,0xc1] +# CHECK-ASM-AND-OBJ: amominu.w s6, s5, (s4) +# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc1] amominu.w s6, s5, (s4) -# CHECK-INST: amomaxu.w s5, s4, (s3) -# CHECK: encoding: [0xaf,0xaa,0x49,0xe1] +# CHECK-ASM-AND-OBJ: amomaxu.w s5, s4, (s3) +# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe1] amomaxu.w s5, s4, (s3) -# CHECK-INST: amoswap.w.aq a4, ra, (s0) -# CHECK: encoding: [0x2f,0x27,0x14,0x0c] +# CHECK-ASM-AND-OBJ: amoswap.w.aq a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0c] amoswap.w.aq a4, ra, (s0) -# CHECK-INST: amoadd.w.aq a1, a2, (a3) -# CHECK: encoding: [0xaf,0xa5,0xc6,0x04] +# CHECK-ASM-AND-OBJ: amoadd.w.aq a1, a2, (a3) +# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x04] amoadd.w.aq a1, a2, (a3) -# CHECK-INST: amoxor.w.aq a2, a3, (a4) -# CHECK: encoding: [0x2f,0x26,0xd7,0x24] +# CHECK-ASM-AND-OBJ: amoxor.w.aq a2, a3, (a4) +# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x24] amoxor.w.aq a2, a3, (a4) -# CHECK-INST: amoand.w.aq a3, a4, (a5) -# CHECK: encoding: [0xaf,0xa6,0xe7,0x64] +# CHECK-ASM-AND-OBJ: amoand.w.aq a3, a4, (a5) +# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x64] amoand.w.aq a3, a4, (a5) -# CHECK-INST: amoor.w.aq a4, a5, (a6) -# CHECK: encoding: [0x2f,0x27,0xf8,0x44] +# CHECK-ASM-AND-OBJ: amoor.w.aq a4, a5, (a6) +# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x44] amoor.w.aq a4, a5, (a6) -# CHECK-INST: amomin.w.aq a5, a6, (a7) -# CHECK: encoding: [0xaf,0xa7,0x08,0x85] +# CHECK-ASM-AND-OBJ: amomin.w.aq a5, a6, (a7) +# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x85] amomin.w.aq a5, a6, (a7) -# CHECK-INST: amomax.w.aq s7, s6, (s5) -# CHECK: encoding: [0xaf,0xab,0x6a,0xa5] +# CHECK-ASM-AND-OBJ: amomax.w.aq s7, s6, (s5) +# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa5] amomax.w.aq s7, s6, (s5) -# CHECK-INST: amominu.w.aq s6, s5, (s4) -# CHECK: encoding: [0x2f,0x2b,0x5a,0xc5] +# CHECK-ASM-AND-OBJ: amominu.w.aq s6, s5, (s4) +# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc5] amominu.w.aq s6, s5, (s4) -# CHECK-INST: amomaxu.w.aq s5, s4, (s3) -# CHECK: encoding: [0xaf,0xaa,0x49,0xe5] +# CHECK-ASM-AND-OBJ: amomaxu.w.aq s5, s4, (s3) +# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe5] amomaxu.w.aq s5, s4, (s3) -# CHECK-INST: amoswap.w.rl a4, ra, (s0) -# CHECK: encoding: [0x2f,0x27,0x14,0x0a] +# CHECK-ASM-AND-OBJ: amoswap.w.rl a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0a] amoswap.w.rl a4, ra, (s0) -# CHECK-INST: amoadd.w.rl a1, a2, (a3) -# CHECK: encoding: [0xaf,0xa5,0xc6,0x02] +# CHECK-ASM-AND-OBJ: amoadd.w.rl a1, a2, (a3) +# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x02] amoadd.w.rl a1, a2, (a3) -# CHECK-INST: amoxor.w.rl a2, a3, (a4) -# CHECK: encoding: [0x2f,0x26,0xd7,0x22] +# CHECK-ASM-AND-OBJ: amoxor.w.rl a2, a3, (a4) +# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x22] amoxor.w.rl a2, a3, (a4) -# CHECK-INST: amoand.w.rl a3, a4, (a5) -# CHECK: encoding: [0xaf,0xa6,0xe7,0x62] +# CHECK-ASM-AND-OBJ: amoand.w.rl a3, a4, (a5) +# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x62] amoand.w.rl a3, a4, (a5) -# CHECK-INST: amoor.w.rl a4, a5, (a6) -# CHECK: encoding: [0x2f,0x27,0xf8,0x42] +# CHECK-ASM-AND-OBJ: amoor.w.rl a4, a5, (a6) +# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x42] amoor.w.rl a4, a5, (a6) -# CHECK-INST: amomin.w.rl a5, a6, (a7) -# CHECK: encoding: [0xaf,0xa7,0x08,0x83] +# CHECK-ASM-AND-OBJ: amomin.w.rl a5, a6, (a7) +# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x83] amomin.w.rl a5, a6, (a7) -# CHECK-INST: amomax.w.rl s7, s6, (s5) -# CHECK: encoding: [0xaf,0xab,0x6a,0xa3] +# CHECK-ASM-AND-OBJ: amomax.w.rl s7, s6, (s5) +# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa3] amomax.w.rl s7, s6, (s5) -# CHECK-INST: amominu.w.rl s6, s5, (s4) -# CHECK: encoding: [0x2f,0x2b,0x5a,0xc3] +# CHECK-ASM-AND-OBJ: amominu.w.rl s6, s5, (s4) +# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc3] amominu.w.rl s6, s5, (s4) -# CHECK-INST: amomaxu.w.rl s5, s4, (s3) -# CHECK: encoding: [0xaf,0xaa,0x49,0xe3] +# CHECK-ASM-AND-OBJ: amomaxu.w.rl s5, s4, (s3) +# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe3] amomaxu.w.rl s5, s4, (s3) -# CHECK-INST: amoswap.w.aqrl a4, ra, (s0) -# CHECK: encoding: [0x2f,0x27,0x14,0x0e] +# CHECK-ASM-AND-OBJ: amoswap.w.aqrl a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0e] amoswap.w.aqrl a4, ra, (s0) -# CHECK-INST: amoadd.w.aqrl a1, a2, (a3) -# CHECK: encoding: [0xaf,0xa5,0xc6,0x06] +# CHECK-ASM-AND-OBJ: amoadd.w.aqrl a1, a2, (a3) +# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x06] amoadd.w.aqrl a1, a2, (a3) -# CHECK-INST: amoxor.w.aqrl a2, a3, (a4) -# CHECK: encoding: [0x2f,0x26,0xd7,0x26] +# CHECK-ASM-AND-OBJ: amoxor.w.aqrl a2, a3, (a4) +# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x26] amoxor.w.aqrl a2, a3, (a4) -# CHECK-INST: amoand.w.aqrl a3, a4, (a5) -# CHECK: encoding: [0xaf,0xa6,0xe7,0x66] +# CHECK-ASM-AND-OBJ: amoand.w.aqrl a3, a4, (a5) +# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x66] amoand.w.aqrl a3, a4, (a5) -# CHECK-INST: amoor.w.aqrl a4, a5, (a6) -# CHECK: encoding: [0x2f,0x27,0xf8,0x46] +# CHECK-ASM-AND-OBJ: amoor.w.aqrl a4, a5, (a6) +# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x46] amoor.w.aqrl a4, a5, (a6) -# CHECK-INST: amomin.w.aqrl a5, a6, (a7) -# CHECK: encoding: [0xaf,0xa7,0x08,0x87] +# CHECK-ASM-AND-OBJ: amomin.w.aqrl a5, a6, (a7) +# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x87] amomin.w.aqrl a5, a6, (a7) -# CHECK-INST: amomax.w.aqrl s7, s6, (s5) -# CHECK: encoding: [0xaf,0xab,0x6a,0xa7] +# CHECK-ASM-AND-OBJ: amomax.w.aqrl s7, s6, (s5) +# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa7] amomax.w.aqrl s7, s6, (s5) -# CHECK-INST: amominu.w.aqrl s6, s5, (s4) -# CHECK: encoding: [0x2f,0x2b,0x5a,0xc7] +# CHECK-ASM-AND-OBJ: amominu.w.aqrl s6, s5, (s4) +# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc7] amominu.w.aqrl s6, s5, (s4) -# CHECK-INST: amomaxu.w.aqrl s5, s4, (s3) -# CHECK: encoding: [0xaf,0xaa,0x49,0xe7] +# CHECK-ASM-AND-OBJ: amomaxu.w.aqrl s5, s4, (s3) +# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe7] amomaxu.w.aqrl s5, s4, (s3) diff --git a/test/MC/RISCV/rv32c-only-valid.s b/test/MC/RISCV/rv32c-only-valid.s index 01700bcd575..b2fc4152594 100644 --- a/test/MC/RISCV/rv32c-only-valid.s +++ b/test/MC/RISCV/rv32c-only-valid.s @@ -1,7 +1,9 @@ -# RUN: llvm-mc -triple=riscv32 -mattr=+c -riscv-no-aliases -show-encoding < %s \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \ -# RUN: | llvm-objdump -d -riscv-no-aliases - | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv32 -mattr=+c -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c < %s \ +# RUN: | llvm-objdump -mattr=+c -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# # RUN: not llvm-mc -triple riscv32 \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s @@ -9,7 +11,9 @@ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s -# CHECK-INST: c.jal 2046 -# CHECK: encoding: [0xfd,0x2f] -# CHECK-NO-EXT: error: instruction use requires an option to be enabled -c.jal 2046 +# FIXME: error message for c.jal with rv64c is misleading + +# CHECK-ASM-AND-OBJ: c.jal 2046 +# CHECK-ASM: encoding: [0xfd,0x2f] +# CHECK-NO-EXT: error: instruction use requires an option to be enabled +c.jal 2046 diff --git a/test/MC/RISCV/rv32c-valid.s b/test/MC/RISCV/rv32c-valid.s index 449e3be51a7..c761c712789 100644 --- a/test/MC/RISCV/rv32c-valid.s +++ b/test/MC/RISCV/rv32c-valid.s @@ -1,105 +1,105 @@ -# RUN: llvm-mc -triple=riscv32 -mattr=+c -riscv-no-aliases -show-encoding < %s \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -triple=riscv64 -mattr=+c -riscv-no-aliases -show-encoding < %s \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \ -# RUN: | llvm-objdump -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c < %s \ -# RUN: | llvm-objdump -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv32 -mattr=+c -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c < %s \ +# RUN: | llvm-objdump -mattr=+c -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+c -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \ +# RUN: | llvm-objdump -mattr=+c -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s # TODO: more exhaustive testing of immediate encoding. -# CHECK-INST: c.lwsp ra, 0(sp) -# CHECK: encoding: [0x82,0x40] -c.lwsp ra, 0(sp) -# CHECK-INST: c.swsp ra, 252(sp) -# CHECK: encoding: [0x86,0xdf] -c.swsp ra, 252(sp) -# CHECK-INST: c.lw a2, 0(a0) -# CHECK: encoding: [0x10,0x41] -c.lw a2, 0(a0) -# CHECK-INST: c.sw a5, 124(a3) -# CHECK: encoding: [0xfc,0xde] -c.sw a5, 124(a3) +# CHECK-ASM-AND-OBJ: c.lwsp ra, 0(sp) +# CHECK-ASM: encoding: [0x82,0x40] +c.lwsp ra, 0(sp) +# CHECK-ASM-AND-OBJ: c.swsp ra, 252(sp) +# CHECK-ASM: encoding: [0x86,0xdf] +c.swsp ra, 252(sp) +# CHECK-ASM-AND-OBJ: c.lw a2, 0(a0) +# CHECK-ASM: encoding: [0x10,0x41] +c.lw a2, 0(a0) +# CHECK-ASM-AND-OBJ: c.sw a5, 124(a3) +# CHECK-ASM: encoding: [0xfc,0xde] +c.sw a5, 124(a3) -# CHECK-INST: c.j -2048 -# CHECK: encoding: [0x01,0xb0] -c.j -2048 -# CHECK-INST: c.jr a7 -# CHECK: encoding: [0x82,0x88] -c.jr a7 -# CHECK-INST: c.jalr a1 -# CHECK: encoding: [0x82,0x95] -c.jalr a1 -# CHECK-INST: c.beqz a3, -256 -# CHECK: encoding: [0x81,0xd2] -c.beqz a3, -256 -# CHECK-INST: c.bnez a5, 254 -# CHECK: encoding: [0xfd,0xef] -c.bnez a5, 254 +# CHECK-ASM-AND-OBJ: c.j -2048 +# CHECK-ASM: encoding: [0x01,0xb0] +c.j -2048 +# CHECK-ASM-AND-OBJ: c.jr a7 +# CHECK-ASM: encoding: [0x82,0x88] +c.jr a7 +# CHECK-ASM-AND-OBJ: c.jalr a1 +# CHECK-ASM: encoding: [0x82,0x95] +c.jalr a1 +# CHECK-ASM-AND-OBJ: c.beqz a3, -256 +# CHECK-ASM: encoding: [0x81,0xd2] +c.beqz a3, -256 +# CHECK-ASM-AND-OBJ: c.bnez a5, 254 +# CHECK-ASM: encoding: [0xfd,0xef] +c.bnez a5, 254 -# CHECK-INST: c.li a7, 31 -# CHECK: encoding: [0xfd,0x48] -c.li a7, 31 -# CHECK-INST: c.addi a3, -32 -# CHECK: encoding: [0x81,0x16] -c.addi a3, -32 -# CHECK-INST: c.addi16sp sp, -512 -# CHECK: encoding: [0x01,0x71] -c.addi16sp sp, -512 -# CHECK-INST: c.addi16sp sp, 496 -# CHECK: encoding: [0x7d,0x61] -c.addi16sp sp, 496 -# CHECK-INST: c.addi4spn a3, sp, 1020 -# CHECK: encoding: [0xf4,0x1f] -c.addi4spn a3, sp, 1020 -# CHECK-INST: c.addi4spn a3, sp, 4 -# CHECK: encoding: [0x54,0x00] -c.addi4spn a3, sp, 4 -# CHECK-INST: c.slli a1, 1 -# CHECK: encoding: [0x86,0x05] -c.slli a1, 1 -# CHECK-INST: c.srli a3, 31 -# CHECK: encoding: [0xfd,0x82] -c.srli a3, 31 -# CHECK-INST: c.srai a4, 2 -# CHECK: encoding: [0x09,0x87] -c.srai a4, 2 -# CHECK-INST: c.andi a5, 15 -# CHECK: encoding: [0xbd,0x8b] -c.andi a5, 15 -# CHECK-INST: c.mv a7, s0 -# CHECK: encoding: [0xa2,0x88] -c.mv a7, s0 -# CHECK-INST: c.and a1, a2 -# CHECK: encoding: [0xf1,0x8d] -c.and a1, a2 -# CHECK-INST: c.or a2, a3 -# CHECK: encoding: [0x55,0x8e] -c.or a2, a3 -# CHECK-INST: c.xor a3, a4 -# CHECK: encoding: [0xb9,0x8e] -c.xor a3, a4 -# CHECK-INST: c.sub a4, a5 -# CHECK: encoding: [0x1d,0x8f] -c.sub a4, a5 -# CHECK-INST: c.nop -# CHECK: encoding: [0x01,0x00] +# CHECK-ASM-AND-OBJ: c.li a7, 31 +# CHECK-ASM: encoding: [0xfd,0x48] +c.li a7, 31 +# CHECK-ASM-AND-OBJ: c.addi a3, -32 +# CHECK-ASM: encoding: [0x81,0x16] +c.addi a3, -32 +# CHECK-ASM-AND-OBJ: c.addi16sp sp, -512 +# CHECK-ASM: encoding: [0x01,0x71] +c.addi16sp sp, -512 +# CHECK-ASM-AND-OBJ: c.addi16sp sp, 496 +# CHECK-ASM: encoding: [0x7d,0x61] +c.addi16sp sp, 496 +# CHECK-ASM-AND-OBJ: c.addi4spn a3, sp, 1020 +# CHECK-ASM: encoding: [0xf4,0x1f] +c.addi4spn a3, sp, 1020 +# CHECK-ASM-AND-OBJ: c.addi4spn a3, sp, 4 +# CHECK-ASM: encoding: [0x54,0x00] +c.addi4spn a3, sp, 4 +# CHECK-ASM-AND-OBJ: c.slli a1, 1 +# CHECK-ASM: encoding: [0x86,0x05] +c.slli a1, 1 +# CHECK-ASM-AND-OBJ: c.srli a3, 31 +# CHECK-ASM: encoding: [0xfd,0x82] +c.srli a3, 31 +# CHECK-ASM-AND-OBJ: c.srai a4, 2 +# CHECK-ASM: encoding: [0x09,0x87] +c.srai a4, 2 +# CHECK-ASM-AND-OBJ: c.andi a5, 15 +# CHECK-ASM: encoding: [0xbd,0x8b] +c.andi a5, 15 +# CHECK-ASM-AND-OBJ: c.mv a7, s0 +# CHECK-ASM: encoding: [0xa2,0x88] +c.mv a7, s0 +# CHECK-ASM-AND-OBJ: c.and a1, a2 +# CHECK-ASM: encoding: [0xf1,0x8d] +c.and a1, a2 +# CHECK-ASM-AND-OBJ: c.or a2, a3 +# CHECK-ASM: encoding: [0x55,0x8e] +c.or a2, a3 +# CHECK-ASM-AND-OBJ: c.xor a3, a4 +# CHECK-ASM: encoding: [0xb9,0x8e] +c.xor a3, a4 +# CHECK-ASM-AND-OBJ: c.sub a4, a5 +# CHECK-ASM: encoding: [0x1d,0x8f] +c.sub a4, a5 +# CHECK-ASM-AND-OBJ: c.nop +# CHECK-ASM: encoding: [0x01,0x00] c.nop -# CHECK-INST: c.ebreak -# CHECK: encoding: [0x02,0x90] +# CHECK-ASM-AND-OBJ: c.ebreak +# CHECK-ASM: encoding: [0x02,0x90] c.ebreak -# CHECK-INST: c.lui s0, 1 -# CHECK: encoding: [0x05,0x64] -c.lui s0, 1 -# CHECK-INST: c.lui s0, 31 -# CHECK: encoding: [0x7d,0x64] -c.lui s0, 31 -# CHECK-INST: c.lui s0, 1048544 -# CHECK: encoding: [0x01,0x74] -c.lui s0, 0xfffe0 -# CHECK-INST: c.lui s0, 1048575 -# CHECK: encoding: [0x7d,0x74] -c.lui s0, 0xfffff +# CHECK-ASM-AND-OBJ: c.lui s0, 1 +# CHECK-ASM: encoding: [0x05,0x64] +c.lui s0, 1 +# CHECK-ASM-AND-OBJ: c.lui s0, 31 +# CHECK-ASM: encoding: [0x7d,0x64] +c.lui s0, 31 +# CHECK-ASM-AND-OBJ: c.lui s0, 1048544 +# CHECK-ASM: encoding: [0x01,0x74] +c.lui s0, 0xfffe0 +# CHECK-ASM-AND-OBJ: c.lui s0, 1048575 +# CHECK-ASM: encoding: [0x7d,0x74] +c.lui s0, 0xfffff diff --git a/test/MC/RISCV/rv32d-valid.s b/test/MC/RISCV/rv32d-valid.s index 0e54b797c36..551a51500dd 100644 --- a/test/MC/RISCV/rv32d-valid.s +++ b/test/MC/RISCV/rv32d-valid.s @@ -1,161 +1,161 @@ # RUN: llvm-mc %s -triple=riscv32 -mattr=+d -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+d < %s \ +# RUN: | llvm-objdump -mattr=+d -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc %s -triple=riscv64 -mattr=+d -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+d < %s \ -# RUN: | llvm-objdump -mattr=+d -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+d < %s \ -# RUN: | llvm-objdump -mattr=+d -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+d < %s \ +# RUN: | llvm-objdump -mattr=+d -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s # Support for the 'D' extension implies support for 'F' -# CHECK-INST: fadd.s fs10, fs11, ft8 -# CHECK: encoding: [0x53,0xfd,0xcd,0x01] +# CHECK-ASM-AND-OBJ: fadd.s fs10, fs11, ft8 +# CHECK-ASM: encoding: [0x53,0xfd,0xcd,0x01] fadd.s f26, f27, f28 -# CHECK-INST: fld ft0, 12(a0) -# CHECK: encoding: [0x07,0x30,0xc5,0x00] +# CHECK-ASM-AND-OBJ: fld ft0, 12(a0) +# CHECK-ASM: encoding: [0x07,0x30,0xc5,0x00] fld f0, 12(a0) -# CHECK-INST: fld ft1, 4(ra) -# CHECK: encoding: [0x87,0xb0,0x40,0x00] +# CHECK-ASM-AND-OBJ: fld ft1, 4(ra) +# CHECK-ASM: encoding: [0x87,0xb0,0x40,0x00] fld f1, +4(ra) -# CHECK-INST: fld ft2, -2048(a3) -# CHECK: encoding: [0x07,0xb1,0x06,0x80] +# CHECK-ASM-AND-OBJ: fld ft2, -2048(a3) +# CHECK-ASM: encoding: [0x07,0xb1,0x06,0x80] fld f2, -2048(x13) -# CHECK-INST: fld ft3, -2048(s1) -# CHECK: encoding: [0x87,0xb1,0x04,0x80] +# CHECK-ASM-AND-OBJ: fld ft3, -2048(s1) +# CHECK-ASM: encoding: [0x87,0xb1,0x04,0x80] fld f3, %lo(2048)(s1) -# CHECK-INST: fld ft4, 2047(s2) -# CHECK: encoding: [0x07,0x32,0xf9,0x7f] +# CHECK-ASM-AND-OBJ: fld ft4, 2047(s2) +# CHECK-ASM: encoding: [0x07,0x32,0xf9,0x7f] fld f4, 2047(s2) -# CHECK-INST: fld ft5, 0(s3) -# CHECK: encoding: [0x87,0xb2,0x09,0x00] +# CHECK-ASM-AND-OBJ: fld ft5, 0(s3) +# CHECK-ASM: encoding: [0x87,0xb2,0x09,0x00] fld f5, 0(s3) -# CHECK-INST: fsd ft6, 2047(s4) -# CHECK: encoding: [0xa7,0x3f,0x6a,0x7e] +# CHECK-ASM-AND-OBJ: fsd ft6, 2047(s4) +# CHECK-ASM: encoding: [0xa7,0x3f,0x6a,0x7e] fsd f6, 2047(s4) -# CHECK-INST: fsd ft7, -2048(s5) -# CHECK: encoding: [0x27,0xb0,0x7a,0x80] +# CHECK-ASM-AND-OBJ: fsd ft7, -2048(s5) +# CHECK-ASM: encoding: [0x27,0xb0,0x7a,0x80] fsd f7, -2048(s5) -# CHECK-INST: fsd fs0, -2048(s6) -# CHECK: encoding: [0x27,0x30,0x8b,0x80] +# CHECK-ASM-AND-OBJ: fsd fs0, -2048(s6) +# CHECK-ASM: encoding: [0x27,0x30,0x8b,0x80] fsd f8, %lo(2048)(s6) -# CHECK-INST: fsd fs1, 999(s7) -# CHECK: encoding: [0xa7,0xb3,0x9b,0x3e] +# CHECK-ASM-AND-OBJ: fsd fs1, 999(s7) +# CHECK-ASM: encoding: [0xa7,0xb3,0x9b,0x3e] fsd f9, 999(s7) -# CHECK-INST: fmadd.d fa0, fa1, fa2, fa3, dyn -# CHECK: encoding: [0x43,0xf5,0xc5,0x6a] +# CHECK-ASM-AND-OBJ: fmadd.d fa0, fa1, fa2, fa3, dyn +# CHECK-ASM: encoding: [0x43,0xf5,0xc5,0x6a] fmadd.d f10, f11, f12, f13, dyn -# CHECK-INST: fmsub.d fa4, fa5, fa6, fa7, dyn -# CHECK: encoding: [0x47,0xf7,0x07,0x8b] +# CHECK-ASM-AND-OBJ: fmsub.d fa4, fa5, fa6, fa7, dyn +# CHECK-ASM: encoding: [0x47,0xf7,0x07,0x8b] fmsub.d f14, f15, f16, f17, dyn -# CHECK-INST: fnmsub.d fs2, fs3, fs4, fs5, dyn -# CHECK: encoding: [0x4b,0xf9,0x49,0xab] +# CHECK-ASM-AND-OBJ: fnmsub.d fs2, fs3, fs4, fs5, dyn +# CHECK-ASM: encoding: [0x4b,0xf9,0x49,0xab] fnmsub.d f18, f19, f20, f21, dyn -# CHECK-INST: fnmadd.d fs6, fs7, fs8, fs9, dyn -# CHECK: encoding: [0x4f,0xfb,0x8b,0xcb] +# CHECK-ASM-AND-OBJ: fnmadd.d fs6, fs7, fs8, fs9, dyn +# CHECK-ASM: encoding: [0x4f,0xfb,0x8b,0xcb] fnmadd.d f22, f23, f24, f25, dyn -# CHECK-INST: fadd.d fs10, fs11, ft8, dyn -# CHECK: encoding: [0x53,0xfd,0xcd,0x03] +# CHECK-ASM-AND-OBJ: fadd.d fs10, fs11, ft8, dyn +# CHECK-ASM: encoding: [0x53,0xfd,0xcd,0x03] fadd.d f26, f27, f28, dyn -# CHECK-INST: fsub.d ft9, ft10, ft11, dyn -# CHECK: encoding: [0xd3,0x7e,0xff,0x0b] +# CHECK-ASM-AND-OBJ: fsub.d ft9, ft10, ft11, dyn +# CHECK-ASM: encoding: [0xd3,0x7e,0xff,0x0b] fsub.d f29, f30, f31, dyn -# CHECK-INST: fmul.d ft0, ft1, ft2, dyn -# CHECK: encoding: [0x53,0xf0,0x20,0x12] +# CHECK-ASM-AND-OBJ: fmul.d ft0, ft1, ft2, dyn +# CHECK-ASM: encoding: [0x53,0xf0,0x20,0x12] fmul.d ft0, ft1, ft2, dyn -# CHECK-INST: fdiv.d ft3, ft4, ft5, dyn -# CHECK: encoding: [0xd3,0x71,0x52,0x1a] +# CHECK-ASM-AND-OBJ: fdiv.d ft3, ft4, ft5, dyn +# CHECK-ASM: encoding: [0xd3,0x71,0x52,0x1a] fdiv.d ft3, ft4, ft5, dyn -# CHECK-INST: fsqrt.d ft6, ft7, dyn -# CHECK: encoding: [0x53,0xf3,0x03,0x5a] +# CHECK-ASM-AND-OBJ: fsqrt.d ft6, ft7, dyn +# CHECK-ASM: encoding: [0x53,0xf3,0x03,0x5a] fsqrt.d ft6, ft7, dyn -# CHECK-INST: fsgnj.d fs1, fa0, fa1 -# CHECK: encoding: [0xd3,0x04,0xb5,0x22] +# CHECK-ASM-AND-OBJ: fsgnj.d fs1, fa0, fa1 +# CHECK-ASM: encoding: [0xd3,0x04,0xb5,0x22] fsgnj.d fs1, fa0, fa1 -# CHECK-INST: fsgnjn.d fa1, fa3, fa4 -# CHECK: encoding: [0xd3,0x95,0xe6,0x22] +# CHECK-ASM-AND-OBJ: fsgnjn.d fa1, fa3, fa4 +# CHECK-ASM: encoding: [0xd3,0x95,0xe6,0x22] fsgnjn.d fa1, fa3, fa4 -# CHECK-INST: fsgnjx.d fa3, fa2, fa1 -# CHECK: encoding: [0xd3,0x26,0xb6,0x22] +# CHECK-ASM-AND-OBJ: fsgnjx.d fa3, fa2, fa1 +# CHECK-ASM: encoding: [0xd3,0x26,0xb6,0x22] fsgnjx.d fa3, fa2, fa1 -# CHECK-INST: fmin.d fa5, fa6, fa7 -# CHECK: encoding: [0xd3,0x07,0x18,0x2b] +# CHECK-ASM-AND-OBJ: fmin.d fa5, fa6, fa7 +# CHECK-ASM: encoding: [0xd3,0x07,0x18,0x2b] fmin.d fa5, fa6, fa7 -# CHECK-INST: fmax.d fs2, fs3, fs4 -# CHECK: encoding: [0x53,0x99,0x49,0x2b] +# CHECK-ASM-AND-OBJ: fmax.d fs2, fs3, fs4 +# CHECK-ASM: encoding: [0x53,0x99,0x49,0x2b] fmax.d fs2, fs3, fs4 -# CHECK-INST: fcvt.s.d fs5, fs6, dyn -# CHECK: encoding: [0xd3,0x7a,0x1b,0x40] +# CHECK-ASM-AND-OBJ: fcvt.s.d fs5, fs6, dyn +# CHECK-ASM: encoding: [0xd3,0x7a,0x1b,0x40] fcvt.s.d fs5, fs6, dyn -# CHECK-INST: fcvt.d.s fs7, fs8 -# CHECK: encoding: [0xd3,0x0b,0x0c,0x42] +# CHECK-ASM-AND-OBJ: fcvt.d.s fs7, fs8 +# CHECK-ASM: encoding: [0xd3,0x0b,0x0c,0x42] fcvt.d.s fs7, fs8 -# CHECK-INST: feq.d a1, fs8, fs9 -# CHECK: encoding: [0xd3,0x25,0x9c,0xa3] +# CHECK-ASM-AND-OBJ: feq.d a1, fs8, fs9 +# CHECK-ASM: encoding: [0xd3,0x25,0x9c,0xa3] feq.d a1, fs8, fs9 -# CHECK-INST: flt.d a2, fs10, fs11 -# CHECK: encoding: [0x53,0x16,0xbd,0xa3] +# CHECK-ASM-AND-OBJ: flt.d a2, fs10, fs11 +# CHECK-ASM: encoding: [0x53,0x16,0xbd,0xa3] flt.d a2, fs10, fs11 -# CHECK-INST: fle.d a3, ft8, ft9 -# CHECK: encoding: [0xd3,0x06,0xde,0xa3] +# CHECK-ASM-AND-OBJ: fle.d a3, ft8, ft9 +# CHECK-ASM: encoding: [0xd3,0x06,0xde,0xa3] fle.d a3, ft8, ft9 -# CHECK-INST: fclass.d a3, ft10 -# CHECK: encoding: [0xd3,0x16,0x0f,0xe2] +# CHECK-ASM-AND-OBJ: fclass.d a3, ft10 +# CHECK-ASM: encoding: [0xd3,0x16,0x0f,0xe2] fclass.d a3, ft10 -# CHECK-INST: fcvt.w.d a4, ft11, dyn -# CHECK: encoding: [0x53,0xf7,0x0f,0xc2] +# CHECK-ASM-AND-OBJ: fcvt.w.d a4, ft11, dyn +# CHECK-ASM: encoding: [0x53,0xf7,0x0f,0xc2] fcvt.w.d a4, ft11, dyn -# CHECK-INST: fcvt.d.w ft0, a5 -# CHECK: encoding: [0x53,0x80,0x07,0xd2] +# CHECK-ASM-AND-OBJ: fcvt.d.w ft0, a5 +# CHECK-ASM: encoding: [0x53,0x80,0x07,0xd2] fcvt.d.w ft0, a5 -# CHECK-INST: fcvt.d.wu ft1, a6 -# CHECK: encoding: [0xd3,0x00,0x18,0xd2] +# CHECK-ASM-AND-OBJ: fcvt.d.wu ft1, a6 +# CHECK-ASM: encoding: [0xd3,0x00,0x18,0xd2] fcvt.d.wu ft1, a6 # Rounding modes -# CHECK-INST: fmadd.d fa0, fa1, fa2, fa3, rne -# CHECK: encoding: [0x43,0x85,0xc5,0x6a] +# CHECK-ASM-AND-OBJ: fmadd.d fa0, fa1, fa2, fa3, rne +# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x6a] fmadd.d f10, f11, f12, f13, rne -# CHECK-INST: fmsub.d fa4, fa5, fa6, fa7, rtz -# CHECK: encoding: [0x47,0x97,0x07,0x8b] +# CHECK-ASM-AND-OBJ: fmsub.d fa4, fa5, fa6, fa7, rtz +# CHECK-ASM: encoding: [0x47,0x97,0x07,0x8b] fmsub.d f14, f15, f16, f17, rtz -# CHECK-INST: fnmsub.d fs2, fs3, fs4, fs5, rdn -# CHECK: encoding: [0x4b,0xa9,0x49,0xab] +# CHECK-ASM-AND-OBJ: fnmsub.d fs2, fs3, fs4, fs5, rdn +# CHECK-ASM: encoding: [0x4b,0xa9,0x49,0xab] fnmsub.d f18, f19, f20, f21, rdn -# CHECK-INST: fnmadd.d fs6, fs7, fs8, fs9, rup -# CHECK: encoding: [0x4f,0xbb,0x8b,0xcb] +# CHECK-ASM-AND-OBJ: fnmadd.d fs6, fs7, fs8, fs9, rup +# CHECK-ASM: encoding: [0x4f,0xbb,0x8b,0xcb] fnmadd.d f22, f23, f24, f25, rup -# CHECK-INST: fadd.d fs10, fs11, ft8, rmm -# CHECK: encoding: [0x53,0xcd,0xcd,0x03] +# CHECK-ASM-AND-OBJ: fadd.d fs10, fs11, ft8, rmm +# CHECK-ASM: encoding: [0x53,0xcd,0xcd,0x03] fadd.d f26, f27, f28, rmm -# CHECK-INST: fsub.d ft9, ft10, ft11 -# CHECK: encoding: [0xd3,0x7e,0xff,0x0b] +# CHECK-ASM-AND-OBJ: fsub.d ft9, ft10, ft11 +# CHECK-ASM: encoding: [0xd3,0x7e,0xff,0x0b] fsub.d f29, f30, f31, dyn -# CHECK-INST: fmul.d ft0, ft1, ft2, rne -# CHECK: encoding: [0x53,0x80,0x20,0x12] +# CHECK-ASM-AND-OBJ: fmul.d ft0, ft1, ft2, rne +# CHECK-ASM: encoding: [0x53,0x80,0x20,0x12] fmul.d ft0, ft1, ft2, rne -# CHECK-INST: fdiv.d ft3, ft4, ft5, rtz -# CHECK: encoding: [0xd3,0x11,0x52,0x1a] +# CHECK-ASM-AND-OBJ: fdiv.d ft3, ft4, ft5, rtz +# CHECK-ASM: encoding: [0xd3,0x11,0x52,0x1a] fdiv.d ft3, ft4, ft5, rtz -# CHECK-INST: fsqrt.d ft6, ft7, rdn -# CHECK: encoding: [0x53,0xa3,0x03,0x5a] +# CHECK-ASM-AND-OBJ: fsqrt.d ft6, ft7, rdn +# CHECK-ASM: encoding: [0x53,0xa3,0x03,0x5a] fsqrt.d ft6, ft7, rdn -# CHECK-INST: fcvt.s.d fs5, fs6, rup -# CHECK: encoding: [0xd3,0x3a,0x1b,0x40] +# CHECK-ASM-AND-OBJ: fcvt.s.d fs5, fs6, rup +# CHECK-ASM: encoding: [0xd3,0x3a,0x1b,0x40] fcvt.s.d fs5, fs6, rup -# CHECK-INST: fcvt.w.d a4, ft11, rmm -# CHECK: encoding: [0x53,0xc7,0x0f,0xc2] +# CHECK-ASM-AND-OBJ: fcvt.w.d a4, ft11, rmm +# CHECK-ASM: encoding: [0x53,0xc7,0x0f,0xc2] fcvt.w.d a4, ft11, rmm -# CHECK-INST: fcvt.wu.d a5, ft10, dyn -# CHECK: encoding: [0xd3,0x77,0x1f,0xc2] +# CHECK-ASM-AND-OBJ: fcvt.wu.d a5, ft10, dyn +# CHECK-ASM: encoding: [0xd3,0x77,0x1f,0xc2] fcvt.wu.d a5, ft10, dyn diff --git a/test/MC/RISCV/rv32dc-valid.s b/test/MC/RISCV/rv32dc-valid.s index 764bcbd2fb1..1a9ea317a35 100644 --- a/test/MC/RISCV/rv32dc-valid.s +++ b/test/MC/RISCV/rv32dc-valid.s @@ -1,29 +1,29 @@ # RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+d -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c,+d < %s \ -# RUN: | llvm-objdump -mattr=+d -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: not llvm-mc -triple riscv32 -mattr=+c\ +# RUN: | llvm-objdump -mattr=+c,+d -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv32 -mattr=+c \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s -# RUN: not llvm-mc -triple riscv32 \ -# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s +# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s -# CHECK-INST: c.fldsp fs0, 504(sp) -# CHECK: encoding: [0x7e,0x34] +# CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp) +# CHECK-ASM: encoding: [0x7e,0x34] # CHECK-NO-EXT: error: instruction use requires an option to be enabled c.fldsp fs0, 504(sp) -# CHECK-INST: c.fsdsp fa7, 504(sp) -# CHECK: encoding: [0xc6,0xbf] +# CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp) +# CHECK-ASM: encoding: [0xc6,0xbf] # CHECK-NO-EXT: error: instruction use requires an option to be enabled c.fsdsp fa7, 504(sp) -# CHECK-INST: c.fld fa3, 248(a5) -# CHECK: encoding: [0xf4,0x3f] +# CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5) +# CHECK-ASM: encoding: [0xf4,0x3f] # CHECK-NO-EXT: error: instruction use requires an option to be enabled c.fld fa3, 248(a5) -# CHECK-INST: c.fsd fa2, 248(a1) -# CHECK: encoding: [0xf0,0xbd] +# CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1) +# CHECK-ASM: encoding: [0xf0,0xbd] # CHECK-NO-EXT: error: instruction use requires an option to be enabled c.fsd fa2, 248(a1) diff --git a/test/MC/RISCV/rv32f-valid.s b/test/MC/RISCV/rv32f-valid.s index f5da84ac2bd..9cf9164f0ab 100644 --- a/test/MC/RISCV/rv32f-valid.s +++ b/test/MC/RISCV/rv32f-valid.s @@ -1,166 +1,166 @@ # RUN: llvm-mc %s -triple=riscv32 -mattr=+f -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc %s -triple=riscv64 -mattr=+f -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ -# RUN: | llvm-objdump -mattr=+f -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump -mattr=+f -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+f < %s \ +# RUN: | llvm-objdump -mattr=+f -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+f < %s \ +# RUN: | llvm-objdump -mattr=+f -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s -# CHECK-INST: flw ft0, 12(a0) -# CHECK: encoding: [0x07,0x20,0xc5,0x00] +# CHECK-ASM-AND-OBJ: flw ft0, 12(a0) +# CHECK-ASM: encoding: [0x07,0x20,0xc5,0x00] flw f0, 12(a0) -# CHECK-INST: flw ft1, 4(ra) -# CHECK: encoding: [0x87,0xa0,0x40,0x00] +# CHECK-ASM-AND-OBJ: flw ft1, 4(ra) +# CHECK-ASM: encoding: [0x87,0xa0,0x40,0x00] flw f1, +4(ra) -# CHECK-INST: flw ft2, -2048(a3) -# CHECK: encoding: [0x07,0xa1,0x06,0x80] +# CHECK-ASM-AND-OBJ: flw ft2, -2048(a3) +# CHECK-ASM: encoding: [0x07,0xa1,0x06,0x80] flw f2, -2048(x13) -# CHECK-INST: flw ft3, -2048(s1) -# CHECK: encoding: [0x87,0xa1,0x04,0x80] +# CHECK-ASM-AND-OBJ: flw ft3, -2048(s1) +# CHECK-ASM: encoding: [0x87,0xa1,0x04,0x80] flw f3, %lo(2048)(s1) -# CHECK-INST: flw ft4, 2047(s2) -# CHECK: encoding: [0x07,0x22,0xf9,0x7f] +# CHECK-ASM-AND-OBJ: flw ft4, 2047(s2) +# CHECK-ASM: encoding: [0x07,0x22,0xf9,0x7f] flw f4, 2047(s2) -# CHECK-INST: flw ft5, 0(s3) -# CHECK: encoding: [0x87,0xa2,0x09,0x00] +# CHECK-ASM-AND-OBJ: flw ft5, 0(s3) +# CHECK-ASM: encoding: [0x87,0xa2,0x09,0x00] flw f5, 0(s3) -# CHECK-INST: fsw ft6, 2047(s4) -# CHECK: encoding: [0xa7,0x2f,0x6a,0x7e] +# CHECK-ASM-AND-OBJ: fsw ft6, 2047(s4) +# CHECK-ASM: encoding: [0xa7,0x2f,0x6a,0x7e] fsw f6, 2047(s4) -# CHECK-INST: fsw ft7, -2048(s5) -# CHECK: encoding: [0x27,0xa0,0x7a,0x80] +# CHECK-ASM-AND-OBJ: fsw ft7, -2048(s5) +# CHECK-ASM: encoding: [0x27,0xa0,0x7a,0x80] fsw f7, -2048(s5) -# CHECK-INST: fsw fs0, -2048(s6) -# CHECK: encoding: [0x27,0x20,0x8b,0x80] +# CHECK-ASM-AND-OBJ: fsw fs0, -2048(s6) +# CHECK-ASM: encoding: [0x27,0x20,0x8b,0x80] fsw f8, %lo(2048)(s6) -# CHECK-INST: fsw fs1, 999(s7) -# CHECK: encoding: [0xa7,0xa3,0x9b,0x3e] +# CHECK-ASM-AND-OBJ: fsw fs1, 999(s7) +# CHECK-ASM: encoding: [0xa7,0xa3,0x9b,0x3e] fsw f9, 999(s7) -# CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, dyn -# CHECK: encoding: [0x43,0xf5,0xc5,0x68] +# CHECK-ASM-AND-OBJ: fmadd.s fa0, fa1, fa2, fa3, dyn +# CHECK-ASM: encoding: [0x43,0xf5,0xc5,0x68] fmadd.s f10, f11, f12, f13, dyn -# CHECK-INST: fmsub.s fa4, fa5, fa6, fa7, dyn -# CHECK: encoding: [0x47,0xf7,0x07,0x89] +# CHECK-ASM-AND-OBJ: fmsub.s fa4, fa5, fa6, fa7, dyn +# CHECK-ASM: encoding: [0x47,0xf7,0x07,0x89] fmsub.s f14, f15, f16, f17, dyn -# CHECK-INST: fnmsub.s fs2, fs3, fs4, fs5, dyn -# CHECK: encoding: [0x4b,0xf9,0x49,0xa9] +# CHECK-ASM-AND-OBJ: fnmsub.s fs2, fs3, fs4, fs5, dyn +# CHECK-ASM: encoding: [0x4b,0xf9,0x49,0xa9] fnmsub.s f18, f19, f20, f21, dyn -# CHECK-INST: fnmadd.s fs6, fs7, fs8, fs9, dyn -# CHECK: encoding: [0x4f,0xfb,0x8b,0xc9] +# CHECK-ASM-AND-OBJ: fnmadd.s fs6, fs7, fs8, fs9, dyn +# CHECK-ASM: encoding: [0x4f,0xfb,0x8b,0xc9] fnmadd.s f22, f23, f24, f25, dyn -# CHECK-INST: fadd.s fs10, fs11, ft8, dyn -# CHECK: encoding: [0x53,0xfd,0xcd,0x01] +# CHECK-ASM-AND-OBJ: fadd.s fs10, fs11, ft8, dyn +# CHECK-ASM: encoding: [0x53,0xfd,0xcd,0x01] fadd.s f26, f27, f28, dyn -# CHECK-INST: fsub.s ft9, ft10, ft11, dyn -# CHECK: encoding: [0xd3,0x7e,0xff,0x09] +# CHECK-ASM-AND-OBJ: fsub.s ft9, ft10, ft11, dyn +# CHECK-ASM: encoding: [0xd3,0x7e,0xff,0x09] fsub.s f29, f30, f31, dyn -# CHECK-INST: fmul.s ft0, ft1, ft2, dyn -# CHECK: encoding: [0x53,0xf0,0x20,0x10] +# CHECK-ASM-AND-OBJ: fmul.s ft0, ft1, ft2, dyn +# CHECK-ASM: encoding: [0x53,0xf0,0x20,0x10] fmul.s ft0, ft1, ft2, dyn -# CHECK-INST: fdiv.s ft3, ft4, ft5, dyn -# CHECK: encoding: [0xd3,0x71,0x52,0x18] +# CHECK-ASM-AND-OBJ: fdiv.s ft3, ft4, ft5, dyn +# CHECK-ASM: encoding: [0xd3,0x71,0x52,0x18] fdiv.s ft3, ft4, ft5, dyn -# CHECK-INST: fsqrt.s ft6, ft7, dyn -# CHECK: encoding: [0x53,0xf3,0x03,0x58] +# CHECK-ASM-AND-OBJ: fsqrt.s ft6, ft7, dyn +# CHECK-ASM: encoding: [0x53,0xf3,0x03,0x58] fsqrt.s ft6, ft7, dyn -# CHECK-INST: fsgnj.s fs1, fa0, fa1 -# CHECK: encoding: [0xd3,0x04,0xb5,0x20] +# CHECK-ASM-AND-OBJ: fsgnj.s fs1, fa0, fa1 +# CHECK-ASM: encoding: [0xd3,0x04,0xb5,0x20] fsgnj.s fs1, fa0, fa1 -# CHECK-INST: fsgnjn.s fa1, fa3, fa4 -# CHECK: encoding: [0xd3,0x95,0xe6,0x20] +# CHECK-ASM-AND-OBJ: fsgnjn.s fa1, fa3, fa4 +# CHECK-ASM: encoding: [0xd3,0x95,0xe6,0x20] fsgnjn.s fa1, fa3, fa4 -# CHECK-INST: fsgnjx.s fa4, fa3, fa2 -# CHECK: encoding: [0x53,0xa7,0xc6,0x20] +# CHECK-ASM-AND-OBJ: fsgnjx.s fa4, fa3, fa2 +# CHECK-ASM: encoding: [0x53,0xa7,0xc6,0x20] fsgnjx.s fa4, fa3, fa2 -# CHECK-INST: fmin.s fa5, fa6, fa7 -# CHECK: encoding: [0xd3,0x07,0x18,0x29] +# CHECK-ASM-AND-OBJ: fmin.s fa5, fa6, fa7 +# CHECK-ASM: encoding: [0xd3,0x07,0x18,0x29] fmin.s fa5, fa6, fa7 -# CHECK-INST: fmax.s fs2, fs3, fs4 -# CHECK: encoding: [0x53,0x99,0x49,0x29] +# CHECK-ASM-AND-OBJ: fmax.s fs2, fs3, fs4 +# CHECK-ASM: encoding: [0x53,0x99,0x49,0x29] fmax.s fs2, fs3, fs4 -# CHECK-INST: fcvt.w.s a0, fs5, dyn -# CHECK: encoding: [0x53,0xf5,0x0a,0xc0] +# CHECK-ASM-AND-OBJ: fcvt.w.s a0, fs5, dyn +# CHECK-ASM: encoding: [0x53,0xf5,0x0a,0xc0] fcvt.w.s a0, fs5, dyn -# CHECK-INST: fcvt.wu.s a1, fs6, dyn -# CHECK: encoding: [0xd3,0x75,0x1b,0xc0] +# CHECK-ASM-AND-OBJ: fcvt.wu.s a1, fs6, dyn +# CHECK-ASM: encoding: [0xd3,0x75,0x1b,0xc0] fcvt.wu.s a1, fs6, dyn -# CHECK-INST: fmv.x.w a2, fs7 -# CHECK: encoding: [0x53,0x86,0x0b,0xe0] +# CHECK-ASM-AND-OBJ: fmv.x.w a2, fs7 +# CHECK-ASM: encoding: [0x53,0x86,0x0b,0xe0] fmv.x.w a2, fs7 -# CHECK-INST: feq.s a1, fs8, fs9 -# CHECK: encoding: [0xd3,0x25,0x9c,0xa1] +# CHECK-ASM-AND-OBJ: feq.s a1, fs8, fs9 +# CHECK-ASM: encoding: [0xd3,0x25,0x9c,0xa1] feq.s a1, fs8, fs9 -# CHECK-INST: flt.s a2, fs10, fs11 -# CHECK: encoding: [0x53,0x16,0xbd,0xa1] +# CHECK-ASM-AND-OBJ: flt.s a2, fs10, fs11 +# CHECK-ASM: encoding: [0x53,0x16,0xbd,0xa1] flt.s a2, fs10, fs11 -# CHECK-INST: fle.s a3, ft8, ft9 -# CHECK: encoding: [0xd3,0x06,0xde,0xa1] +# CHECK-ASM-AND-OBJ: fle.s a3, ft8, ft9 +# CHECK-ASM: encoding: [0xd3,0x06,0xde,0xa1] fle.s a3, ft8, ft9 -# CHECK-INST: fclass.s a3, ft10 -# CHECK: encoding: [0xd3,0x16,0x0f,0xe0] +# CHECK-ASM-AND-OBJ: fclass.s a3, ft10 +# CHECK-ASM: encoding: [0xd3,0x16,0x0f,0xe0] fclass.s a3, ft10 -# CHECK-INST: fcvt.s.w ft11, a4, dyn -# CHECK: encoding: [0xd3,0x7f,0x07,0xd0] +# CHECK-ASM-AND-OBJ: fcvt.s.w ft11, a4, dyn +# CHECK-ASM: encoding: [0xd3,0x7f,0x07,0xd0] fcvt.s.w ft11, a4, dyn -# CHECK-INST: fcvt.s.wu ft0, a5, dyn -# CHECK: encoding: [0x53,0xf0,0x17,0xd0] +# CHECK-ASM-AND-OBJ: fcvt.s.wu ft0, a5, dyn +# CHECK-ASM: encoding: [0x53,0xf0,0x17,0xd0] fcvt.s.wu ft0, a5, dyn -# CHECK-INST: fmv.w.x ft1, a6 -# CHECK: encoding: [0xd3,0x00,0x08,0xf0] +# CHECK-ASM-AND-OBJ: fmv.w.x ft1, a6 +# CHECK-ASM: encoding: [0xd3,0x00,0x08,0xf0] fmv.w.x ft1, a6 # Rounding modes -# CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, rne -# CHECK: encoding: [0x43,0x85,0xc5,0x68] +# CHECK-ASM-AND-OBJ: fmadd.s fa0, fa1, fa2, fa3, rne +# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x68] fmadd.s f10, f11, f12, f13, rne -# CHECK-INST: fmsub.s fa4, fa5, fa6, fa7, rtz -# CHECK: encoding: [0x47,0x97,0x07,0x89] +# CHECK-ASM-AND-OBJ: fmsub.s fa4, fa5, fa6, fa7, rtz +# CHECK-ASM: encoding: [0x47,0x97,0x07,0x89] fmsub.s f14, f15, f16, f17, rtz -# CHECK-INST: fnmsub.s fs2, fs3, fs4, fs5, rdn -# CHECK: encoding: [0x4b,0xa9,0x49,0xa9] +# CHECK-ASM-AND-OBJ: fnmsub.s fs2, fs3, fs4, fs5, rdn +# CHECK-ASM: encoding: [0x4b,0xa9,0x49,0xa9] fnmsub.s f18, f19, f20, f21, rdn -# CHECK-INST: fnmadd.s fs6, fs7, fs8, fs9, rup -# CHECK: encoding: [0x4f,0xbb,0x8b,0xc9] +# CHECK-ASM-AND-OBJ: fnmadd.s fs6, fs7, fs8, fs9, rup +# CHECK-ASM: encoding: [0x4f,0xbb,0x8b,0xc9] fnmadd.s f22, f23, f24, f25, rup -# CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, rmm -# CHECK: encoding: [0x43,0xc5,0xc5,0x68] +# CHECK-ASM-AND-OBJ: fmadd.s fa0, fa1, fa2, fa3, rmm +# CHECK-ASM: encoding: [0x43,0xc5,0xc5,0x68] fmadd.s f10, f11, f12, f13, rmm -# CHECK-INST: fmsub.s fa4, fa5, fa6, fa7 -# CHECK: encoding: [0x47,0xf7,0x07,0x89] +# CHECK-ASM-AND-OBJ: fmsub.s fa4, fa5, fa6, fa7 +# CHECK-ASM: encoding: [0x47,0xf7,0x07,0x89] fmsub.s f14, f15, f16, f17, dyn -# CHECK-INST: fadd.s fs10, fs11, ft8, rne -# CHECK: encoding: [0x53,0x8d,0xcd,0x01] +# CHECK-ASM-AND-OBJ: fadd.s fs10, fs11, ft8, rne +# CHECK-ASM: encoding: [0x53,0x8d,0xcd,0x01] fadd.s f26, f27, f28, rne -# CHECK-INST: fsub.s ft9, ft10, ft11, rtz -# CHECK: encoding: [0xd3,0x1e,0xff,0x09] +# CHECK-ASM-AND-OBJ: fsub.s ft9, ft10, ft11, rtz +# CHECK-ASM: encoding: [0xd3,0x1e,0xff,0x09] fsub.s f29, f30, f31, rtz -# CHECK-INST: fmul.s ft0, ft1, ft2, rdn -# CHECK: encoding: [0x53,0xa0,0x20,0x10] +# CHECK-ASM-AND-OBJ: fmul.s ft0, ft1, ft2, rdn +# CHECK-ASM: encoding: [0x53,0xa0,0x20,0x10] fmul.s ft0, ft1, ft2, rdn -# CHECK-INST: fdiv.s ft3, ft4, ft5, rup -# CHECK: encoding: [0xd3,0x31,0x52,0x18] +# CHECK-ASM-AND-OBJ: fdiv.s ft3, ft4, ft5, rup +# CHECK-ASM: encoding: [0xd3,0x31,0x52,0x18] fdiv.s ft3, ft4, ft5, rup -# CHECK-INST: fsqrt.s ft6, ft7, rmm -# CHECK: encoding: [0x53,0xc3,0x03,0x58] +# CHECK-ASM-AND-OBJ: fsqrt.s ft6, ft7, rmm +# CHECK-ASM: encoding: [0x53,0xc3,0x03,0x58] fsqrt.s ft6, ft7, rmm -# CHECK-INST: fcvt.w.s a0, fs5, rup -# CHECK: encoding: [0x53,0xb5,0x0a,0xc0] +# CHECK-ASM-AND-OBJ: fcvt.w.s a0, fs5, rup +# CHECK-ASM: encoding: [0x53,0xb5,0x0a,0xc0] fcvt.w.s a0, fs5, rup -# CHECK-INST: fcvt.wu.s a1, fs6, rdn -# CHECK: encoding: [0xd3,0x25,0x1b,0xc0] +# CHECK-ASM-AND-OBJ: fcvt.wu.s a1, fs6, rdn +# CHECK-ASM: encoding: [0xd3,0x25,0x1b,0xc0] fcvt.wu.s a1, fs6, rdn -# CHECK-INST: fcvt.s.w ft11, a4, rtz -# CHECK: encoding: [0xd3,0x1f,0x07,0xd0] +# CHECK-ASM-AND-OBJ: fcvt.s.w ft11, a4, rtz +# CHECK-ASM: encoding: [0xd3,0x1f,0x07,0xd0] fcvt.s.w ft11, a4, rtz -# CHECK-INST: fcvt.s.wu ft0, a5, rne -# CHECK: encoding: [0x53,0x80,0x17,0xd0] +# CHECK-ASM-AND-OBJ: fcvt.s.wu ft0, a5, rne +# CHECK-ASM: encoding: [0x53,0x80,0x17,0xd0] fcvt.s.wu ft0, a5, rne diff --git a/test/MC/RISCV/rv32fc-valid.s b/test/MC/RISCV/rv32fc-valid.s index 87d86c13799..3e29a5c9485 100644 --- a/test/MC/RISCV/rv32fc-valid.s +++ b/test/MC/RISCV/rv32fc-valid.s @@ -1,8 +1,9 @@ # RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+f -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c,+f < %s \ -# RUN: | llvm-objdump -mattr=+f -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: | llvm-objdump -mattr=+c,+f -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# # RUN: not llvm-mc -triple riscv32 -mattr=+c \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s @@ -13,21 +14,22 @@ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s +# FIXME: error messages for rv64fc are misleading -# CHECK-INST: c.flwsp fs0, 252(sp) -# CHECK: encoding: [0x7e,0x74] +# CHECK-ASM-AND-OBJ: c.flwsp fs0, 252(sp) +# CHECK-ASM: encoding: [0x7e,0x74] # CHECK-NO-EXT: error: instruction use requires an option to be enabled c.flwsp fs0, 252(sp) -# CHECK-INST: c.fswsp fa7, 252(sp) -# CHECK: encoding: [0xc6,0xff] +# CHECK-ASM-AND-OBJ: c.fswsp fa7, 252(sp) +# CHECK-ASM: encoding: [0xc6,0xff] # CHECK-NO-EXT: error: instruction use requires an option to be enabled c.fswsp fa7, 252(sp) -# CHECK-INST: c.flw fa3, 124(a5) -# CHECK: encoding: [0xf4,0x7f] +# CHECK-ASM-AND-OBJ: c.flw fa3, 124(a5) +# CHECK-ASM: encoding: [0xf4,0x7f] # CHECK-NO-EXT: error: instruction use requires an option to be enabled c.flw fa3, 124(a5) -# CHECK-INST: c.fsw fa2, 124(a1) -# CHECK: encoding: [0xf0,0xfd] +# CHECK-ASM-AND-OBJ: c.fsw fa2, 124(a1) +# CHECK-ASM: encoding: [0xf0,0xfd] # CHECK-NO-EXT: error: instruction use requires an option to be enabled c.fsw fa2, 124(a1) diff --git a/test/MC/RISCV/rv32i-valid.s b/test/MC/RISCV/rv32i-valid.s index 4491bd8b658..c446c881b45 100644 --- a/test/MC/RISCV/rv32i-valid.s +++ b/test/MC/RISCV/rv32i-valid.s @@ -1,243 +1,243 @@ # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ -# RUN: | llvm-objdump -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ -# RUN: | llvm-objdump -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple riscv64 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 < %s \ +# RUN: | llvm-objdump -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 < %s \ +# RUN: | llvm-objdump -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s -# CHECK-INST: lui a0, 2 -# CHECK: encoding: [0x37,0x25,0x00,0x00] +# CHECK-ASM-AND-OBJ: lui a0, 2 +# CHECK-ASM: encoding: [0x37,0x25,0x00,0x00] lui a0, 2 -# CHECK-INST: lui s11, 552960 -# CHECK: encoding: [0xb7,0x0d,0x00,0x87] +# CHECK-ASM-AND-OBJ: lui s11, 552960 +# CHECK-ASM: encoding: [0xb7,0x0d,0x00,0x87] lui s11, (0x87000000>>12) -# CHECK-INST: lui a0, 0 -# CHECK: encoding: [0x37,0x05,0x00,0x00] +# CHECK-ASM-AND-OBJ: lui a0, 0 +# CHECK-ASM: encoding: [0x37,0x05,0x00,0x00] lui a0, %hi(2) -# CHECK-INST: lui s11, 552960 -# CHECK: encoding: [0xb7,0x0d,0x00,0x87] +# CHECK-ASM-AND-OBJ: lui s11, 552960 +# CHECK-ASM: encoding: [0xb7,0x0d,0x00,0x87] lui s11, (0x87000000>>12) -# CHECK-INST: lui s11, 552960 -# CHECK: encoding: [0xb7,0x0d,0x00,0x87] +# CHECK-ASM-AND-OBJ: lui s11, 552960 +# CHECK-ASM: encoding: [0xb7,0x0d,0x00,0x87] lui s11, %hi(0x87000000) -# CHECK-INST: lui t0, 1048575 -# CHECK: encoding: [0xb7,0xf2,0xff,0xff] +# CHECK-ASM-AND-OBJ: lui t0, 1048575 +# CHECK-ASM: encoding: [0xb7,0xf2,0xff,0xff] lui t0, 1048575 -# CHECK-INST: lui gp, 0 -# CHECK: encoding: [0xb7,0x01,0x00,0x00] +# CHECK-ASM-AND-OBJ: lui gp, 0 +# CHECK-ASM: encoding: [0xb7,0x01,0x00,0x00] lui gp, 0 -# CHECK-INST: auipc a0, 2 -# CHECK: encoding: [0x17,0x25,0x00,0x00] +# CHECK-ASM-AND-OBJ: auipc a0, 2 +# CHECK-ASM: encoding: [0x17,0x25,0x00,0x00] auipc a0, 2 -# CHECK-INST: auipc s11, 552960 -# CHECK: encoding: [0x97,0x0d,0x00,0x87] +# CHECK-ASM-AND-OBJ: auipc s11, 552960 +# CHECK-ASM: encoding: [0x97,0x0d,0x00,0x87] auipc s11, (0x87000000>>12) -# CHECK-INST: auipc t0, 1048575 -# CHECK: encoding: [0x97,0xf2,0xff,0xff] +# CHECK-ASM-AND-OBJ: auipc t0, 1048575 +# CHECK-ASM: encoding: [0x97,0xf2,0xff,0xff] auipc t0, 1048575 -# CHECK-INST: auipc gp, 0 -# CHECK: encoding: [0x97,0x01,0x00,0x00] +# CHECK-ASM-AND-OBJ: auipc gp, 0 +# CHECK-ASM: encoding: [0x97,0x01,0x00,0x00] auipc gp, 0 -# CHECK-INST: jal a2, 1048574 -# CHECK: encoding: [0x6f,0xf6,0xff,0x7f] +# CHECK-ASM-AND-OBJ: jal a2, 1048574 +# CHECK-ASM: encoding: [0x6f,0xf6,0xff,0x7f] jal a2, 1048574 -# CHECK-INST: jal a3, 256 -# CHECK: encoding: [0xef,0x06,0x00,0x10] +# CHECK-ASM-AND-OBJ: jal a3, 256 +# CHECK-ASM: encoding: [0xef,0x06,0x00,0x10] jal a3, 256 -# CHECK-INST: jalr a0, a1, -2048 -# CHECK: encoding: [0x67,0x85,0x05,0x80] +# CHECK-ASM-AND-OBJ: jalr a0, a1, -2048 +# CHECK-ASM: encoding: [0x67,0x85,0x05,0x80] jalr a0, a1, -2048 -# CHECK-INST: jalr a0, a1, -2048 -# CHECK: encoding: [0x67,0x85,0x05,0x80] +# CHECK-ASM-AND-OBJ: jalr a0, a1, -2048 +# CHECK-ASM: encoding: [0x67,0x85,0x05,0x80] jalr a0, a1, %lo(2048) -# CHECK-INST: jalr t2, t1, 2047 -# CHECK: encoding: [0xe7,0x03,0xf3,0x7f] +# CHECK-ASM-AND-OBJ: jalr t2, t1, 2047 +# CHECK-ASM: encoding: [0xe7,0x03,0xf3,0x7f] jalr t2, t1, 2047 -# CHECK-INST: jalr sp, zero, 256 -# CHECK: encoding: [0x67,0x01,0x00,0x10] +# CHECK-ASM-AND-OBJ: jalr sp, zero, 256 +# CHECK-ASM: encoding: [0x67,0x01,0x00,0x10] jalr sp, zero, 256 -# CHECK-INST: beq s1, s1, 102 -# CHECK: encoding: [0x63,0x83,0x94,0x06] +# CHECK-ASM-AND-OBJ: beq s1, s1, 102 +# CHECK-ASM: encoding: [0x63,0x83,0x94,0x06] beq s1, s1, 102 -# CHECK-INST: bne a4, a5, -4096 -# CHECK: encoding: [0x63,0x10,0xf7,0x80] +# CHECK-ASM-AND-OBJ: bne a4, a5, -4096 +# CHECK-ASM: encoding: [0x63,0x10,0xf7,0x80] bne a4, a5, -4096 -# CHECK-INST: blt sp, gp, 4094 -# CHECK: encoding: [0xe3,0x4f,0x31,0x7e] +# CHECK-ASM-AND-OBJ: blt sp, gp, 4094 +# CHECK-ASM: encoding: [0xe3,0x4f,0x31,0x7e] blt sp, gp, 4094 -# CHECK-INST: bge s2, ra, -224 -# CHECK: encoding: [0xe3,0x50,0x19,0xf2] +# CHECK-ASM-AND-OBJ: bge s2, ra, -224 +# CHECK-ASM: encoding: [0xe3,0x50,0x19,0xf2] bge s2, ra, -224 -# CHECK-INST: bltu zero, zero, 0 -# CHECK: encoding: [0x63,0x60,0x00,0x00] +# CHECK-ASM-AND-OBJ: bltu zero, zero, 0 +# CHECK-ASM: encoding: [0x63,0x60,0x00,0x00] bltu zero, zero, 0 -# CHECK-INST: bgeu s8, sp, 512 -# CHECK: encoding: [0x63,0x70,0x2c,0x20] +# CHECK-ASM-AND-OBJ: bgeu s8, sp, 512 +# CHECK-ASM: encoding: [0x63,0x70,0x2c,0x20] bgeu s8, sp, 512 -# CHECK-INST: lb s3, 4(ra) -# CHECK: encoding: [0x83,0x89,0x40,0x00] +# CHECK-ASM-AND-OBJ: lb s3, 4(ra) +# CHECK-ASM: encoding: [0x83,0x89,0x40,0x00] lb s3, 4(ra) -# CHECK-INST: lb s3, 4(ra) -# CHECK: encoding: [0x83,0x89,0x40,0x00] +# CHECK-ASM-AND-OBJ: lb s3, 4(ra) +# CHECK-ASM: encoding: [0x83,0x89,0x40,0x00] lb s3, +4(ra) -# CHECK-INST: lh t1, -2048(zero) -# CHECK: encoding: [0x03,0x13,0x00,0x80] +# CHECK-ASM-AND-OBJ: lh t1, -2048(zero) +# CHECK-ASM: encoding: [0x03,0x13,0x00,0x80] lh t1, -2048(zero) -# CHECK-INST: lh t1, -2048(zero) -# CHECK: encoding: [0x03,0x13,0x00,0x80] +# CHECK-ASM-AND-OBJ: lh t1, -2048(zero) +# CHECK-ASM: encoding: [0x03,0x13,0x00,0x80] lh t1, %lo(2048)(zero) -# CHECK-INST: lh sp, 2047(a0) -# CHECK: encoding: [0x03,0x11,0xf5,0x7f] +# CHECK-ASM-AND-OBJ: lh sp, 2047(a0) +# CHECK-ASM: encoding: [0x03,0x11,0xf5,0x7f] lh sp, 2047(a0) -# CHECK-INST: lw a0, 97(a2) -# CHECK: encoding: [0x03,0x25,0x16,0x06] +# CHECK-ASM-AND-OBJ: lw a0, 97(a2) +# CHECK-ASM: encoding: [0x03,0x25,0x16,0x06] lw a0, 97(a2) -# CHECK-INST: lbu s5, 0(s6) -# CHECK: encoding: [0x83,0x4a,0x0b,0x00] +# CHECK-ASM-AND-OBJ: lbu s5, 0(s6) +# CHECK-ASM: encoding: [0x83,0x4a,0x0b,0x00] lbu s5, 0(s6) -# CHECK-INST: lhu t3, 255(t3) -# CHECK: encoding: [0x03,0x5e,0xfe,0x0f] +# CHECK-ASM-AND-OBJ: lhu t3, 255(t3) +# CHECK-ASM: encoding: [0x03,0x5e,0xfe,0x0f] lhu t3, 255(t3) -# CHECK-INST: sb a0, 2047(a2) -# CHECK: encoding: [0xa3,0x0f,0xa6,0x7e] +# CHECK-ASM-AND-OBJ: sb a0, 2047(a2) +# CHECK-ASM: encoding: [0xa3,0x0f,0xa6,0x7e] sb a0, 2047(a2) -# CHECK-INST: sh t3, -2048(t5) -# CHECK: encoding: [0x23,0x10,0xcf,0x81] +# CHECK-ASM-AND-OBJ: sh t3, -2048(t5) +# CHECK-ASM: encoding: [0x23,0x10,0xcf,0x81] sh t3, -2048(t5) -# CHECK-INST: sh t3, -2048(t5) -# CHECK: encoding: [0x23,0x10,0xcf,0x81] +# CHECK-ASM-AND-OBJ: sh t3, -2048(t5) +# CHECK-ASM: encoding: [0x23,0x10,0xcf,0x81] sh t3, %lo(2048)(t5) -# CHECK-INST: sw ra, 999(zero) -# CHECK: encoding: [0xa3,0x23,0x10,0x3e] +# CHECK-ASM-AND-OBJ: sw ra, 999(zero) +# CHECK-ASM: encoding: [0xa3,0x23,0x10,0x3e] sw ra, 999(zero) -# CHECK-INST: addi ra, sp, 2 -# CHECK: encoding: [0x93,0x00,0x21,0x00] +# CHECK-ASM-AND-OBJ: addi ra, sp, 2 +# CHECK-ASM: encoding: [0x93,0x00,0x21,0x00] addi ra, sp, 2 -# CHECK-INST: slti a0, a2, -20 -# CHECK: encoding: [0x13,0x25,0xc6,0xfe] +# CHECK-ASM-AND-OBJ: slti a0, a2, -20 +# CHECK-ASM: encoding: [0x13,0x25,0xc6,0xfe] slti a0, a2, -20 -# CHECK-INST: sltiu s2, s3, 80 -# CHECK: encoding: [0x13,0xb9,0x09,0x05] +# CHECK-ASM-AND-OBJ: sltiu s2, s3, 80 +# CHECK-ASM: encoding: [0x13,0xb9,0x09,0x05] sltiu s2, s3, 0x50 -# CHECK-INST: xori tp, t1, -99 -# CHECK: encoding: [0x13,0x42,0xd3,0xf9] +# CHECK-ASM-AND-OBJ: xori tp, t1, -99 +# CHECK-ASM: encoding: [0x13,0x42,0xd3,0xf9] xori tp, t1, -99 -# CHECK-INST: ori a0, a1, -2048 -# CHECK: encoding: [0x13,0xe5,0x05,0x80] +# CHECK-ASM-AND-OBJ: ori a0, a1, -2048 +# CHECK-ASM: encoding: [0x13,0xe5,0x05,0x80] ori a0, a1, -2048 -# CHECK-INST: ori a0, a1, -2048 -# CHECK: encoding: [0x13,0xe5,0x05,0x80] +# CHECK-ASM-AND-OBJ: ori a0, a1, -2048 +# CHECK-ASM: encoding: [0x13,0xe5,0x05,0x80] ori a0, a1, %lo(2048) -# CHECK-INST: andi ra, sp, 2047 -# CHECK: encoding: [0x93,0x70,0xf1,0x7f] +# CHECK-ASM-AND-OBJ: andi ra, sp, 2047 +# CHECK-ASM: encoding: [0x93,0x70,0xf1,0x7f] andi ra, sp, 2047 -# CHECK-INST: andi ra, sp, 2047 -# CHECK: encoding: [0x93,0x70,0xf1,0x7f] +# CHECK-ASM-AND-OBJ: andi ra, sp, 2047 +# CHECK-ASM: encoding: [0x93,0x70,0xf1,0x7f] andi x1, x2, 2047 -# CHECK-INST: slli t3, t3, 31 -# CHECK: encoding: [0x13,0x1e,0xfe,0x01] +# CHECK-ASM-AND-OBJ: slli t3, t3, 31 +# CHECK-ASM: encoding: [0x13,0x1e,0xfe,0x01] slli t3, t3, 31 -# CHECK-INST: srli a0, a4, 0 -# CHECK: encoding: [0x13,0x55,0x07,0x00] +# CHECK-ASM-AND-OBJ: srli a0, a4, 0 +# CHECK-ASM: encoding: [0x13,0x55,0x07,0x00] srli a0, a4, 0 -# CHECK-INST: srai a2, sp, 15 -# CHECK: encoding: [0x13,0x56,0xf1,0x40] +# CHECK-ASM-AND-OBJ: srai a2, sp, 15 +# CHECK-ASM: encoding: [0x13,0x56,0xf1,0x40] srai a2, sp, 15 -# CHECK-INST: add ra, zero, zero -# CHECK: encoding: [0xb3,0x00,0x00,0x00] +# CHECK-ASM-AND-OBJ: add ra, zero, zero +# CHECK-ASM: encoding: [0xb3,0x00,0x00,0x00] add ra, zero, zero -# CHECK-INST: add ra, zero, zero -# CHECK: encoding: [0xb3,0x00,0x00,0x00] +# CHECK-ASM-AND-OBJ: add ra, zero, zero +# CHECK-ASM: encoding: [0xb3,0x00,0x00,0x00] add x1, x0, x0 -# CHECK-INST: sub t0, t2, t1 -# CHECK: encoding: [0xb3,0x82,0x63,0x40] +# CHECK-ASM-AND-OBJ: sub t0, t2, t1 +# CHECK-ASM: encoding: [0xb3,0x82,0x63,0x40] sub t0, t2, t1 -# CHECK-INST: sll a5, a4, a3 -# CHECK: encoding: [0xb3,0x17,0xd7,0x00] +# CHECK-ASM-AND-OBJ: sll a5, a4, a3 +# CHECK-ASM: encoding: [0xb3,0x17,0xd7,0x00] sll a5, a4, a3 -# CHECK-INST: slt s0, s0, s0 -# CHECK: encoding: [0x33,0x24,0x84,0x00] +# CHECK-ASM-AND-OBJ: slt s0, s0, s0 +# CHECK-ASM: encoding: [0x33,0x24,0x84,0x00] slt s0, s0, s0 -# CHECK-INST: sltu gp, a0, a1 -# CHECK: encoding: [0xb3,0x31,0xb5,0x00] +# CHECK-ASM-AND-OBJ: sltu gp, a0, a1 +# CHECK-ASM: encoding: [0xb3,0x31,0xb5,0x00] sltu gp, a0, a1 -# CHECK-INST: xor s2, s2, s8 -# CHECK: encoding: [0x33,0x49,0x89,0x01] +# CHECK-ASM-AND-OBJ: xor s2, s2, s8 +# CHECK-ASM: encoding: [0x33,0x49,0x89,0x01] xor s2, s2, s8 -# CHECK-INST: xor s2, s2, s8 -# CHECK: encoding: [0x33,0x49,0x89,0x01] +# CHECK-ASM-AND-OBJ: xor s2, s2, s8 +# CHECK-ASM: encoding: [0x33,0x49,0x89,0x01] xor x18, x18, x24 -# CHECK-INST: srl a0, s0, t0 -# CHECK: encoding: [0x33,0x55,0x54,0x00] +# CHECK-ASM-AND-OBJ: srl a0, s0, t0 +# CHECK-ASM: encoding: [0x33,0x55,0x54,0x00] srl a0, s0, t0 -# CHECK-INST: sra t0, s2, zero -# CHECK: encoding: [0xb3,0x52,0x09,0x40] +# CHECK-ASM-AND-OBJ: sra t0, s2, zero +# CHECK-ASM: encoding: [0xb3,0x52,0x09,0x40] sra t0, s2, zero -# CHECK-INST: or s10, t1, ra -# CHECK: encoding: [0x33,0x6d,0x13,0x00] +# CHECK-ASM-AND-OBJ: or s10, t1, ra +# CHECK-ASM: encoding: [0x33,0x6d,0x13,0x00] or s10, t1, ra -# CHECK-INST: and a0, s2, s3 -# CHECK: encoding: [0x33,0x75,0x39,0x01] +# CHECK-ASM-AND-OBJ: and a0, s2, s3 +# CHECK-ASM: encoding: [0x33,0x75,0x39,0x01] and a0, s2, s3 -# CHECK-INST: fence iorw, iorw -# CHECK: encoding: [0x0f,0x00,0xf0,0x0f] +# CHECK-ASM-AND-OBJ: fence iorw, iorw +# CHECK-ASM: encoding: [0x0f,0x00,0xf0,0x0f] fence iorw, iorw -# CHECK-INST: fence io, rw -# CHECK: encoding: [0x0f,0x00,0x30,0x0c] +# CHECK-ASM-AND-OBJ: fence io, rw +# CHECK-ASM: encoding: [0x0f,0x00,0x30,0x0c] fence io, rw -# CHECK-INST: fence r, w -# CHECK: encoding: [0x0f,0x00,0x10,0x02] +# CHECK-ASM-AND-OBJ: fence r, w +# CHECK-ASM: encoding: [0x0f,0x00,0x10,0x02] fence r,w -# CHECK-INST: fence w, ir -# CHECK: encoding: [0x0f,0x00,0xa0,0x01] +# CHECK-ASM-AND-OBJ: fence w, ir +# CHECK-ASM: encoding: [0x0f,0x00,0xa0,0x01] fence w,ir -# CHECK-INST: fence.tso -# CHECK: encoding: [0x0f,0x00,0x30,0x83] +# CHECK-ASM-AND-OBJ: fence.tso +# CHECK-ASM: encoding: [0x0f,0x00,0x30,0x83] fence.tso -# CHECK-INST: fence.i -# CHECK: encoding: [0x0f,0x10,0x00,0x00] +# CHECK-ASM-AND-OBJ: fence.i +# CHECK-ASM: encoding: [0x0f,0x10,0x00,0x00] fence.i -# CHECK-INST: ecall -# CHECK: encoding: [0x73,0x00,0x00,0x00] +# CHECK-ASM-AND-OBJ: ecall +# CHECK-ASM: encoding: [0x73,0x00,0x00,0x00] ecall -# CHECK-INST: ebreak -# CHECK: encoding: [0x73,0x00,0x10,0x00] +# CHECK-ASM-AND-OBJ: ebreak +# CHECK-ASM: encoding: [0x73,0x00,0x10,0x00] ebreak -# CHECK-INST: csrrw t0, 4095, t1 -# CHECK: encoding: [0xf3,0x12,0xf3,0xff] +# CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1 +# CHECK-ASM: encoding: [0xf3,0x12,0xf3,0xff] csrrw t0, 0xfff, t1 -# CHECK-INST: csrrs s0, 3072, zero -# CHECK: encoding: [0x73,0x24,0x00,0xc0] +# CHECK-ASM-AND-OBJ: csrrs s0, 3072, zero +# CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0] csrrs s0, 0xc00, x0 -# CHECK-INST: csrrs s3, 1, s5 -# CHECK: encoding: [0xf3,0xa9,0x1a,0x00] +# CHECK-ASM-AND-OBJ: csrrs s3, 1, s5 +# CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00] csrrs s3, 0x001, s5 -# CHECK-INST: csrrc sp, 0, ra -# CHECK: encoding: [0x73,0xb1,0x00,0x00] +# CHECK-ASM-AND-OBJ: csrrc sp, 0, ra +# CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00] csrrc sp, 0x000, ra -# CHECK-INST: csrrwi a5, 0, 0 -# CHECK: encoding: [0xf3,0x57,0x00,0x00] +# CHECK-ASM-AND-OBJ: csrrwi a5, 0, 0 +# CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00] csrrwi a5, 0x000, 0 -# CHECK-INST: csrrsi t2, 4095, 31 -# CHECK: encoding: [0xf3,0xe3,0xff,0xff] +# CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31 +# CHECK-ASM: encoding: [0xf3,0xe3,0xff,0xff] csrrsi t2, 0xfff, 31 -# CHECK-INST: csrrci t1, 320, 5 -# CHECK: encoding: [0x73,0xf3,0x02,0x14] +# CHECK-ASM-AND-OBJ: csrrci t1, 320, 5 +# CHECK-ASM: encoding: [0x73,0xf3,0x02,0x14] csrrci t1, 0x140, 5 diff --git a/test/MC/RISCV/rv32m-valid.s b/test/MC/RISCV/rv32m-valid.s index 385c4d86cd3..2b410f2c80c 100644 --- a/test/MC/RISCV/rv32m-valid.s +++ b/test/MC/RISCV/rv32m-valid.s @@ -1,35 +1,35 @@ # RUN: llvm-mc %s -triple=riscv32 -mattr=+m -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc %s -triple=riscv64 -mattr=+m -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+m < %s \ -# RUN: | llvm-objdump -mattr=+m -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+m < %s \ -# RUN: | llvm-objdump -mattr=+m -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+m < %s \ +# RUN: | llvm-objdump -mattr=+m -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+m < %s \ +# RUN: | llvm-objdump -mattr=+m -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s -# CHECK-INST: mul a4, ra, s0 -# CHECK: encoding: [0x33,0x87,0x80,0x02] +# CHECK-ASM-AND-OBJ: mul a4, ra, s0 +# CHECK-ASM: encoding: [0x33,0x87,0x80,0x02] mul a4, ra, s0 -# CHECK-INST: mulh ra, zero, zero -# CHECK: encoding: [0xb3,0x10,0x00,0x02] +# CHECK-ASM-AND-OBJ: mulh ra, zero, zero +# CHECK-ASM: encoding: [0xb3,0x10,0x00,0x02] mulh x1, x0, x0 -# CHECK-INST: mulhsu t0, t2, t1 -# CHECK: encoding: [0xb3,0xa2,0x63,0x02] +# CHECK-ASM-AND-OBJ: mulhsu t0, t2, t1 +# CHECK-ASM: encoding: [0xb3,0xa2,0x63,0x02] mulhsu t0, t2, t1 -# CHECK-INST: mulhu a5, a4, a3 -# CHECK: encoding: [0xb3,0x37,0xd7,0x02] +# CHECK-ASM-AND-OBJ: mulhu a5, a4, a3 +# CHECK-ASM: encoding: [0xb3,0x37,0xd7,0x02] mulhu a5, a4, a3 -# CHECK-INST: div s0, s0, s0 -# CHECK: encoding: [0x33,0x44,0x84,0x02] +# CHECK-ASM-AND-OBJ: div s0, s0, s0 +# CHECK-ASM: encoding: [0x33,0x44,0x84,0x02] div s0, s0, s0 -# CHECK-INST: divu gp, a0, a1 -# CHECK: encoding: [0xb3,0x51,0xb5,0x02] +# CHECK-ASM-AND-OBJ: divu gp, a0, a1 +# CHECK-ASM: encoding: [0xb3,0x51,0xb5,0x02] divu gp, a0, a1 -# CHECK-INST: rem s2, s2, s8 -# CHECK: encoding: [0x33,0x69,0x89,0x03] +# CHECK-ASM-AND-OBJ: rem s2, s2, s8 +# CHECK-ASM: encoding: [0x33,0x69,0x89,0x03] rem s2, s2, s8 -# CHECK-INST: remu s2, s2, s8 -# CHECK: encoding: [0x33,0x79,0x89,0x03] +# CHECK-ASM-AND-OBJ: remu s2, s2, s8 +# CHECK-ASM: encoding: [0x33,0x79,0x89,0x03] remu x18, x18, x24 diff --git a/test/MC/RISCV/rv64a-valid.s b/test/MC/RISCV/rv64a-valid.s index 3203d6e6d3f..2112727a8f2 100644 --- a/test/MC/RISCV/rv64a-valid.s +++ b/test/MC/RISCV/rv64a-valid.s @@ -1,190 +1,193 @@ # RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+a < %s \ -# RUN: | llvm-objdump -mattr=+a -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \ +# RUN: | llvm-objdump -mattr=+a -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# # RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \ # RUN: | FileCheck -check-prefix=CHECK-RV32 %s -# CHECK-INST: lr.d t0, (t1) -# CHECK: encoding: [0xaf,0x32,0x03,0x10] +# FIXME: error messages for rv32a are misleading + +# CHECK-ASM-AND-OBJ: lr.d t0, (t1) +# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled lr.d t0, (t1) -# CHECK-INST: lr.d.aq t1, (t2) -# CHECK: encoding: [0x2f,0xb3,0x03,0x14] +# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2) +# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled lr.d.aq t1, (t2) -# CHECK-INST: lr.d.rl t2, (t3) -# CHECK: encoding: [0xaf,0x33,0x0e,0x12] +# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3) +# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled lr.d.rl t2, (t3) -# CHECK-INST: lr.d.aqrl t3, (t4) -# CHECK: encoding: [0x2f,0xbe,0x0e,0x16] +# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4) +# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled lr.d.aqrl t3, (t4) -# CHECK-INST: sc.d t6, t5, (t4) -# CHECK: encoding: [0xaf,0xbf,0xee,0x19] +# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4) +# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled sc.d t6, t5, (t4) -# CHECK-INST: sc.d.aq t5, t4, (t3) -# CHECK: encoding: [0x2f,0x3f,0xde,0x1d] +# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3) +# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled sc.d.aq t5, t4, (t3) -# CHECK-INST: sc.d.rl t4, t3, (t2) -# CHECK: encoding: [0xaf,0xbe,0xc3,0x1b] +# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2) +# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled sc.d.rl t4, t3, (t2) -# CHECK-INST: sc.d.aqrl t3, t2, (t1) -# CHECK: encoding: [0x2f,0x3e,0x73,0x1e] +# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1) +# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled sc.d.aqrl t3, t2, (t1) -# CHECK-INST: amoswap.d a4, ra, (s0) -# CHECK: encoding: [0x2f,0x37,0x14,0x08] +# CHECK-ASM-AND-OBJ: amoswap.d a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoswap.d a4, ra, (s0) -# CHECK-INST: amoadd.d a1, a2, (a3) -# CHECK: encoding: [0xaf,0xb5,0xc6,0x00] +# CHECK-ASM-AND-OBJ: amoadd.d a1, a2, (a3) +# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x00] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoadd.d a1, a2, (a3) -# CHECK-INST: amoxor.d a2, a3, (a4) -# CHECK: encoding: [0x2f,0x36,0xd7,0x20] +# CHECK-ASM-AND-OBJ: amoxor.d a2, a3, (a4) +# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x20] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoxor.d a2, a3, (a4) -# CHECK-INST: amoand.d a3, a4, (a5) -# CHECK: encoding: [0xaf,0xb6,0xe7,0x60] +# CHECK-ASM-AND-OBJ: amoand.d a3, a4, (a5) +# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x60] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoand.d a3, a4, (a5) -# CHECK-INST: amoor.d a4, a5, (a6) -# CHECK: encoding: [0x2f,0x37,0xf8,0x40] +# CHECK-ASM-AND-OBJ: amoor.d a4, a5, (a6) +# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x40] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoor.d a4, a5, (a6) -# CHECK-INST: amomin.d a5, a6, (a7) -# CHECK: encoding: [0xaf,0xb7,0x08,0x81] +# CHECK-ASM-AND-OBJ: amomin.d a5, a6, (a7) +# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x81] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amomin.d a5, a6, (a7) -# CHECK-INST: amomax.d s7, s6, (s5) -# CHECK: encoding: [0xaf,0xbb,0x6a,0xa1] +# CHECK-ASM-AND-OBJ: amomax.d s7, s6, (s5) +# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa1] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amomax.d s7, s6, (s5) -# CHECK-INST: amominu.d s6, s5, (s4) -# CHECK: encoding: [0x2f,0x3b,0x5a,0xc1] +# CHECK-ASM-AND-OBJ: amominu.d s6, s5, (s4) +# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc1] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amominu.d s6, s5, (s4) -# CHECK-INST: amomaxu.d s5, s4, (s3) -# CHECK: encoding: [0xaf,0xba,0x49,0xe1] +# CHECK-ASM-AND-OBJ: amomaxu.d s5, s4, (s3) +# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe1] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amomaxu.d s5, s4, (s3) -# CHECK-INST: amoswap.d.aq a4, ra, (s0) -# CHECK: encoding: [0x2f,0x37,0x14,0x0c] +# CHECK-ASM-AND-OBJ: amoswap.d.aq a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0c] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoswap.d.aq a4, ra, (s0) -# CHECK-INST: amoadd.d.aq a1, a2, (a3) -# CHECK: encoding: [0xaf,0xb5,0xc6,0x04] +# CHECK-ASM-AND-OBJ: amoadd.d.aq a1, a2, (a3) +# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x04] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoadd.d.aq a1, a2, (a3) -# CHECK-INST: amoxor.d.aq a2, a3, (a4) -# CHECK: encoding: [0x2f,0x36,0xd7,0x24] +# CHECK-ASM-AND-OBJ: amoxor.d.aq a2, a3, (a4) +# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x24] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoxor.d.aq a2, a3, (a4) -# CHECK-INST: amoand.d.aq a3, a4, (a5) -# CHECK: encoding: [0xaf,0xb6,0xe7,0x64] +# CHECK-ASM-AND-OBJ: amoand.d.aq a3, a4, (a5) +# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x64] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoand.d.aq a3, a4, (a5) -# CHECK-INST: amoor.d.aq a4, a5, (a6) -# CHECK: encoding: [0x2f,0x37,0xf8,0x44] +# CHECK-ASM-AND-OBJ: amoor.d.aq a4, a5, (a6) +# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x44] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoor.d.aq a4, a5, (a6) -# CHECK-INST: amomin.d.aq a5, a6, (a7) -# CHECK: encoding: [0xaf,0xb7,0x08,0x85] +# CHECK-ASM-AND-OBJ: amomin.d.aq a5, a6, (a7) +# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x85] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amomin.d.aq a5, a6, (a7) -# CHECK-INST: amomax.d.aq s7, s6, (s5) -# CHECK: encoding: [0xaf,0xbb,0x6a,0xa5] +# CHECK-ASM-AND-OBJ: amomax.d.aq s7, s6, (s5) +# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa5] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amomax.d.aq s7, s6, (s5) -# CHECK-INST: amominu.d.aq s6, s5, (s4) -# CHECK: encoding: [0x2f,0x3b,0x5a,0xc5] +# CHECK-ASM-AND-OBJ: amominu.d.aq s6, s5, (s4) +# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc5] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amominu.d.aq s6, s5, (s4) -# CHECK-INST: amomaxu.d.aq s5, s4, (s3) -# CHECK: encoding: [0xaf,0xba,0x49,0xe5] +# CHECK-ASM-AND-OBJ: amomaxu.d.aq s5, s4, (s3) +# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe5] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amomaxu.d.aq s5, s4, (s3) -# CHECK-INST: amoswap.d.rl a4, ra, (s0) -# CHECK: encoding: [0x2f,0x37,0x14,0x0a] +# CHECK-ASM-AND-OBJ: amoswap.d.rl a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0a] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoswap.d.rl a4, ra, (s0) -# CHECK-INST: amoadd.d.rl a1, a2, (a3) -# CHECK: encoding: [0xaf,0xb5,0xc6,0x02] +# CHECK-ASM-AND-OBJ: amoadd.d.rl a1, a2, (a3) +# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x02] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoadd.d.rl a1, a2, (a3) -# CHECK-INST: amoxor.d.rl a2, a3, (a4) -# CHECK: encoding: [0x2f,0x36,0xd7,0x22] +# CHECK-ASM-AND-OBJ: amoxor.d.rl a2, a3, (a4) +# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x22] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoxor.d.rl a2, a3, (a4) -# CHECK-INST: amoand.d.rl a3, a4, (a5) -# CHECK: encoding: [0xaf,0xb6,0xe7,0x62] +# CHECK-ASM-AND-OBJ: amoand.d.rl a3, a4, (a5) +# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x62] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoand.d.rl a3, a4, (a5) -# CHECK-INST: amoor.d.rl a4, a5, (a6) -# CHECK: encoding: [0x2f,0x37,0xf8,0x42] +# CHECK-ASM-AND-OBJ: amoor.d.rl a4, a5, (a6) +# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x42] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoor.d.rl a4, a5, (a6) -# CHECK-INST: amomin.d.rl a5, a6, (a7) -# CHECK: encoding: [0xaf,0xb7,0x08,0x83] +# CHECK-ASM-AND-OBJ: amomin.d.rl a5, a6, (a7) +# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x83] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amomin.d.rl a5, a6, (a7) -# CHECK-INST: amomax.d.rl s7, s6, (s5) -# CHECK: encoding: [0xaf,0xbb,0x6a,0xa3] +# CHECK-ASM-AND-OBJ: amomax.d.rl s7, s6, (s5) +# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa3] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amomax.d.rl s7, s6, (s5) -# CHECK-INST: amominu.d.rl s6, s5, (s4) -# CHECK: encoding: [0x2f,0x3b,0x5a,0xc3] +# CHECK-ASM-AND-OBJ: amominu.d.rl s6, s5, (s4) +# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc3] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amominu.d.rl s6, s5, (s4) -# CHECK-INST: amomaxu.d.rl s5, s4, (s3) -# CHECK: encoding: [0xaf,0xba,0x49,0xe3] +# CHECK-ASM-AND-OBJ: amomaxu.d.rl s5, s4, (s3) +# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe3] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amomaxu.d.rl s5, s4, (s3) -# CHECK-INST: amoswap.d.aqrl a4, ra, (s0) -# CHECK: encoding: [0x2f,0x37,0x14,0x0e] +# CHECK-ASM-AND-OBJ: amoswap.d.aqrl a4, ra, (s0) +# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0e] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoswap.d.aqrl a4, ra, (s0) -# CHECK-INST: amoadd.d.aqrl a1, a2, (a3) -# CHECK: encoding: [0xaf,0xb5,0xc6,0x06] +# CHECK-ASM-AND-OBJ: amoadd.d.aqrl a1, a2, (a3) +# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x06] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoadd.d.aqrl a1, a2, (a3) -# CHECK-INST: amoxor.d.aqrl a2, a3, (a4) -# CHECK: encoding: [0x2f,0x36,0xd7,0x26] +# CHECK-ASM-AND-OBJ: amoxor.d.aqrl a2, a3, (a4) +# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x26] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoxor.d.aqrl a2, a3, (a4) -# CHECK-INST: amoand.d.aqrl a3, a4, (a5) -# CHECK: encoding: [0xaf,0xb6,0xe7,0x66] +# CHECK-ASM-AND-OBJ: amoand.d.aqrl a3, a4, (a5) +# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x66] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoand.d.aqrl a3, a4, (a5) -# CHECK-INST: amoor.d.aqrl a4, a5, (a6) -# CHECK: encoding: [0x2f,0x37,0xf8,0x46] +# CHECK-ASM-AND-OBJ: amoor.d.aqrl a4, a5, (a6) +# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x46] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amoor.d.aqrl a4, a5, (a6) -# CHECK-INST: amomin.d.aqrl a5, a6, (a7) -# CHECK: encoding: [0xaf,0xb7,0x08,0x87] +# CHECK-ASM-AND-OBJ: amomin.d.aqrl a5, a6, (a7) +# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x87] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amomin.d.aqrl a5, a6, (a7) -# CHECK-INST: amomax.d.aqrl s7, s6, (s5) -# CHECK: encoding: [0xaf,0xbb,0x6a,0xa7] +# CHECK-ASM-AND-OBJ: amomax.d.aqrl s7, s6, (s5) +# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa7] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amomax.d.aqrl s7, s6, (s5) -# CHECK-INST: amominu.d.aqrl s6, s5, (s4) -# CHECK: encoding: [0x2f,0x3b,0x5a,0xc7] +# CHECK-ASM-AND-OBJ: amominu.d.aqrl s6, s5, (s4) +# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc7] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amominu.d.aqrl s6, s5, (s4) -# CHECK-INST: amomaxu.d.aqrl s5, s4, (s3) -# CHECK: encoding: [0xaf,0xba,0x49,0xe7] +# CHECK-ASM-AND-OBJ: amomaxu.d.aqrl s5, s4, (s3) +# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe7] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled amomaxu.d.aqrl s5, s4, (s3) diff --git a/test/MC/RISCV/rv64c-valid.s b/test/MC/RISCV/rv64c-valid.s index c436fe5414c..959aaf34fa5 100644 --- a/test/MC/RISCV/rv64c-valid.s +++ b/test/MC/RISCV/rv64c-valid.s @@ -1,58 +1,62 @@ -# RUN: llvm-mc -triple=riscv64 -mattr=+c -riscv-no-aliases -show-encoding < %s \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c < %s \ -# RUN: | llvm-objdump -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+c -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \ +# RUN: | llvm-objdump -mattr=+c -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# +# # RUN: not llvm-mc -triple riscv64 \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s -# RUN: not llvm-mc -triple riscv32 -mattr=+c\ +# RUN: not llvm-mc -triple riscv32 -mattr=+c \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s +# FIXME: error messages for rv32c are misleading + # TODO: more exhaustive testing of immediate encoding. -# CHECK-INST: c.ldsp ra, 0(sp) -# CHECK: encoding: [0x82,0x60] +# CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp) +# CHECK-ASM: encoding: [0x82,0x60] # CHECK-NO-EXT: error: instruction use requires an option to be enabled -c.ldsp ra, 0(sp) -# CHECK-INST: c.sdsp ra, 504(sp) -# CHECK: encoding: [0x86,0xff] +c.ldsp ra, 0(sp) +# CHECK-ASM-AND-OBJ: c.sdsp ra, 504(sp) +# CHECK-ASM: encoding: [0x86,0xff] # CHECK-NO-EXT: error: instruction use requires an option to be enabled -c.sdsp ra, 504(sp) -# CHECK-INST: c.ld a4, 0(a3) -# CHECK: encoding: [0x98,0x62] +c.sdsp ra, 504(sp) +# CHECK-ASM-AND-OBJ: c.ld a4, 0(a3) +# CHECK-ASM: encoding: [0x98,0x62] # CHECK-NO-EXT: error: instruction use requires an option to be enabled -c.ld a4, 0(a3) -# CHECK-INST: c.sd a5, 248(a3) -# CHECK: encoding: [0xfc,0xfe] +c.ld a4, 0(a3) +# CHECK-ASM-AND-OBJ: c.sd a5, 248(a3) +# CHECK-ASM: encoding: [0xfc,0xfe] # CHECK-NO-EXT: error: instruction use requires an option to be enabled -c.sd a5, 248(a3) +c.sd a5, 248(a3) -# CHECK-INST: c.subw a3, a4 -# CHECK: encoding: [0x99,0x9e] -c.subw a3, a4 -# CHECK-INST: c.addw a0, a2 -# CHECK: encoding: [0x31,0x9d] +# CHECK-ASM-AND-OBJ: c.subw a3, a4 +# CHECK-ASM: encoding: [0x99,0x9e] +c.subw a3, a4 +# CHECK-ASM-AND-OBJ: c.addw a0, a2 +# CHECK-ASM: encoding: [0x31,0x9d] # CHECK-NO-EXT: error: instruction use requires an option to be enabled -c.addw a0, a2 +c.addw a0, a2 -# CHECK-INST: c.addiw a3, -32 -# CHECK: encoding: [0x81,0x36] +# CHECK-ASM-AND-OBJ: c.addiw a3, -32 +# CHECK-ASM: encoding: [0x81,0x36] # CHECK-NO-EXT: error: instruction use requires an option to be enabled -c.addiw a3, -32 -# CHECK-INST: c.addiw a3, 31 -# CHECK: encoding: [0xfd,0x26] +c.addiw a3, -32 +# CHECK-ASM-AND-OBJ: c.addiw a3, 31 +# CHECK-ASM: encoding: [0xfd,0x26] # CHECK-NO-EXT: error: instruction use requires an option to be enabled -c.addiw a3, 31 +c.addiw a3, 31 -# CHECK-INST: c.slli s0, 1 -# CHECK: encoding: [0x06,0x04] +# CHECK-ASM-AND-OBJ: c.slli s0, 1 +# CHECK-ASM: encoding: [0x06,0x04] # CHECK-NO-EXT: error: instruction use requires an option to be enabled -c.slli s0, 1 -# CHECK-INST: c.srli a3, 63 -# CHECK: encoding: [0xfd,0x92] -c.srli a3, 63 -# CHECK-INST: c.srai a2, 63 -# CHECK: encoding: [0x7d,0x96] -c.srai a2, 63 +c.slli s0, 1 +# CHECK-ASM-AND-OBJ: c.srli a3, 63 +# CHECK-ASM: encoding: [0xfd,0x92] +c.srli a3, 63 +# CHECK-ASM-AND-OBJ: c.srai a2, 63 +# CHECK-ASM: encoding: [0x7d,0x96] +c.srai a2, 63 diff --git a/test/MC/RISCV/rv64d-valid.s b/test/MC/RISCV/rv64d-valid.s index c8dd5696f47..06ce1d36460 100644 --- a/test/MC/RISCV/rv64d-valid.s +++ b/test/MC/RISCV/rv64d-valid.s @@ -1,50 +1,53 @@ # RUN: llvm-mc %s -triple=riscv64 -mattr=+d -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+d < %s \ -# RUN: | llvm-objdump -mattr=+d -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+d < %s \ +# RUN: | llvm-objdump -mattr=+d -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# # RUN: not llvm-mc -triple riscv32 -mattr=+d < %s 2>&1 \ # RUN: | FileCheck -check-prefix=CHECK-RV32 %s -# CHECK-INST: fcvt.l.d a0, ft0, dyn -# CHECK: encoding: [0x53,0x75,0x20,0xc2] +# FIXME: error messages for rv32d are misleading + +# CHECK-ASM-AND-OBJ: fcvt.l.d a0, ft0, dyn +# CHECK-ASM: encoding: [0x53,0x75,0x20,0xc2] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.l.d a0, ft0, dyn -# CHECK-INST: fcvt.lu.d a1, ft1, dyn -# CHECK: encoding: [0xd3,0xf5,0x30,0xc2] +# CHECK-ASM-AND-OBJ: fcvt.lu.d a1, ft1, dyn +# CHECK-ASM: encoding: [0xd3,0xf5,0x30,0xc2] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.lu.d a1, ft1, dyn -# CHECK-INST: fmv.x.d a2, ft2 -# CHECK: encoding: [0x53,0x06,0x01,0xe2] +# CHECK-ASM-AND-OBJ: fmv.x.d a2, ft2 +# CHECK-ASM: encoding: [0x53,0x06,0x01,0xe2] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fmv.x.d a2, ft2 -# CHECK-INST: fcvt.d.l ft3, a3, dyn -# CHECK: encoding: [0xd3,0xf1,0x26,0xd2] +# CHECK-ASM-AND-OBJ: fcvt.d.l ft3, a3, dyn +# CHECK-ASM: encoding: [0xd3,0xf1,0x26,0xd2] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.d.l ft3, a3, dyn -# CHECK-INST: fcvt.d.lu ft4, a4, dyn -# CHECK: encoding: [0x53,0x72,0x37,0xd2] +# CHECK-ASM-AND-OBJ: fcvt.d.lu ft4, a4, dyn +# CHECK-ASM: encoding: [0x53,0x72,0x37,0xd2] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.d.lu ft4, a4, dyn -# CHECK-INST: fmv.d.x ft5, a5 -# CHECK: encoding: [0xd3,0x82,0x07,0xf2] +# CHECK-ASM-AND-OBJ: fmv.d.x ft5, a5 +# CHECK-ASM: encoding: [0xd3,0x82,0x07,0xf2] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fmv.d.x ft5, a5 # Rounding modes -# CHECK-INST: fcvt.d.l ft3, a3, rne -# CHECK: encoding: [0xd3,0x81,0x26,0xd2] +# CHECK-ASM-AND-OBJ: fcvt.d.l ft3, a3, rne +# CHECK-ASM: encoding: [0xd3,0x81,0x26,0xd2] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.d.l ft3, a3, rne -# CHECK-INST: fcvt.d.lu ft4, a4, rtz -# CHECK: encoding: [0x53,0x12,0x37,0xd2] +# CHECK-ASM-AND-OBJ: fcvt.d.lu ft4, a4, rtz +# CHECK-ASM: encoding: [0x53,0x12,0x37,0xd2] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.d.lu ft4, a4, rtz -# CHECK-INST: fcvt.l.d a0, ft0, rdn -# CHECK: encoding: [0x53,0x25,0x20,0xc2] +# CHECK-ASM-AND-OBJ: fcvt.l.d a0, ft0, rdn +# CHECK-ASM: encoding: [0x53,0x25,0x20,0xc2] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.l.d a0, ft0, rdn -# CHECK-INST: fcvt.lu.d a1, ft1, rup -# CHECK: encoding: [0xd3,0xb5,0x30,0xc2] +# CHECK-ASM-AND-OBJ: fcvt.lu.d a1, ft1, rup +# CHECK-ASM: encoding: [0xd3,0xb5,0x30,0xc2] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.lu.d a1, ft1, rup diff --git a/test/MC/RISCV/rv64dc-valid.s b/test/MC/RISCV/rv64dc-valid.s index c9ef4cbf289..18f1a68df60 100644 --- a/test/MC/RISCV/rv64dc-valid.s +++ b/test/MC/RISCV/rv64dc-valid.s @@ -1,29 +1,29 @@ # RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+d -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+d < %s \ -# RUN: | llvm-objdump -mattr=+d -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: not llvm-mc -triple riscv64 -mattr=+c\ +# RUN: | llvm-objdump -mattr=+c,+d -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# +# RUN: not llvm-mc -triple riscv64 -mattr=+c \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s -# RUN: not llvm-mc -triple riscv64 \ -# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s +# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s -# CHECK-INST: c.fldsp fs0, 504(sp) -# CHECK: encoding: [0x7e,0x34] +# CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp) +# CHECK-ASM: encoding: [0x7e,0x34] # CHECK-NO-EXT: error: instruction use requires an option to be enabled c.fldsp fs0, 504(sp) -# CHECK-INST: c.fsdsp fa7, 504(sp) -# CHECK: encoding: [0xc6,0xbf] +# CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp) +# CHECK-ASM: encoding: [0xc6,0xbf] # CHECK-NO-EXT: error: instruction use requires an option to be enabled c.fsdsp fa7, 504(sp) -# CHECK-INST: c.fld fa3, 248(a5) -# CHECK: encoding: [0xf4,0x3f] +# CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5) +# CHECK-ASM: encoding: [0xf4,0x3f] # CHECK-NO-EXT: error: instruction use requires an option to be enabled c.fld fa3, 248(a5) -# CHECK-INST: c.fsd fa2, 248(a1) -# CHECK: encoding: [0xf0,0xbd] +# CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1) +# CHECK-ASM: encoding: [0xf0,0xbd] # CHECK-NO-EXT: error: instruction use requires an option to be enabled c.fsd fa2, 248(a1) diff --git a/test/MC/RISCV/rv64f-valid.s b/test/MC/RISCV/rv64f-valid.s index 69b503bef80..caf6d081151 100644 --- a/test/MC/RISCV/rv64f-valid.s +++ b/test/MC/RISCV/rv64f-valid.s @@ -1,38 +1,41 @@ # RUN: llvm-mc %s -triple=riscv64 -mattr=+f -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ -# RUN: | llvm-objdump -mattr=+f -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+f < %s \ +# RUN: | llvm-objdump -mattr=+f -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s +# # RUN: not llvm-mc -triple riscv32 -mattr=+f < %s 2>&1 \ # RUN: | FileCheck -check-prefix=CHECK-RV32 %s -# CHECK-INST: fcvt.l.s a0, ft0, dyn -# CHECK: encoding: [0x53,0x75,0x20,0xc0] +# FIXME: error messages for rv32f are misleading + +# CHECK-ASM-AND-OBJ: fcvt.l.s a0, ft0, dyn +# CHECK-ASM: encoding: [0x53,0x75,0x20,0xc0] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.l.s a0, ft0, dyn -# CHECK-INST: fcvt.lu.s a1, ft1, dyn -# CHECK: encoding: [0xd3,0xf5,0x30,0xc0] +# CHECK-ASM-AND-OBJ: fcvt.lu.s a1, ft1, dyn +# CHECK-ASM: encoding: [0xd3,0xf5,0x30,0xc0] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.lu.s a1, ft1, dyn -# CHECK-INST: fcvt.s.l ft2, a2, dyn -# CHECK: encoding: [0x53,0x71,0x26,0xd0] +# CHECK-ASM-AND-OBJ: fcvt.s.l ft2, a2, dyn +# CHECK-ASM: encoding: [0x53,0x71,0x26,0xd0] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.s.l ft2, a2, dyn -# CHECK-INST: fcvt.s.lu ft3, a3, dyn -# CHECK: encoding: [0xd3,0xf1,0x36,0xd0] +# CHECK-ASM-AND-OBJ: fcvt.s.lu ft3, a3, dyn +# CHECK-ASM: encoding: [0xd3,0xf1,0x36,0xd0] # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.s.lu ft3, a3, dyn # Rounding modes -# CHECK-INST: fcvt.l.s a4, ft4, rne +# CHECK-ASM-AND-OBJ: fcvt.l.s a4, ft4, rne # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.l.s a4, ft4, rne -# CHECK-INST: fcvt.lu.s a5, ft5, rtz +# CHECK-ASM-AND-OBJ: fcvt.lu.s a5, ft5, rtz # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.lu.s a5, ft5, rtz -# CHECK-INST: fcvt.s.l ft6, a6, rdn +# CHECK-ASM-AND-OBJ: fcvt.s.l ft6, a6, rdn # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.s.l ft6, a6, rdn -# CHECK-INST: fcvt.s.lu ft7, a7, rup +# CHECK-ASM-AND-OBJ: fcvt.s.lu ft7, a7, rup # CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled fcvt.s.lu ft7, a7, rup diff --git a/test/MC/RISCV/rv64i-valid.s b/test/MC/RISCV/rv64i-valid.s index 57868c41bea..337b996e447 100644 --- a/test/MC/RISCV/rv64i-valid.s +++ b/test/MC/RISCV/rv64i-valid.s @@ -1,99 +1,99 @@ # RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ -# RUN: | llvm-objdump -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 < %s \ +# RUN: | llvm-objdump -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s -# CHECK-INST: lwu zero, 4(ra) -# CHECK: encoding: [0x03,0xe0,0x40,0x00] +# CHECK-ASM-AND-OBJ: lwu zero, 4(ra) +# CHECK-ASM: encoding: [0x03,0xe0,0x40,0x00] lwu x0, 4(x1) -# CHECK-INST: lwu sp, 4(gp) -# CHECK: encoding: [0x03,0xe1,0x41,0x00] +# CHECK-ASM-AND-OBJ: lwu sp, 4(gp) +# CHECK-ASM: encoding: [0x03,0xe1,0x41,0x00] lwu x2, +4(x3) -# CHECK-INST: lwu tp, -2048(t0) -# CHECK: encoding: [0x03,0xe2,0x02,0x80] +# CHECK-ASM-AND-OBJ: lwu tp, -2048(t0) +# CHECK-ASM: encoding: [0x03,0xe2,0x02,0x80] lwu x4, -2048(x5) -# CHECK-INST: lwu t1, -2048(t2) -# CHECK: encoding: [0x03,0xe3,0x03,0x80] +# CHECK-ASM-AND-OBJ: lwu t1, -2048(t2) +# CHECK-ASM: encoding: [0x03,0xe3,0x03,0x80] lwu x6, %lo(2048)(x7) -# CHECK-INST: lwu s0, 2047(s1) -# CHECK: encoding: [0x03,0xe4,0xf4,0x7f] +# CHECK-ASM-AND-OBJ: lwu s0, 2047(s1) +# CHECK-ASM: encoding: [0x03,0xe4,0xf4,0x7f] lwu x8, 2047(x9) -# CHECK-INST: ld a0, -2048(a1) -# CHECK: encoding: [0x03,0xb5,0x05,0x80] +# CHECK-ASM-AND-OBJ: ld a0, -2048(a1) +# CHECK-ASM: encoding: [0x03,0xb5,0x05,0x80] ld x10, -2048(x11) -# CHECK-INST: ld a2, -2048(a3) -# CHECK: encoding: [0x03,0xb6,0x06,0x80] +# CHECK-ASM-AND-OBJ: ld a2, -2048(a3) +# CHECK-ASM: encoding: [0x03,0xb6,0x06,0x80] ld x12, %lo(2048)(x13) -# CHECK-INST: ld a4, 2047(a5) -# CHECK: encoding: [0x03,0xb7,0xf7,0x7f] +# CHECK-ASM-AND-OBJ: ld a4, 2047(a5) +# CHECK-ASM: encoding: [0x03,0xb7,0xf7,0x7f] ld x14, 2047(x15) -# CHECK-INST: sd a6, -2048(a7) -# CHECK: encoding: [0x23,0xb0,0x08,0x81] +# CHECK-ASM-AND-OBJ: sd a6, -2048(a7) +# CHECK-ASM: encoding: [0x23,0xb0,0x08,0x81] sd x16, -2048(x17) -# CHECK-INST: sd s2, -2048(s3) -# CHECK: encoding: [0x23,0xb0,0x29,0x81] +# CHECK-ASM-AND-OBJ: sd s2, -2048(s3) +# CHECK-ASM: encoding: [0x23,0xb0,0x29,0x81] sd x18, %lo(2048)(x19) -# CHECK-INST: sd s4, 2047(s5) -# CHECK: encoding: [0xa3,0xbf,0x4a,0x7f] +# CHECK-ASM-AND-OBJ: sd s4, 2047(s5) +# CHECK-ASM: encoding: [0xa3,0xbf,0x4a,0x7f] sd x20, 2047(x21) -# CHECK-INST: slli s6, s7, 45 -# CHECK: encoding: [0x13,0x9b,0xdb,0x02] +# CHECK-ASM-AND-OBJ: slli s6, s7, 45 +# CHECK-ASM: encoding: [0x13,0x9b,0xdb,0x02] slli x22, x23, 45 -# CHECK-INST: srli s8, s9, 0 -# CHECK: encoding: [0x13,0xdc,0x0c,0x00] +# CHECK-ASM-AND-OBJ: srli s8, s9, 0 +# CHECK-ASM: encoding: [0x13,0xdc,0x0c,0x00] srli x24, x25, 0 -# CHECK-INST: srai s10, s11, 31 -# CHECK: encoding: [0x13,0xdd,0xfd,0x41] +# CHECK-ASM-AND-OBJ: srai s10, s11, 31 +# CHECK-ASM: encoding: [0x13,0xdd,0xfd,0x41] srai x26, x27, 31 -# CHECK-INST: addiw t3, t4, -2048 -# CHECK: encoding: [0x1b,0x8e,0x0e,0x80] +# CHECK-ASM-AND-OBJ: addiw t3, t4, -2048 +# CHECK-ASM: encoding: [0x1b,0x8e,0x0e,0x80] addiw x28, x29, -2048 -# CHECK-INST: addiw t5, t6, 2047 -# CHECK: encoding: [0x1b,0x8f,0xff,0x7f] +# CHECK-ASM-AND-OBJ: addiw t5, t6, 2047 +# CHECK-ASM: encoding: [0x1b,0x8f,0xff,0x7f] addiw x30, x31, 2047 -# CHECK-INST: slliw zero, ra, 0 -# CHECK: encoding: [0x1b,0x90,0x00,0x00] +# CHECK-ASM-AND-OBJ: slliw zero, ra, 0 +# CHECK-ASM: encoding: [0x1b,0x90,0x00,0x00] slliw zero, ra, 0 -# CHECK-INST: slliw sp, gp, 31 -# CHECK: encoding: [0x1b,0x91,0xf1,0x01] +# CHECK-ASM-AND-OBJ: slliw sp, gp, 31 +# CHECK-ASM: encoding: [0x1b,0x91,0xf1,0x01] slliw sp, gp, 31 -# CHECK-INST: srliw tp, t0, 0 -# CHECK: encoding: [0x1b,0xd2,0x02,0x00] +# CHECK-ASM-AND-OBJ: srliw tp, t0, 0 +# CHECK-ASM: encoding: [0x1b,0xd2,0x02,0x00] srliw tp, t0, 0 -# CHECK-INST: srliw t1, t2, 31 -# CHECK: encoding: [0x1b,0xd3,0xf3,0x01] +# CHECK-ASM-AND-OBJ: srliw t1, t2, 31 +# CHECK-ASM: encoding: [0x1b,0xd3,0xf3,0x01] srliw t1, t2, 31 -# CHECK-INST: sraiw s0, s1, 0 -# CHECK: encoding: [0x1b,0xd4,0x04,0x40] +# CHECK-ASM-AND-OBJ: sraiw s0, s1, 0 +# CHECK-ASM: encoding: [0x1b,0xd4,0x04,0x40] sraiw s0, s1, 0 -# CHECK-INST: sraiw a0, a1, 31 -# CHECK: encoding: [0x1b,0xd5,0xf5,0x41] +# CHECK-ASM-AND-OBJ: sraiw a0, a1, 31 +# CHECK-ASM: encoding: [0x1b,0xd5,0xf5,0x41] sraiw a0, a1, 31 -# CHECK-INST: addw a2, a3, a4 -# CHECK: encoding: [0x3b,0x86,0xe6,0x00] +# CHECK-ASM-AND-OBJ: addw a2, a3, a4 +# CHECK-ASM: encoding: [0x3b,0x86,0xe6,0x00] addw a2, a3, a4 -# CHECK-INST: addw a5, a6, a7 -# CHECK: encoding: [0xbb,0x07,0x18,0x01] +# CHECK-ASM-AND-OBJ: addw a5, a6, a7 +# CHECK-ASM: encoding: [0xbb,0x07,0x18,0x01] addw a5, a6, a7 -# CHECK-INST: subw s2, s3, s4 -# CHECK: encoding: [0x3b,0x89,0x49,0x41] +# CHECK-ASM-AND-OBJ: subw s2, s3, s4 +# CHECK-ASM: encoding: [0x3b,0x89,0x49,0x41] subw s2, s3, s4 -# CHECK-INST: subw s5, s6, s7 -# CHECK: encoding: [0xbb,0x0a,0x7b,0x41] +# CHECK-ASM-AND-OBJ: subw s5, s6, s7 +# CHECK-ASM: encoding: [0xbb,0x0a,0x7b,0x41] subw s5, s6, s7 -# CHECK-INST: sllw s8, s9, s10 -# CHECK: encoding: [0x3b,0x9c,0xac,0x01] +# CHECK-ASM-AND-OBJ: sllw s8, s9, s10 +# CHECK-ASM: encoding: [0x3b,0x9c,0xac,0x01] sllw s8, s9, s10 -# CHECK-INST: srlw s11, t3, t4 -# CHECK: encoding: [0xbb,0x5d,0xde,0x01] +# CHECK-ASM-AND-OBJ: srlw s11, t3, t4 +# CHECK-ASM: encoding: [0xbb,0x5d,0xde,0x01] srlw s11, t3, t4 -# CHECK-INST: sraw t5, t6, zero -# CHECK: encoding: [0x3b,0xdf,0x0f,0x40] +# CHECK-ASM-AND-OBJ: sraw t5, t6, zero +# CHECK-ASM: encoding: [0x3b,0xdf,0x0f,0x40] sraw t5, t6, zero diff --git a/test/MC/RISCV/rv64m-valid.s b/test/MC/RISCV/rv64m-valid.s index b34666c0310..f1a98bf8f11 100644 --- a/test/MC/RISCV/rv64m-valid.s +++ b/test/MC/RISCV/rv64m-valid.s @@ -1,21 +1,21 @@ # RUN: llvm-mc %s -triple=riscv64 -mattr=+m -riscv-no-aliases -show-encoding \ -# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+m < %s \ -# RUN: | llvm-objdump -mattr=+m -riscv-no-aliases -d - \ -# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+m < %s \ +# RUN: | llvm-objdump -mattr=+m -riscv-no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s -# CHECK-INST: mulw ra, sp, gp -# CHECK: encoding: [0xbb,0x00,0x31,0x02] +# CHECK-ASM-AND-OBJ: mulw ra, sp, gp +# CHECK-ASM: encoding: [0xbb,0x00,0x31,0x02] mulw ra, sp, gp -# CHECK-INST: divw tp, t0, t1 -# CHECK: encoding: [0x3b,0xc2,0x62,0x02] +# CHECK-ASM-AND-OBJ: divw tp, t0, t1 +# CHECK-ASM: encoding: [0x3b,0xc2,0x62,0x02] divw tp, t0, t1 -# CHECK-INST: divuw t2, s0, s2 -# CHECK: encoding: [0xbb,0x53,0x24,0x03] +# CHECK-ASM-AND-OBJ: divuw t2, s0, s2 +# CHECK-ASM: encoding: [0xbb,0x53,0x24,0x03] divuw t2, s0, s2 -# CHECK-INST: remw a0, a1, a2 -# CHECK: encoding: [0x3b,0xe5,0xc5,0x02] +# CHECK-ASM-AND-OBJ: remw a0, a1, a2 +# CHECK-ASM: encoding: [0x3b,0xe5,0xc5,0x02] remw a0, a1, a2 -# CHECK-INST: remuw a3, a4, a5 -# CHECK: encoding: [0xbb,0x76,0xf7,0x02] +# CHECK-ASM-AND-OBJ: remuw a3, a4, a5 +# CHECK-ASM: encoding: [0xbb,0x76,0xf7,0x02] remuw a3, a4, a5