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ARM: Fix ELF global base reg intialization.

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The create machine code wasn't properly in SSA, which the machine verifier
properly complains about. Now that fast-isel is closer to verifier clean,
errors like this show up more clearly.

Additionally, the Thumb pseudo tPICADD was used for both ARM and Thumb
mode functions, which is obviously wrong. Fix that along the way.

Test case is part of the following commit which will finish making an
additional fast-isel test verifier clean an enable it for the
regression test suite. This commit is separate since its not just
a verifier cleanup, but an actual correctness issue.

rdar://12594152 (for the fast-isel verifier aspects)

llvm-svn: 189269
This commit is contained in:
Jim Grosbach 2013-08-26 20:07:25 +00:00
parent 84204dd94d
commit 2b30758f49
1 changed files with 8 additions and 3 deletions
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11
lib/Target/ARM/ARMInstrInfo.cpp
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@ -22,6 +22,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Function.h" #include "llvm/IR/Function.h"
#include "llvm/IR/GlobalVariable.h" #include "llvm/IR/GlobalVariable.h"
#include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCAsmInfo.h"
@ -119,20 +120,24 @@ namespace {
MachineBasicBlock &FirstMBB = MF.front(); MachineBasicBlock &FirstMBB = MF.front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin(); MachineBasicBlock::iterator MBBI = FirstMBB.begin();
DebugLoc DL = FirstMBB.findDebugLoc(MBBI); DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
unsigned GlobalBaseReg = AFI->getGlobalBaseReg(); unsigned TempReg =
MF.getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ?
ARM::t2LDRpci : ARM::LDRcp; ARM::t2LDRpci : ARM::LDRcp;
const TargetInstrInfo &TII = *TM->getInstrInfo(); const TargetInstrInfo &TII = *TM->getInstrInfo();
MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL, MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
TII.get(Opc), GlobalBaseReg) TII.get(Opc), TempReg)
.addConstantPoolIndex(Idx); .addConstantPoolIndex(Idx);
if (Opc == ARM::LDRcp) if (Opc == ARM::LDRcp)
MIB.addImm(0); MIB.addImm(0);
AddDefaultPred(MIB); AddDefaultPred(MIB);
// Fix the GOT address by adding pc. // Fix the GOT address by adding pc.
unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? ARM::tPICADD
: ARM::PICADD;
BuildMI(FirstMBB, MBBI, DL, TII.get(ARM::tPICADD), GlobalBaseReg) BuildMI(FirstMBB, MBBI, DL, TII.get(ARM::tPICADD), GlobalBaseReg)
.addReg(GlobalBaseReg).addImm(ARMPCLabelIndex); .addReg(TempReg).addImm(ARMPCLabelIndex);
return true; return true;
} }