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AMDGPU: Combine directly on mul24 intrinsics
The problem these are supposed to work around can occur before the intrinsics are lowered into the nodes. Try to directly simplify them so they are matched before the bit assert operations can be optimized out. llvm-svn: 369994
This commit is contained in:
Matt Arsenault
parent
8c4f29af2a
commit
2b606d0a39
@ -506,6 +506,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::FABS);
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setTargetDAGCombine(ISD::AssertZext);
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setTargetDAGCombine(ISD::AssertSext);
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setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
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}
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//===----------------------------------------------------------------------===//
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@ -2771,8 +2772,16 @@ static bool isI24(SDValue Op, SelectionDAG &DAG) {
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static SDValue simplifyI24(SDNode *Node24,
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TargetLowering::DAGCombinerInfo &DCI) {
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SelectionDAG &DAG = DCI.DAG;
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SDValue LHS = Node24->getOperand(0);
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SDValue RHS = Node24->getOperand(1);
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bool IsIntrin = Node24->getOpcode() == ISD::INTRINSIC_WO_CHAIN;
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SDValue LHS = IsIntrin ? Node24->getOperand(1) : Node24->getOperand(0);
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SDValue RHS = IsIntrin ? Node24->getOperand(2) : Node24->getOperand(1);
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unsigned NewOpcode = Node24->getOpcode();
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if (IsIntrin) {
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unsigned IID = cast<ConstantSDNode>(Node24->getOperand(0))->getZExtValue();
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NewOpcode = IID == Intrinsic::amdgcn_mul_i24 ?
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AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
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}
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APInt Demanded = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 24);
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@ -2782,7 +2791,7 @@ static SDValue simplifyI24(SDNode *Node24,
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SDValue DemandedLHS = DAG.GetDemandedBits(LHS, Demanded);
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SDValue DemandedRHS = DAG.GetDemandedBits(RHS, Demanded);
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if (DemandedLHS || DemandedRHS)
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return DAG.getNode(Node24->getOpcode(), SDLoc(Node24), Node24->getVTList(),
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return DAG.getNode(NewOpcode, SDLoc(Node24), Node24->getVTList(),
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DemandedLHS ? DemandedLHS : LHS,
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DemandedRHS ? DemandedRHS : RHS);
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@ -3020,6 +3029,19 @@ SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,
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return SDValue();
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}
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SDValue AMDGPUTargetLowering::performIntrinsicWOChainCombine(
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SDNode *N, DAGCombinerInfo &DCI) const {
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unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
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switch (IID) {
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case Intrinsic::amdgcn_mul_i24:
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case Intrinsic::amdgcn_mul_u24:
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return simplifyI24(N, DCI);
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default:
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return SDValue();
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}
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}
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/// Split the 64-bit value \p LHS into two 32-bit components, and perform the
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/// binary operation \p Opc to it with the corresponding constant operands.
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SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(
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@ -4108,6 +4130,8 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::AssertZext:
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case ISD::AssertSext:
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return performAssertSZExtCombine(N, DCI);
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case ISD::INTRINSIC_WO_CHAIN:
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return performIntrinsicWOChainCombine(N, DCI);
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}
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return SDValue();
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}
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@ -78,6 +78,7 @@ protected:
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SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
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unsigned Opc, SDValue LHS,
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=GCN --check-prefix=FUNC
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=GCN --check-prefix=FUNC
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
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@ -9,8 +9,8 @@
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; Make sure we aren't masking the inputs.
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; CM-NOT: AND
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; CM: MULADD_INT24
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; SI-NOT: and
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; SI: v_mad_i32_i24
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; GCN-NOT: and
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; GCN: v_mad_i32_i24
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define amdgpu_kernel void @i32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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entry:
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%0 = shl i32 %a, 8
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@ -22,3 +22,100 @@ entry:
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}mad24_known_bits_destroyed:
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; GCN: s_waitcnt
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; GCN-NEXT: v_mad_i32_i24
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; GCN-NEXT: v_mul_i32_i24
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; GCN-NEXT: s_setpc_b64
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define i32 @mad24_known_bits_destroyed(i32 %a, i32 %b, i32 %c) {
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%shl.0 = shl i32 %a, 8
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%sra.0 = ashr i32 %shl.0, 8
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%shl.1 = shl i32 %b, 8
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%sra.1 = ashr i32 %shl.1, 8
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%mul0 = mul nsw i32 %sra.0, %sra.1
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%add0 = add nsw i32 %mul0, %c
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%shl.2 = shl i32 %add0, 8
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%sra.2 = ashr i32 %shl.2, 8
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%shl.3 = shl i32 %sra.0, 8
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%sra.3 = ashr i32 %shl.3, 8
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%mul1 = mul nsw i32 %sra.2, %sra.3
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ret i32 %mul1
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}
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; GCN-LABEL: {{^}}mad24_intrin_known_bits_destroyed:
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; GCN: s_waitcnt
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; GCN-NEXT: v_mad_i32_i24
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; GCN-NEXT: v_mul_i32_i24
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; GCN-NEXT: s_setpc_b64
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define i32 @mad24_intrin_known_bits_destroyed(i32 %a, i32 %b, i32 %c) {
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%shl.0 = shl i32 %a, 8
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%sra.0 = ashr i32 %shl.0, 8
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%shl.1 = shl i32 %b, 8
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%sra.1 = ashr i32 %shl.1, 8
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%mul0 = call i32 @llvm.amdgcn.mul.i24(i32 %sra.0, i32 %sra.1)
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%add0 = add nsw i32 %mul0, %c
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%shl.2 = shl i32 %add0, 8
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%sra.2 = ashr i32 %shl.2, 8
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%shl.3 = shl i32 %sra.0, 8
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%sra.3 = ashr i32 %shl.3, 8
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%mul1 = mul nsw i32 %sra.2, %sra.3
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ret i32 %mul1
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}
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; Make sure no unnecessary BFEs are emitted in the loop.
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; GCN-LABEL: {{^}}mad24_destroyed_knownbits_2:
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; GCN-NOT: v_bfe
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; GCN: v_mad_i32_i24
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; GCN-NOT: v_bfe
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; GCN: v_mad_i32_i24
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; GCN-NOT: v_bfe
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; GCN: v_mad_i32_i24
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; GCN-NOT: v_bfe
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; GCN: v_mad_i32_i24
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; GCN-NOT: v_bfe
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define void @mad24_destroyed_knownbits_2(i32 %arg, i32 %arg1, i32 %arg2, i32 addrspace(1)* %arg3) {
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bb:
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br label %bb6
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bb5: ; preds = %bb6
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ret void
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bb6: ; preds = %bb6, %bb
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%tmp = phi i32 [ %tmp27, %bb6 ], [ 0, %bb ]
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%tmp7 = phi i32 [ %arg2, %bb6 ], [ 1, %bb ]
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%tmp8 = phi i32 [ %tmp26, %bb6 ], [ %arg, %bb ]
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%tmp9 = shl i32 %tmp7, 8
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%tmp10 = ashr exact i32 %tmp9, 8
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%tmp11 = shl i32 %tmp8, 8
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%tmp12 = ashr exact i32 %tmp11, 8
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%tmp13 = mul nsw i32 %tmp12, %tmp10
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%tmp14 = add nsw i32 %tmp13, %tmp7
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%tmp15 = shl i32 %tmp14, 8
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%tmp16 = ashr exact i32 %tmp15, 8
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%tmp17 = mul nsw i32 %tmp16, %tmp10
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%tmp18 = add nsw i32 %tmp17, %tmp14
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%tmp19 = shl i32 %tmp18, 8
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%tmp20 = ashr exact i32 %tmp19, 8
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%tmp21 = mul nsw i32 %tmp20, %tmp16
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%tmp22 = add nsw i32 %tmp21, %tmp18
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%tmp23 = shl i32 %tmp22, 8
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%tmp24 = ashr exact i32 %tmp23, 8
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%tmp25 = mul nsw i32 %tmp24, %tmp20
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%tmp26 = add nsw i32 %tmp25, %tmp22
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store i32 %tmp26, i32 addrspace(1)* %arg3
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%tmp27 = add nuw i32 %tmp, 1
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%tmp28 = icmp eq i32 %tmp27, %arg1
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br i1 %tmp28, label %bb5, label %bb6
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}
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declare i32 @llvm.amdgcn.mul.i24(i32, i32)
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