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PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec

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instructions.

llvm-svn: 73009
This commit is contained in:
Eli Friedman 2009-06-07 01:07:55 +00:00
parent acd23348af
commit 2b6cb1684f
2 changed files with 32 additions and 0 deletions
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22
lib/Target/PowerPC/PPCInstrAltivec.td
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@ -666,3 +666,25 @@ def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
(VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC)>;
// Vector shifts
def : Pat<(v16i8 (shl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))),
(v16i8 (VSLB VRRC:$vA, VRRC:$vB))>;
def : Pat<(v8i16 (shl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))),
(v8i16 (VSLH VRRC:$vA, VRRC:$vB))>;
def : Pat<(v4i32 (shl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))),
(v4i32 (VSLW VRRC:$vA, VRRC:$vB))>;
def : Pat<(v16i8 (srl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))),
(v16i8 (VSRB VRRC:$vA, VRRC:$vB))>;
def : Pat<(v8i16 (srl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))),
(v8i16 (VSRH VRRC:$vA, VRRC:$vB))>;
def : Pat<(v4i32 (srl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))),
(v4i32 (VSRW VRRC:$vA, VRRC:$vB))>;
def : Pat<(v16i8 (sra (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))),
(v16i8 (VSRAB VRRC:$vA, VRRC:$vB))>;
def : Pat<(v8i16 (sra (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))),
(v8i16 (VSRAH VRRC:$vA, VRRC:$vB))>;
def : Pat<(v4i32 (sra (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))),
(v4i32 (VSRAW VRRC:$vA, VRRC:$vB))>;

10
test/CodeGen/PowerPC/vec_shift.ll Normal file
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@ -0,0 +1,10 @@
; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5
; PR3628
define void @update(<4 x i32> %val, <4 x i32>* %dst) nounwind {
entry:
%shl = shl <4 x i32> %val, < i32 4, i32 3, i32 2, i32 1 >
%shr = ashr <4 x i32> %shl, < i32 1, i32 2, i32 3, i32 4 >
store <4 x i32> %shr, <4 x i32>* %dst
ret void
}