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R600/SI: Add assembler support for FLAT instructions
- Add glc, slc, and tfe operands to flat instructions - Add missing flat instructions - Fix the encoding of flat_load_dwordx3 and flat_store_dwordx3. llvm-svn: 239637
This commit is contained in:
Tom Stellard
parent
5e21e81e4e
commit
2b78afe7cf
@ -24,6 +24,11 @@ DS Instructions
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---------------
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All DS instructions are supported.
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FLAT Instructions
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------------------
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These instructions are only present in the Sea Islands and Volcanic Islands
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instruction set. All FLAT instructions are supported for these architectures
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MUBUF Instructions
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------------------
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All non-atomic MUBUF instructions are supported.
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@ -376,6 +376,10 @@ public:
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OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
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OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
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OperandMatchResultTy parseFlatOptionalOps(OperandVector &Operands);
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OperandMatchResultTy parseFlatAtomicOptionalOps(OperandVector &Operands);
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void cvtFlat(MCInst &Inst, const OperandVector &Operands);
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void cvtMubuf(MCInst &Inst, const OperandVector &Operands);
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OperandMatchResultTy parseOffset(OperandVector &Operands);
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OperandMatchResultTy parseMubufOptionalOps(OperandVector &Operands);
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@ -1091,6 +1095,67 @@ AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {
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}
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}
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//===----------------------------------------------------------------------===//
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// flat
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//===----------------------------------------------------------------------===//
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static const OptionalOperand FlatOptionalOps [] = {
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{"glc", AMDGPUOperand::ImmTyGLC, true, 0, nullptr},
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{"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr},
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{"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
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};
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static const OptionalOperand FlatAtomicOptionalOps [] = {
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{"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr},
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{"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
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};
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseFlatOptionalOps(OperandVector &Operands) {
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return parseOptionalOps(FlatOptionalOps, Operands);
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseFlatAtomicOptionalOps(OperandVector &Operands) {
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return parseOptionalOps(FlatAtomicOptionalOps, Operands);
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}
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void AMDGPUAsmParser::cvtFlat(MCInst &Inst,
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const OperandVector &Operands) {
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std::map<AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
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for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
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// Add the register arguments
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if (Op.isReg()) {
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Op.addRegOperands(Inst, 1);
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continue;
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}
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// Handle 'glc' token which is sometimes hard-coded into the
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// asm string. There are no MCInst operands for these.
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if (Op.isToken())
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continue;
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// Handle optional arguments
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OptionalIdx[Op.getImmTy()] = i;
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}
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// flat atomic instructions don't have a glc argument.
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if (OptionalIdx.count(AMDGPUOperand::ImmTyGLC)) {
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unsigned GLCIdx = OptionalIdx[AMDGPUOperand::ImmTyGLC];
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((AMDGPUOperand &)*Operands[GLCIdx]).addImmOperands(Inst, 1);
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}
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unsigned SLCIdx = OptionalIdx[AMDGPUOperand::ImmTySLC];
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unsigned TFEIdx = OptionalIdx[AMDGPUOperand::ImmTyTFE];
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((AMDGPUOperand &)*Operands[SLCIdx]).addImmOperands(Inst, 1);
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((AMDGPUOperand &)*Operands[TFEIdx]).addImmOperands(Inst, 1);
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}
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//===----------------------------------------------------------------------===//
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// mubuf
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//===----------------------------------------------------------------------===//
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@ -41,89 +41,86 @@ defm V_LOG_LEGACY_F32 : VOP1Inst <vop1<0x45, 0x4c>, "v_log_legacy_f32",
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defm V_EXP_LEGACY_F32 : VOP1Inst <vop1<0x46, 0x4b>, "v_exp_legacy_f32",
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VOP_F32_F32
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>;
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} // End SubtargetPredicate = isCIVI
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//===----------------------------------------------------------------------===//
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// Flat Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasFlatAddressSpace] in {
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def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x00000008, "flat_load_ubyte", VGPR_32>;
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def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x00000009, "flat_load_sbyte", VGPR_32>;
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def FLAT_LOAD_USHORT : FLAT_Load_Helper <0x0000000a, "flat_load_ushort", VGPR_32>;
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def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0x0000000b, "flat_load_sshort", VGPR_32>;
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def FLAT_LOAD_DWORD : FLAT_Load_Helper <0x0000000c, "flat_load_dword", VGPR_32>;
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def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0x0000000d, "flat_load_dwordx2", VReg_64>;
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def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0x0000000e, "flat_load_dwordx4", VReg_128>;
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def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0x00000010, "flat_load_dwordx3", VReg_96>;
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def FLAT_STORE_BYTE : FLAT_Store_Helper <
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0x00000018, "flat_store_byte", VGPR_32
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>;
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def FLAT_STORE_SHORT : FLAT_Store_Helper <
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0x0000001a, "flat_store_short", VGPR_32
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>;
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def FLAT_STORE_DWORD : FLAT_Store_Helper <
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0x0000001c, "flat_store_dword", VGPR_32
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>;
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def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x8, "flat_load_ubyte", VGPR_32>;
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def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x9, "flat_load_sbyte", VGPR_32>;
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def FLAT_LOAD_USHORT : FLAT_Load_Helper <0xa, "flat_load_ushort", VGPR_32>;
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def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0xb, "flat_load_sshort", VGPR_32>;
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def FLAT_LOAD_DWORD : FLAT_Load_Helper <0xc, "flat_load_dword", VGPR_32>;
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def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0xd, "flat_load_dwordx2", VReg_64>;
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def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0xe, "flat_load_dwordx4", VReg_128>;
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def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0xf, "flat_load_dwordx3", VReg_96>;
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def FLAT_STORE_BYTE : FLAT_Store_Helper <0x18, "flat_store_byte", VGPR_32>;
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def FLAT_STORE_SHORT : FLAT_Store_Helper <0x1a, "flat_store_short", VGPR_32>;
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def FLAT_STORE_DWORD : FLAT_Store_Helper <0x1c, "flat_store_dword", VGPR_32>;
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def FLAT_STORE_DWORDX2 : FLAT_Store_Helper <
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0x0000001d, "flat_store_dwordx2", VReg_64
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0x1d, "flat_store_dwordx2", VReg_64
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>;
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def FLAT_STORE_DWORDX4 : FLAT_Store_Helper <
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0x0000001e, "flat_store_dwordx4", VReg_128
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0x1e, "flat_store_dwordx4", VReg_128
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>;
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def FLAT_STORE_DWORDX3 : FLAT_Store_Helper <
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0x0000001e, "flat_store_dwordx3", VReg_96
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0x1f, "flat_store_dwordx3", VReg_96
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>;
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defm FLAT_ATOMIC_SWAP : FLAT_ATOMIC <0x30, "flat_atomic_swap", VGPR_32>;
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defm FLAT_ATOMIC_CMPSWAP : FLAT_ATOMIC <
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0x31, "flat_atomic_cmpswap", VGPR_32, VReg_64
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>;
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defm FLAT_ATOMIC_ADD : FLAT_ATOMIC <0x32, "flat_atomic_add", VGPR_32>;
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defm FLAT_ATOMIC_SUB : FLAT_ATOMIC <0x33, "flat_atomic_sub", VGPR_32>;
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defm FLAT_ATOMIC_RSUB : FLAT_ATOMIC <0x34, "flat_atomic_rsub", VGPR_32>;
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defm FLAT_ATOMIC_SMIN : FLAT_ATOMIC <0x35, "flat_atomic_smin", VGPR_32>;
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defm FLAT_ATOMIC_UMIN : FLAT_ATOMIC <0x36, "flat_atomic_umin", VGPR_32>;
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defm FLAT_ATOMIC_SMAX : FLAT_ATOMIC <0x37, "flat_atomic_smax", VGPR_32>;
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defm FLAT_ATOMIC_UMAX : FLAT_ATOMIC <0x38, "flat_atomic_umax", VGPR_32>;
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defm FLAT_ATOMIC_AND : FLAT_ATOMIC <0x39, "flat_atomic_and", VGPR_32>;
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defm FLAT_ATOMIC_OR : FLAT_ATOMIC <0x3a, "flat_atomic_or", VGPR_32>;
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defm FLAT_ATOMIC_XOR : FLAT_ATOMIC <0x3b, "flat_atomic_xor", VGPR_32>;
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defm FLAT_ATOMIC_INC : FLAT_ATOMIC <0x3c, "flat_atomic_inc", VGPR_32>;
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defm FLAT_ATOMIC_DEC : FLAT_ATOMIC <0x3d, "flat_atomic_dec", VGPR_32>;
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defm FLAT_ATOMIC_FCMPSWAP : FLAT_ATOMIC <
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0x3e, "flat_atomic_fcmpswap", VGPR_32, VReg_64
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>;
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defm FLAT_ATOMIC_FMIN : FLAT_ATOMIC <0x3f, "flat_atomic_fmin", VGPR_32>;
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defm FLAT_ATOMIC_FMAX : FLAT_ATOMIC <0x40, "flat_atomic_fmax", VGPR_32>;
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defm FLAT_ATOMIC_SWAP_X2 : FLAT_ATOMIC <0x50, "flat_atomic_swap_x2", VReg_64>;
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defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_ATOMIC <
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0x51, "flat_atomic_cmpswap_x2", VReg_64, VReg_128
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>;
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defm FLAT_ATOMIC_ADD_X2 : FLAT_ATOMIC <0x52, "flat_atomic_add_x2", VReg_64>;
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defm FLAT_ATOMIC_SUB_X2 : FLAT_ATOMIC <0x53, "flat_atomic_sub_x2", VReg_64>;
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defm FLAT_ATOMIC_RSUB_X2 : FLAT_ATOMIC <0x54, "flat_atomic_rsub_x2", VReg_64>;
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defm FLAT_ATOMIC_SMIN_X2 : FLAT_ATOMIC <0x55, "flat_atomic_smin_x2", VReg_64>;
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defm FLAT_ATOMIC_UMIN_X2 : FLAT_ATOMIC <0x56, "flat_atomic_umin_x2", VReg_64>;
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defm FLAT_ATOMIC_SMAX_X2 : FLAT_ATOMIC <0x57, "flat_atomic_smax_x2", VReg_64>;
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defm FLAT_ATOMIC_UMAX_X2 : FLAT_ATOMIC <0x58, "flat_atomic_umax_x2", VReg_64>;
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defm FLAT_ATOMIC_AND_X2 : FLAT_ATOMIC <0x59, "flat_atomic_and_x2", VReg_64>;
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defm FLAT_ATOMIC_OR_X2 : FLAT_ATOMIC <0x5a, "flat_atomic_or_x2", VReg_64>;
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defm FLAT_ATOMIC_XOR_X2 : FLAT_ATOMIC <0x5b, "flat_atomic_xor_x2", VReg_64>;
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defm FLAT_ATOMIC_INC_X2 : FLAT_ATOMIC <0x5c, "flat_atomic_inc_x2", VReg_64>;
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defm FLAT_ATOMIC_DEC_X2 : FLAT_ATOMIC <0x5d, "flat_atomic_dec_x2", VReg_64>;
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defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_ATOMIC <
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0x5e, "flat_atomic_fcmpswap_x2", VReg_64, VReg_128
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>;
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defm FLAT_ATOMIC_FMIN_X2 : FLAT_ATOMIC <0x5f, "flat_atomic_fmin_x2", VReg_64>;
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defm FLAT_ATOMIC_FMAX_X2 : FLAT_ATOMIC <0x60, "flat_atomic_fmax_x2", VReg_64>;
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//def FLAT_ATOMIC_SWAP : FLAT_ <0x00000030, "flat_atomic_swap", []>;
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//def FLAT_ATOMIC_CMPSWAP : FLAT_ <0x00000031, "flat_atomic_cmpswap", []>;
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//def FLAT_ATOMIC_ADD : FLAT_ <0x00000032, "flat_atomic_add", []>;
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//def FLAT_ATOMIC_SUB : FLAT_ <0x00000033, "flat_atomic_sub", []>;
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//def FLAT_ATOMIC_RSUB : FLAT_ <0x00000034, "flat_atomic_rsub", []>;
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//def FLAT_ATOMIC_SMIN : FLAT_ <0x00000035, "flat_atomic_smin", []>;
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//def FLAT_ATOMIC_UMIN : FLAT_ <0x00000036, "flat_atomic_umin", []>;
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//def FLAT_ATOMIC_SMAX : FLAT_ <0x00000037, "flat_atomic_smax", []>;
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//def FLAT_ATOMIC_UMAX : FLAT_ <0x00000038, "flat_atomic_umax", []>;
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//def FLAT_ATOMIC_AND : FLAT_ <0x00000039, "flat_atomic_and", []>;
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//def FLAT_ATOMIC_OR : FLAT_ <0x0000003a, "flat_atomic_or", []>;
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//def FLAT_ATOMIC_XOR : FLAT_ <0x0000003b, "flat_atomic_xor", []>;
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//def FLAT_ATOMIC_INC : FLAT_ <0x0000003c, "flat_atomic_inc", []>;
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//def FLAT_ATOMIC_DEC : FLAT_ <0x0000003d, "flat_atomic_dec", []>;
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//def FLAT_ATOMIC_FCMPSWAP : FLAT_ <0x0000003e, "flat_atomic_fcmpswap", []>;
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//def FLAT_ATOMIC_FMIN : FLAT_ <0x0000003f, "flat_atomic_fmin", []>;
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//def FLAT_ATOMIC_FMAX : FLAT_ <0x00000040, "flat_atomic_fmax", []>;
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//def FLAT_ATOMIC_SWAP_X2 : FLAT_X2 <0x00000050, "flat_atomic_swap_x2", []>;
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//def FLAT_ATOMIC_CMPSWAP_X2 : FLAT_X2 <0x00000051, "flat_atomic_cmpswap_x2", []>;
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//def FLAT_ATOMIC_ADD_X2 : FLAT_X2 <0x00000052, "flat_atomic_add_x2", []>;
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//def FLAT_ATOMIC_SUB_X2 : FLAT_X2 <0x00000053, "flat_atomic_sub_x2", []>;
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//def FLAT_ATOMIC_RSUB_X2 : FLAT_X2 <0x00000054, "flat_atomic_rsub_x2", []>;
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//def FLAT_ATOMIC_SMIN_X2 : FLAT_X2 <0x00000055, "flat_atomic_smin_x2", []>;
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//def FLAT_ATOMIC_UMIN_X2 : FLAT_X2 <0x00000056, "flat_atomic_umin_x2", []>;
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//def FLAT_ATOMIC_SMAX_X2 : FLAT_X2 <0x00000057, "flat_atomic_smax_x2", []>;
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//def FLAT_ATOMIC_UMAX_X2 : FLAT_X2 <0x00000058, "flat_atomic_umax_x2", []>;
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//def FLAT_ATOMIC_AND_X2 : FLAT_X2 <0x00000059, "flat_atomic_and_x2", []>;
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//def FLAT_ATOMIC_OR_X2 : FLAT_X2 <0x0000005a, "flat_atomic_or_x2", []>;
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//def FLAT_ATOMIC_XOR_X2 : FLAT_X2 <0x0000005b, "flat_atomic_xor_x2", []>;
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//def FLAT_ATOMIC_INC_X2 : FLAT_X2 <0x0000005c, "flat_atomic_inc_x2", []>;
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//def FLAT_ATOMIC_DEC_X2 : FLAT_X2 <0x0000005d, "flat_atomic_dec_x2", []>;
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//def FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_X2 <0x0000005e, "flat_atomic_fcmpswap_x2", []>;
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//def FLAT_ATOMIC_FMIN_X2 : FLAT_X2 <0x0000005f, "flat_atomic_fmin_x2", []>;
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//def FLAT_ATOMIC_FMAX_X2 : FLAT_X2 <0x00000060, "flat_atomic_fmax_x2", []>;
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} // End SubtargetPredicate = isCIVI
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//===----------------------------------------------------------------------===//
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// Flat Patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [HasFlatAddressSpace] in {
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class FLATLoad_Pattern <FLAT Instr_ADDR64, ValueType vt,
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PatFrag flat_ld> :
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Pat <(vt (flat_ld i64:$ptr)),
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(Instr_ADDR64 $ptr)
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(Instr_ADDR64 $ptr, 0, 0, 0)
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>;
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def : FLATLoad_Pattern <FLAT_LOAD_SBYTE, i32, sextloadi8_flat>;
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@ -138,7 +135,7 @@ def : FLATLoad_Pattern <FLAT_LOAD_DWORDX4, v4i32, flat_load>;
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class FLATStore_Pattern <FLAT Instr, ValueType vt, PatFrag st> :
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Pat <(st vt:$value, i64:$ptr),
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(Instr $value, $ptr)
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(Instr $value, $ptr, 0, 0, 0)
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>;
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def : FLATStore_Pattern <FLAT_STORE_BYTE, i32, truncstorei8_flat>;
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@ -655,6 +655,7 @@ class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let UseNamedOperandTable = 1;
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let hasSideEffects = 0;
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let AsmMatchConverter = "cvtFlat";
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let SchedRW = [WriteVMEM];
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}
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@ -390,27 +390,38 @@ class GDSBaseMatchClass <string parser> : AsmOperandClass {
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def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
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def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
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def GLCMatchClass : AsmOperandClass {
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let Name = "GLC";
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class GLCBaseMatchClass <string parser> : AsmOperandClass {
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let Name = "GLC"#parser;
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let PredicateMethod = "isImm";
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let ParserMethod = "parseMubufOptionalOps";
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let ParserMethod = parser;
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let RenderMethod = "addImmOperands";
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}
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def SLCMatchClass : AsmOperandClass {
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let Name = "SLC";
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def GLCMubufMatchClass : GLCBaseMatchClass <"parseMubufOptionalOps">;
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def GLCFlatMatchClass : GLCBaseMatchClass <"parseFlatOptionalOps">;
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class SLCBaseMatchClass <string parser> : AsmOperandClass {
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let Name = "SLC"#parser;
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let PredicateMethod = "isImm";
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let ParserMethod = "parseMubufOptionalOps";
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let ParserMethod = parser;
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let RenderMethod = "addImmOperands";
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}
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def TFEMatchClass : AsmOperandClass {
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let Name = "TFE";
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def SLCMubufMatchClass : SLCBaseMatchClass <"parseMubufOptionalOps">;
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def SLCFlatMatchClass : SLCBaseMatchClass <"parseFlatOptionalOps">;
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def SLCFlatAtomicMatchClass : SLCBaseMatchClass <"parseFlatAtomicOptionalOps">;
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class TFEBaseMatchClass <string parser> : AsmOperandClass {
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let Name = "TFE"#parser;
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let PredicateMethod = "isImm";
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let ParserMethod = "parseMubufOptionalOps";
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let ParserMethod = parser;
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let RenderMethod = "addImmOperands";
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}
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def TFEMubufMatchClass : TFEBaseMatchClass <"parseMubufOptionalOps">;
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def TFEFlatMatchClass : TFEBaseMatchClass <"parseFlatOptionalOps">;
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def TFEFlatAtomicMatchClass : TFEBaseMatchClass <"parseFlatAtomicOptionalOps">;
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def OModMatchClass : AsmOperandClass {
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let Name = "OMod";
|
||||
let PredicateMethod = "isImm";
|
||||
@ -463,19 +474,32 @@ def gds : gds_base <GDSMatchClass>;
|
||||
|
||||
def gds01 : gds_base <GDS01MatchClass>;
|
||||
|
||||
def glc : Operand <i1> {
|
||||
class glc_base <AsmOperandClass mc> : Operand <i1> {
|
||||
let PrintMethod = "printGLC";
|
||||
let ParserMatchClass = GLCMatchClass;
|
||||
let ParserMatchClass = mc;
|
||||
}
|
||||
def slc : Operand <i1> {
|
||||
|
||||
def glc : glc_base <GLCMubufMatchClass>;
|
||||
def glc_flat : glc_base <GLCFlatMatchClass>;
|
||||
|
||||
class slc_base <AsmOperandClass mc> : Operand <i1> {
|
||||
let PrintMethod = "printSLC";
|
||||
let ParserMatchClass = SLCMatchClass;
|
||||
let ParserMatchClass = mc;
|
||||
}
|
||||
def tfe : Operand <i1> {
|
||||
|
||||
def slc : slc_base <SLCMubufMatchClass>;
|
||||
def slc_flat : slc_base <SLCFlatMatchClass>;
|
||||
def slc_flat_atomic : slc_base <SLCFlatAtomicMatchClass>;
|
||||
|
||||
class tfe_base <AsmOperandClass mc> : Operand <i1> {
|
||||
let PrintMethod = "printTFE";
|
||||
let ParserMatchClass = TFEMatchClass;
|
||||
let ParserMatchClass = mc;
|
||||
}
|
||||
|
||||
def tfe : tfe_base <TFEMubufMatchClass>;
|
||||
def tfe_flat : tfe_base <TFEFlatMatchClass>;
|
||||
def tfe_flat_atomic : tfe_base <TFEFlatAtomicMatchClass>;
|
||||
|
||||
def omod : Operand <i32> {
|
||||
let PrintMethod = "printOModSI";
|
||||
let ParserMatchClass = OModMatchClass;
|
||||
@ -2335,30 +2359,48 @@ multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
|
||||
|
||||
class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
|
||||
FLAT <op, (outs regClass:$vdst),
|
||||
(ins VReg_64:$addr),
|
||||
asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
|
||||
let glc = 0;
|
||||
let slc = 0;
|
||||
let tfe = 0;
|
||||
(ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
|
||||
asm#" $vdst, $addr"#"$glc"#"$slc"#"$tfe", []> {
|
||||
let data = 0;
|
||||
let mayLoad = 1;
|
||||
}
|
||||
|
||||
class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
|
||||
FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
|
||||
name#" $data, $addr, [M0, FLAT_SCRATCH]",
|
||||
FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr,
|
||||
glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
|
||||
name#" $data, $addr"#"$glc"#"$slc"#"$tfe",
|
||||
[]> {
|
||||
|
||||
let mayLoad = 0;
|
||||
let mayStore = 1;
|
||||
|
||||
// Encoding
|
||||
let glc = 0;
|
||||
let slc = 0;
|
||||
let tfe = 0;
|
||||
let vdst = 0;
|
||||
}
|
||||
|
||||
multiclass FLAT_ATOMIC <bits<7> op, string name, RegisterClass vdst_rc,
|
||||
RegisterClass data_rc = vdst_rc> {
|
||||
|
||||
let mayLoad = 1, mayStore = 1 in {
|
||||
def "" : FLAT <op, (outs),
|
||||
(ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
|
||||
tfe_flat_atomic:$tfe),
|
||||
name#" $addr, $data"#"$slc"#"$tfe", []>,
|
||||
AtomicNoRet <NAME, 0> {
|
||||
let glc = 0;
|
||||
let vdst = 0;
|
||||
}
|
||||
|
||||
def _RTN : FLAT <op, (outs vdst_rc:$vdst),
|
||||
(ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
|
||||
tfe_flat_atomic:$tfe),
|
||||
name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>,
|
||||
AtomicNoRet <NAME, 1> {
|
||||
let glc = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
class MIMG_Mask <string op, int channels> {
|
||||
string Op = op;
|
||||
int Channels = channels;
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
|
||||
|
||||
; CHECK-LABEL: {{^}}branch_use_flat_i32:
|
||||
; CHECK: flat_store_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, [M0, FLAT_SCRATCH]
|
||||
; CHECK: flat_store_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
|
||||
; CHECK: s_endpgm
|
||||
define void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 {
|
||||
entry:
|
||||
|
||||
477
test/MC/R600/flat.s
Normal file
477
test/MC/R600/flat.s
Normal file
@ -0,0 +1,477 @@
|
||||
// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CIVI --check-prefix=CI
|
||||
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=CIVI
|
||||
|
||||
// FIXME: These instructions give an 'invalid operand' error on SI and should
|
||||
// instead be reporting an 'instruction not supported' error.
|
||||
|
||||
// XUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=NOVI
|
||||
// XUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI
|
||||
// XUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Operands
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
flat_load_dword v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] glc slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] glc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] glc slc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] glc tfe slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] slc glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] slc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] slc glc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] slc tfe glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] tfe glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] tfe slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] tfe glc slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] tfe slc glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_store_dword v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] glc slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] glc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] glc slc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] glc tfe slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] slc glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] slc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] slc glc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] slc tfe glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] tfe glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] tfe slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] tfe glc slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] tfe slc glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
// FIXME: For atomic instructions, glc must be placed immediately following
|
||||
// the data regiser. These forms aren't currently supported:
|
||||
// flat_atomic_add v1, v[3:4], v5 slc glc
|
||||
// flat_atomic_add v1, v[3:4], v5 slc glc tfe
|
||||
// flat_atomic_add v1, v[3:4], v5 slc tfe glc
|
||||
// flat_atomic_add v1, v[3:4], v5 tfe glc
|
||||
// flat_atomic_add v[3:4], v5 tfe glc
|
||||
// flat_atomic_add v1, v[3:4], v5 tfe glc slc
|
||||
// flat_atomic_add v1, v[3:4], v5 tfe slc glc
|
||||
|
||||
flat_atomic_add v1 v[3:4], v5 glc slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_add v1 v[3:4], v5 glc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v1, v[3:4], v5 glc tfe ; encoding: [0x00,0x00,0xc9,0xdc,0x03,0x05,0x80,0x01]
|
||||
|
||||
flat_atomic_add v1 v[3:4], v5 glc slc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x80,0x01]
|
||||
|
||||
flat_atomic_add v1 v[3:4], v5 glc tfe slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x80,0x01]
|
||||
|
||||
flat_atomic_add v[3:4], v5 slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v[3:4], v5 slc ; encoding: [0x00,0x00,0xca,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_add v[3:4], v5 slc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v[3:4], v5 slc tfe ; encoding: [0x00,0x00,0xca,0xdc,0x03,0x05,0x80,0x00]
|
||||
|
||||
flat_atomic_add v[3:4], v5 tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v[3:4], v5 tfe ; encoding: [0x00,0x00,0xc8,0xdc,0x03,0x05,0x80,0x00]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
flat_load_ubyte v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_ubyte v1, v[3:4] ; encoding: [0x00,0x00,0x20,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_sbyte v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_sbyte v1, v[3:4] ; encoding: [0x00,0x00,0x24,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_ushort v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_ushort v1, v[3:4] ; encoding: [0x00,0x00,0x28,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_sshort v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_sshort v1, v[3:4] ; encoding: [0x00,0x00,0x2c,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dwordx2 v[1:2], v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dwordx2 v[1:2], v[3:4] ; encoding: [0x00,0x00,0x34,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dwordx4 v[5:8], v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dwordx4 v[5:8], v[3:4] ; encoding: [0x00,0x00,0x38,0xdc,0x03,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx3 v[5:7], v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dwordx3 v[5:7], v[3:4] ; encoding: [0x00,0x00,0x3c,0xdc,0x03,0x00,0x00,0x05]
|
||||
|
||||
flat_store_byte v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_byte v1, v[3:4] ; encoding: [0x00,0x00,0x60,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_short v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_short v1, v[3:4] ; encoding: [0x00,0x00,0x68,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dword v1, v[3:4] ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dwordx2 v[1:2], v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dwordx2 v[1:2], v[3:4] ; encoding: [0x00,0x00,0x74,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dwordx4 v[5:8], v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dwordx4 v[5:8], v[3:4] ; encoding: [0x00,0x00,0x78,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_store_dwordx3 v[5:7], v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dwordx3 v[5:7], v[3:4] ; encoding: [0x00,0x00,0x7c,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_swap v[3:4], v5 ; encoding: [0x00,0x00,0xc0,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_swap v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xc1,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_cmpswap v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_cmpswap v[3:4], v[5:6] ; encoding: [0x00,0x00,0xc4,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap v1, v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_cmpswap v1, v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0xc5,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_add v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v[3:4], v5 ; encoding: [0x00,0x00,0xc8,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_add v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xc9,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_sub v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_sub v[3:4], v5 ; encoding: [0x00,0x00,0xcc,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_sub v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_sub v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xcd,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_smin v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smin v[3:4], v5 ; encoding: [0x00,0x00,0xd4,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_smin v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xd5,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_umin v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umin v[3:4], v5 ; encoding: [0x00,0x00,0xd8,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_umin v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xd9,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_smax v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smax v[3:4], v5 ; encoding: [0x00,0x00,0xdc,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_smax v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smax v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xdd,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_umax v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umax v[3:4], v5 ; encoding: [0x00,0x00,0xe0,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_umax v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umax v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe1,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_and v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_and v[3:4], v5 ; encoding: [0x00,0x00,0xe4,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_and v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_and v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe5,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_or v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_or v[3:4], v5 ; encoding: [0x00,0x00,0xe8,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_or v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_or v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe9,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_xor v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_xor v[3:4], v5 ; encoding: [0x00,0x00,0xec,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_xor v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_xor v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xed,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_inc v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_inc v[3:4], v5 ; encoding: [0x00,0x00,0xf0,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_inc v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_inc v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xf1,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_dec v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_dec v[3:4], v5 ; encoding: [0x00,0x00,0xf4,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_dec v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_dec v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xf5,0xdc,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_swap_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_swap_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x40,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_swap_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_swap_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x41,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[3:4], v[5:8]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_cmpswap_x2 v[3:4], v[5:8] ; encoding: [0x00,0x00,0x44,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[1:2], v[3:4], v[5:8] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_cmpswap_x2 v[1:2], v[3:4], v[5:8] glc ; encoding: [0x00,0x00,0x45,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_add_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x48,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_add_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x49,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_sub_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_sub_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x4c,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_sub_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_sub_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x4d,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_smin_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x54,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_smin_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x55,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_umin_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x58,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x59,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_smax_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x5c,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_smax_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x5d,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_umax_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x60,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_umax_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x61,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_and_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_and_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x64,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_and_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_and_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x65,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_or_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_or_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x68,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_or_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_or_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x69,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_xor_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_xor_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x6c,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_xor_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_xor_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x6d,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_inc_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_inc_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x70,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_inc_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_inc_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x71,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_dec_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_dec_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x74,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_dec_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_dec_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x75,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_fcmpswap_x2 v[3:4], v[5:8]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CI: flat_atomic_fcmpswap_x2 v[3:4], v[5:8] ; encoding: [0x00,0x00,0x78,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
|
||||
flat_atomic_fcmpswap_x2 v[1:2], v[3:4], v[5:8] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CI: flat_atomic_fcmpswap_x2 v[1:2], v[3:4], v[5:8] glc ; encoding: [0x00,0x00,0x79,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
|
||||
flat_atomic_fmin_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CI: flat_atomic_fmin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x7c,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
|
||||
flat_atomic_fmin_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CI: flat_atomic_fmin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x7d,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
|
||||
flat_atomic_fmax_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CI: flat_atomic_fmax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x80,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
|
||||
flat_atomic_fmax_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CI: flat_atomic_fmax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x81,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
Loading…
Reference in New Issue
Block a user