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[VE] Add lvm/svm intrinsic instructions
Add lvm/svm intrinsic instructions and a regression test. Change RegisterInfo to specify that VM0/VMP0 are constant and reserved registers. This modifies a vst regression test, so update it. Also add pseudo instructions for VM512 register classes and mechanism to expand them after register allocation. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D91541
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@ -84,3 +84,7 @@ let TargetPrefix = "ve" in def int_ve_vl_lsv_vvss : GCCBuiltin<"__builtin_ve_vl_
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let TargetPrefix = "ve" in def int_ve_vl_lvsl_svs : GCCBuiltin<"__builtin_ve_vl_lvsl_svs">, Intrinsic<[LLVMType<i64>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
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let TargetPrefix = "ve" in def int_ve_vl_lvsd_svs : GCCBuiltin<"__builtin_ve_vl_lvsd_svs">, Intrinsic<[LLVMType<f64>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
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let TargetPrefix = "ve" in def int_ve_vl_lvss_svs : GCCBuiltin<"__builtin_ve_vl_lvss_svs">, Intrinsic<[LLVMType<f32>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
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let TargetPrefix = "ve" in def int_ve_vl_lvm_mmss : GCCBuiltin<"__builtin_ve_vl_lvm_mmss">, Intrinsic<[LLVMType<v256i1>], [LLVMType<v256i1>, LLVMType<i64>, LLVMType<i64>], [IntrNoMem]>;
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let TargetPrefix = "ve" in def int_ve_vl_lvm_MMss : GCCBuiltin<"__builtin_ve_vl_lvm_MMss">, Intrinsic<[LLVMType<v512i1>], [LLVMType<v512i1>, LLVMType<i64>, LLVMType<i64>], [IntrNoMem]>;
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let TargetPrefix = "ve" in def int_ve_vl_svm_sms : GCCBuiltin<"__builtin_ve_vl_svm_sms">, Intrinsic<[LLVMType<i64>], [LLVMType<v256i1>, LLVMType<i64>], [IntrNoMem]>;
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let TargetPrefix = "ve" in def int_ve_vl_svm_sMs : GCCBuiltin<"__builtin_ve_vl_svm_sMs">, Intrinsic<[LLVMType<i64>], [LLVMType<v512i1>, LLVMType<i64>], [IntrNoMem]>;
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@ -717,6 +717,12 @@ Register VEInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
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return GlobalBaseReg;
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}
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static Register getVM512Upper(Register reg) {
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return (reg - VE::VMP0) * 2 + VE::VM0;
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}
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static Register getVM512Lower(Register reg) { return getVM512Upper(reg) + 1; }
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bool VEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case VE::EXTEND_STACK: {
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@ -729,6 +735,84 @@ bool VEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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case VE::GETSTACKTOP: {
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return expandGetStackTopPseudo(MI);
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}
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case VE::LVMyir:
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case VE::LVMyim:
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case VE::LVMyir_y:
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case VE::LVMyim_y: {
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Register VMXu = getVM512Upper(MI.getOperand(0).getReg());
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Register VMXl = getVM512Lower(MI.getOperand(0).getReg());
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int64_t Imm = MI.getOperand(1).getImm();
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bool IsSrcReg =
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MI.getOpcode() == VE::LVMyir || MI.getOpcode() == VE::LVMyir_y;
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Register Src = IsSrcReg ? MI.getOperand(2).getReg() : VE::NoRegister;
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int64_t MImm = IsSrcReg ? 0 : MI.getOperand(2).getImm();
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bool KillSrc = IsSrcReg ? MI.getOperand(2).isKill() : false;
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Register VMX = VMXl;
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if (Imm >= 4) {
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VMX = VMXu;
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Imm -= 4;
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}
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MachineBasicBlock *MBB = MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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switch (MI.getOpcode()) {
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case VE::LVMyir:
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BuildMI(*MBB, MI, DL, get(VE::LVMir))
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.addDef(VMX)
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.addImm(Imm)
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.addReg(Src, getKillRegState(KillSrc));
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break;
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case VE::LVMyim:
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BuildMI(*MBB, MI, DL, get(VE::LVMim))
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.addDef(VMX)
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.addImm(Imm)
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.addImm(MImm);
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break;
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case VE::LVMyir_y:
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assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() &&
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"LVMyir_y has different register in 3rd operand");
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BuildMI(*MBB, MI, DL, get(VE::LVMir_m))
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.addDef(VMX)
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.addImm(Imm)
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.addReg(Src, getKillRegState(KillSrc))
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.addReg(VMX);
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break;
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case VE::LVMyim_y:
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assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() &&
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"LVMyim_y has different register in 3rd operand");
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BuildMI(*MBB, MI, DL, get(VE::LVMim_m))
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.addDef(VMX)
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.addImm(Imm)
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.addImm(MImm)
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.addReg(VMX);
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break;
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}
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MI.eraseFromParent();
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return true;
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}
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case VE::SVMyi: {
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Register Dest = MI.getOperand(0).getReg();
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Register VMZu = getVM512Upper(MI.getOperand(1).getReg());
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Register VMZl = getVM512Lower(MI.getOperand(1).getReg());
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bool KillSrc = MI.getOperand(1).isKill();
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int64_t Imm = MI.getOperand(2).getImm();
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Register VMZ = VMZl;
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if (Imm >= 4) {
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VMZ = VMZu;
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Imm -= 4;
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}
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MachineBasicBlock *MBB = MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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MachineInstrBuilder MIB =
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BuildMI(*MBB, MI, DL, get(VE::SVMmi), Dest).addReg(VMZ).addImm(Imm);
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MachineInstr *Inst = MIB.getInstr();
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MI.eraseFromParent();
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if (KillSrc) {
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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Inst->addRegisterKilled(MI.getOperand(1).getReg(), TRI, true);
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}
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return true;
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}
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}
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return false;
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}
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@ -162,3 +162,7 @@ def : Pat<(int_ve_vl_pfchv_ssl i64:$sy, i64:$sz, i32:$vl), (PFCHVrrl i64:$sy, i6
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def : Pat<(int_ve_vl_pfchv_ssl simm7:$I, i64:$sz, i32:$vl), (PFCHVirl (LO7 $I), i64:$sz, i32:$vl)>;
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def : Pat<(int_ve_vl_pfchvnc_ssl i64:$sy, i64:$sz, i32:$vl), (PFCHVNCrrl i64:$sy, i64:$sz, i32:$vl)>;
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def : Pat<(int_ve_vl_pfchvnc_ssl simm7:$I, i64:$sz, i32:$vl), (PFCHVNCirl (LO7 $I), i64:$sz, i32:$vl)>;
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def : Pat<(int_ve_vl_lvm_mmss v256i1:$ptm, uimm6:$N, i64:$sz), (LVMir_m (ULO7 $N), i64:$sz, v256i1:$ptm)>;
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def : Pat<(int_ve_vl_lvm_MMss v512i1:$ptm, uimm6:$N, i64:$sz), (LVMyir_y (ULO7 $N), i64:$sz, v512i1:$ptm)>;
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def : Pat<(int_ve_vl_svm_sms v256i1:$vmz, uimm6:$N), (SVMmi v256i1:$vmz, (ULO7 $N))>;
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def : Pat<(int_ve_vl_svm_sMs v512i1:$vmz, uimm6:$N), (SVMyi v512i1:$vmz, (ULO7 $N))>;
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@ -2,6 +2,26 @@
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// Vector Instructions
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//===----------------------------------------------------------------------===//
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// Pseudo instructions for VM512 modifications
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//
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// Specifies hasSideEffects = 0 to disable UnmodeledSideEffects.
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let hasSideEffects = 0 in {
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let Constraints = "$vx = $vd", DisableEncoding = "$vd" in {
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def LVMyir_y : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, I64:$sz, VM512:$vd),
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"# pseudo LVM $vx, $sy, $sz, $vd">;
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def LVMyim_y : Pseudo<(outs VM512:$vx),
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(ins uimm3:$sy, mimm:$sz, VM512:$vd),
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"# pseudo LVM $vx, $sy, $sz, $vd">;
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}
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def LVMyir : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, I64:$sz),
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"# pseudo LVM $vx, $sy, $sz">;
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def LVMyim : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, mimm:$sz),
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"# pseudo LVM $vx, $sy, $sz">;
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def SVMyi : Pseudo<(outs I64:$sx), (ins VM512:$vz, uimm3:$sy),
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"# pseudo SVM $sx, $vz, $sy">;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//
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@ -86,10 +86,22 @@ BitVector VERegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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++ItAlias)
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Reserved.set(*ItAlias);
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// Reserve constant registers.
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Reserved.set(VE::VM0);
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Reserved.set(VE::VMP0);
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return Reserved;
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}
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bool VERegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { return false; }
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bool VERegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
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switch (PhysReg) {
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case VE::VM0:
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case VE::VMP0:
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return true;
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default:
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return false;
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}
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}
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const TargetRegisterClass *
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VERegisterInfo::getPointerRegClass(const MachineFunction &MF,
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46
test/CodeGen/VE/VELIntrinsics/lvm.ll
Normal file
46
test/CodeGen/VE/VELIntrinsics/lvm.ll
Normal file
@ -0,0 +1,46 @@
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; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test load/save vector mask intrinsic instructions
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;;;
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;;; Note:
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;;; We test LVMir_m, LVMyir_y, SVMmi, and SVMyi instructions.
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; Function Attrs: nounwind readnone
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define i64 @lvm_mmss(i8* nocapture readnone %0, i64 %1) {
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; CHECK-LABEL: lvm_mmss:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lvm %vm1, 3, %s1
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; CHECK-NEXT: svm %s0, %vm1, 3
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call <256 x i1> @llvm.ve.vl.lvm.mmss(<256 x i1> undef, i64 3, i64 %1)
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%4 = tail call i64 @llvm.ve.vl.svm.sms(<256 x i1> %3, i64 3)
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ret i64 %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x i1> @llvm.ve.vl.lvm.mmss(<256 x i1>, i64, i64)
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; Function Attrs: nounwind readnone
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declare i64 @llvm.ve.vl.svm.sms(<256 x i1>, i64)
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; Function Attrs: nounwind readnone
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define i64 @lvml_MMss(i8* nocapture readnone %0, i64 %1) {
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; CHECK-LABEL: lvml_MMss:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lvm %vm2, 1, %s1
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; CHECK-NEXT: svm %s0, %vm3, 3
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; CHECK-NEXT: svm %s1, %vm2, 2
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; CHECK-NEXT: adds.l %s0, %s1, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call <512 x i1> @llvm.ve.vl.lvm.MMss(<512 x i1> undef, i64 5, i64 %1)
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%4 = tail call i64 @llvm.ve.vl.svm.sMs(<512 x i1> %3, i64 3)
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%5 = tail call i64 @llvm.ve.vl.svm.sMs(<512 x i1> %3, i64 6)
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%6 = add i64 %5, %4
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ret i64 %6
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}
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; Function Attrs: nounwind readnone
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declare <512 x i1> @llvm.ve.vl.lvm.MMss(<512 x i1>, i64, i64)
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; Function Attrs: nounwind readnone
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declare i64 @llvm.ve.vl.svm.sMs(<512 x i1>, i64)
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@ -32,7 +32,7 @@ define void @vst_vssml(i8* %0, i64 %1) {
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vld %v0, %s1, %s0
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; CHECK-NEXT: vst %v0, %s1, %s0, %vm0
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; CHECK-NEXT: vst %v0, %s1, %s0, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
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tail call void @llvm.ve.vl.vst.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
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@ -63,7 +63,7 @@ define void @vst_vssml_imm(i8* %0) {
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: vst %v0, 8, %s0, %vm0
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; CHECK-NEXT: vst %v0, 8, %s0, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
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tail call void @llvm.ve.vl.vst.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
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@ -94,7 +94,7 @@ define void @vstnc_vssml(i8* %0, i64 %1) {
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vld %v0, %s1, %s0
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; CHECK-NEXT: vst.nc %v0, %s1, %s0, %vm0
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; CHECK-NEXT: vst.nc %v0, %s1, %s0, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
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tail call void @llvm.ve.vl.vstnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
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@ -125,7 +125,7 @@ define void @vstnc_vssml_imm(i8* %0) {
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: vst.nc %v0, 8, %s0, %vm0
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; CHECK-NEXT: vst.nc %v0, 8, %s0, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
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tail call void @llvm.ve.vl.vstnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
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@ -156,7 +156,7 @@ define void @vstot_vssml(i8* %0, i64 %1) {
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vld %v0, %s1, %s0
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; CHECK-NEXT: vst.ot %v0, %s1, %s0, %vm0
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; CHECK-NEXT: vst.ot %v0, %s1, %s0, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
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tail call void @llvm.ve.vl.vstot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
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@ -187,7 +187,7 @@ define void @vstot_vssml_imm(i8* %0) {
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: vst.ot %v0, 8, %s0, %vm0
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; CHECK-NEXT: vst.ot %v0, 8, %s0, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
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tail call void @llvm.ve.vl.vstot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
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@ -218,7 +218,7 @@ define void @vstncot_vssml(i8* %0, i64 %1) {
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vld %v0, %s1, %s0
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; CHECK-NEXT: vst.nc.ot %v0, %s1, %s0, %vm0
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; CHECK-NEXT: vst.nc.ot %v0, %s1, %s0, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
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tail call void @llvm.ve.vl.vstncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
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@ -249,7 +249,7 @@ define void @vstncot_vssml_imm(i8* %0) {
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: vst.nc.ot %v0, 8, %s0, %vm0
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; CHECK-NEXT: vst.nc.ot %v0, 8, %s0, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
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tail call void @llvm.ve.vl.vstncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
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@ -280,7 +280,7 @@ define void @vstu_vssml(i8* %0, i64 %1) {
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vld %v0, %s1, %s0
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; CHECK-NEXT: vstu %v0, %s1, %s0, %vm0
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; CHECK-NEXT: vstu %v0, %s1, %s0, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
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tail call void @llvm.ve.vl.vstu.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
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@ -311,7 +311,7 @@ define void @vstu_vssml_imm(i8* %0) {
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: vstu %v0, 8, %s0, %vm0
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; CHECK-NEXT: vstu %v0, 8, %s0, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstu.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -342,7 +342,7 @@ define void @vstunc_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstu.nc %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstu.nc %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstunc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -373,7 +373,7 @@ define void @vstunc_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstu.nc %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstu.nc %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstunc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -404,7 +404,7 @@ define void @vstuot_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstu.ot %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstu.ot %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstuot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -435,7 +435,7 @@ define void @vstuot_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstu.ot %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstu.ot %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstuot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -466,7 +466,7 @@ define void @vstuncot_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstu.nc.ot %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstu.nc.ot %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstuncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -497,7 +497,7 @@ define void @vstuncot_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstu.nc.ot %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstu.nc.ot %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstuncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -528,7 +528,7 @@ define void @vstl_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstl %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstl %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstl.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -559,7 +559,7 @@ define void @vstl_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstl %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstl %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstl.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -590,7 +590,7 @@ define void @vstlnc_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstl.nc %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstl.nc %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstlnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -621,7 +621,7 @@ define void @vstlnc_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstl.nc %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstl.nc %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstlnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -652,7 +652,7 @@ define void @vstlot_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstl.ot %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstl.ot %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstlot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -683,7 +683,7 @@ define void @vstlot_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstl.ot %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstl.ot %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstlot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -714,7 +714,7 @@ define void @vstlncot_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstl.nc.ot %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstl.nc.ot %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstlncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -745,7 +745,7 @@ define void @vstlncot_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstl.nc.ot %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstl.nc.ot %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstlncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -776,7 +776,7 @@ define void @vst2d_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vst2d %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vst2d %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vst2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -807,7 +807,7 @@ define void @vst2d_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vst2d %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vst2d %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vst2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -838,7 +838,7 @@ define void @vst2dnc_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vst2d.nc %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vst2d.nc %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vst2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -869,7 +869,7 @@ define void @vst2dnc_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vst2d.nc %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vst2d.nc %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vst2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -900,7 +900,7 @@ define void @vst2dot_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vst2d.ot %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vst2d.ot %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vst2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -931,7 +931,7 @@ define void @vst2dot_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vst2d.ot %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vst2d.ot %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vst2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -962,7 +962,7 @@ define void @vst2dncot_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vst2d.nc.ot %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vst2d.nc.ot %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vst2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -993,7 +993,7 @@ define void @vst2dncot_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vst2d.nc.ot %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vst2d.nc.ot %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vst2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1024,7 +1024,7 @@ define void @vstu2d_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstu2d %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstu2d %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstu2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1055,7 +1055,7 @@ define void @vstu2d_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstu2d %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstu2d %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstu2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1086,7 +1086,7 @@ define void @vstu2dnc_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstu2d.nc %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstu2d.nc %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstu2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1117,7 +1117,7 @@ define void @vstu2dnc_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstu2d.nc %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstu2d.nc %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstu2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1148,7 +1148,7 @@ define void @vstu2dot_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstu2d.ot %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstu2d.ot %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstu2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1179,7 +1179,7 @@ define void @vstu2dot_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstu2d.ot %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstu2d.ot %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstu2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1210,7 +1210,7 @@ define void @vstu2dncot_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstu2d.nc.ot %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstu2d.nc.ot %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstu2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1241,7 +1241,7 @@ define void @vstu2dncot_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstu2d.nc.ot %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstu2d.nc.ot %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstu2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1272,7 +1272,7 @@ define void @vstl2d_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstl2d %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstl2d %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstl2d.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1303,7 +1303,7 @@ define void @vstl2d_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstl2d %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstl2d %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstl2d.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1334,7 +1334,7 @@ define void @vstl2dnc_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstl2d.nc %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstl2d.nc %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstl2dnc.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1365,7 +1365,7 @@ define void @vstl2dnc_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstl2d.nc %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstl2d.nc %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstl2dnc.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1396,7 +1396,7 @@ define void @vstl2dot_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstl2d.ot %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstl2d.ot %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstl2dot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1427,7 +1427,7 @@ define void @vstl2dot_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstl2d.ot %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstl2d.ot %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstl2dot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1458,7 +1458,7 @@ define void @vstl2dncot_vssml(i8* %0, i64 %1) {
|
||||
; CHECK-NEXT: lea %s2, 256
|
||||
; CHECK-NEXT: lvl %s2
|
||||
; CHECK-NEXT: vld %v0, %s1, %s0
|
||||
; CHECK-NEXT: vstl2d.nc.ot %v0, %s1, %s0, %vm0
|
||||
; CHECK-NEXT: vstl2d.nc.ot %v0, %s1, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 %1, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstl2dncot.vssml(<256 x double> %3, i64 %1, i8* %0, <256 x i1> undef, i32 256)
|
||||
@ -1489,7 +1489,7 @@ define void @vstl2dncot_vssml_imm(i8* %0) {
|
||||
; CHECK-NEXT: lea %s1, 256
|
||||
; CHECK-NEXT: lvl %s1
|
||||
; CHECK-NEXT: vld %v0, 8, %s0
|
||||
; CHECK-NEXT: vstl2d.nc.ot %v0, 8, %s0, %vm0
|
||||
; CHECK-NEXT: vstl2d.nc.ot %v0, 8, %s0, %vm1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, i8* %0, i32 256)
|
||||
tail call void @llvm.ve.vl.vstl2dncot.vssml(<256 x double> %2, i64 8, i8* %0, <256 x i1> undef, i32 256)
|
||||
|
Loading…
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Reference in New Issue
Block a user