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[InstCombine] Add testcases for (mul (sext x), cst) --> (sext (mul x, cst')) and (mul (zext x), cst) --> (zext (mul x, cst')) for vectors constants.
If the multiply won't overflow in the original type we can use a smaller mul and sign extend afterwards. We don't currently support this for vector constants. llvm-svn: 341884
This commit is contained in:
Craig Topper
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2b90ef6c05
@ -198,4 +198,134 @@ define <2 x i64> @test7_vec(<2 x i32> %V) {
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ret <2 x i64> %add
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}
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define i64 @test8(i32 %V) {
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; CHECK-LABEL: @test8(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[V:%.*]], 16
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; CHECK-NEXT: [[MULCONV:%.*]] = mul nsw i32 [[ASHR]], 32767
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; CHECK-NEXT: [[MUL:%.*]] = sext i32 [[MULCONV]] to i64
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; CHECK-NEXT: ret i64 [[MUL]]
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;
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%ashr = ashr i32 %V, 16
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%sext = sext i32 %ashr to i64
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%mul = mul i64 %sext, 32767
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ret i64 %mul
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}
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define <2 x i64> @test8_splat(<2 x i32> %V) {
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; CHECK-LABEL: @test8_splat(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 16, i32 16>
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; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw <2 x i64> [[SEXT]], <i64 32767, i64 32767>
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; CHECK-NEXT: ret <2 x i64> [[MUL]]
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;
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%ashr = ashr <2 x i32> %V, <i32 16, i32 16>
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%sext = sext <2 x i32> %ashr to <2 x i64>
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%mul = mul <2 x i64> %sext, <i64 32767, i64 32767>
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ret <2 x i64> %mul
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}
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define <2 x i64> @test8_vec(<2 x i32> %V) {
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; CHECK-LABEL: @test8_vec(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 16, i32 16>
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; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw <2 x i64> [[SEXT]], <i64 32767, i64 16384>
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; CHECK-NEXT: ret <2 x i64> [[MUL]]
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;
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%ashr = ashr <2 x i32> %V, <i32 16, i32 16>
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%sext = sext <2 x i32> %ashr to <2 x i64>
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%mul = mul <2 x i64> %sext, <i64 32767, i64 16384>
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ret <2 x i64> %mul
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}
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define <2 x i64> @test8_vec2(<2 x i32> %V) {
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; CHECK-LABEL: @test8_vec2(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 16, i32 16>
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; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw <2 x i64> [[SEXT]], <i64 32767, i64 -32767>
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; CHECK-NEXT: ret <2 x i64> [[MUL]]
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;
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%ashr = ashr <2 x i32> %V, <i32 16, i32 16>
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%sext = sext <2 x i32> %ashr to <2 x i64>
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%mul = mul <2 x i64> %sext, <i64 32767, i64 -32767>
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ret <2 x i64> %mul
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}
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define i64 @test9(i32 %V) {
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; CHECK-LABEL: @test9(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[V:%.*]], 16
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; CHECK-NEXT: [[MULCONV:%.*]] = mul nsw i32 [[ASHR]], -32767
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; CHECK-NEXT: [[MUL:%.*]] = sext i32 [[MULCONV]] to i64
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; CHECK-NEXT: ret i64 [[MUL]]
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;
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%ashr = ashr i32 %V, 16
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%sext = sext i32 %ashr to i64
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%mul = mul i64 %sext, -32767
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ret i64 %mul
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}
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define <2 x i64> @test9_splat(<2 x i32> %V) {
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; CHECK-LABEL: @test9_splat(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 16, i32 16>
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; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw <2 x i64> [[SEXT]], <i64 -32767, i64 -32767>
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; CHECK-NEXT: ret <2 x i64> [[MUL]]
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;
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%ashr = ashr <2 x i32> %V, <i32 16, i32 16>
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%sext = sext <2 x i32> %ashr to <2 x i64>
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%mul = mul <2 x i64> %sext, <i64 -32767, i64 -32767>
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ret <2 x i64> %mul
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}
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define <2 x i64> @test9_vec(<2 x i32> %V) {
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; CHECK-LABEL: @test9_vec(
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; CHECK-NEXT: [[ASHR:%.*]] = ashr <2 x i32> [[V:%.*]], <i32 16, i32 16>
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; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i32> [[ASHR]] to <2 x i64>
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw <2 x i64> [[SEXT]], <i64 -32767, i64 -10>
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; CHECK-NEXT: ret <2 x i64> [[MUL]]
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;
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%ashr = ashr <2 x i32> %V, <i32 16, i32 16>
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%sext = sext <2 x i32> %ashr to <2 x i64>
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%mul = mul <2 x i64> %sext, <i64 -32767, i64 -10>
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ret <2 x i64> %mul
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}
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define i64 @test10(i32 %V) {
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; CHECK-LABEL: @test10(
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; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[V:%.*]], 16
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; CHECK-NEXT: [[MULCONV:%.*]] = mul nuw i32 [[LSHR]], 65535
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; CHECK-NEXT: [[MUL:%.*]] = zext i32 [[MULCONV]] to i64
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; CHECK-NEXT: ret i64 [[MUL]]
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;
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%lshr = lshr i32 %V, 16
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%zext = zext i32 %lshr to i64
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%mul = mul i64 %zext, 65535
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ret i64 %mul
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}
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define <2 x i64> @test10_splat(<2 x i32> %V) {
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; CHECK-LABEL: @test10_splat(
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; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i32> [[V:%.*]], <i32 16, i32 16>
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; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[LSHR]] to <2 x i64>
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; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw <2 x i64> [[ZEXT]], <i64 65535, i64 65535>
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; CHECK-NEXT: ret <2 x i64> [[MUL]]
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;
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%lshr = lshr <2 x i32> %V, <i32 16, i32 16>
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%zext = zext <2 x i32> %lshr to <2 x i64>
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%mul = mul <2 x i64> %zext, <i64 65535, i64 65535>
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ret <2 x i64> %mul
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}
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define <2 x i64> @test10_vec(<2 x i32> %V) {
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; CHECK-LABEL: @test10_vec(
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; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i32> [[V:%.*]], <i32 16, i32 16>
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; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i32> [[LSHR]] to <2 x i64>
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; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw <2 x i64> [[ZEXT]], <i64 65535, i64 2>
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; CHECK-NEXT: ret <2 x i64> [[MUL]]
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;
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%lshr = lshr <2 x i32> %V, <i32 16, i32 16>
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%zext = zext <2 x i32> %lshr to <2 x i64>
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%mul = mul <2 x i64> %zext, <i64 65535, i64 2>
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ret <2 x i64> %mul
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}
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!0 = !{ i32 0, i32 2000 }
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