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[MachineSink] Use the real post dominator tree
Summary: Fixes a FIXME in MachineSinking. Instead of using the simple heuristics in isPostDominatedBy, use the real MachinePostDominatorTree. The old heuristics caused instructions to sink unnecessarily, and might create register pressure. Test Plan: Added a NVPTX codegen test to verify that our change is in effect. It also shows the unnecessary register pressure caused by over-sinking. Updated affected tests in AArch64 and X86. Reviewers: eliben, meheff, Jiangning Reviewed By: Jiangning Subscribers: jholewinski, aemerson, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D4814 llvm-svn: 216862
This commit is contained in:
Jingyue Wu
parent
836d1e85c7
commit
2b97db6061
@ -23,6 +23,7 @@
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachinePostDominators.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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@ -48,8 +49,9 @@ namespace {
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class MachineSinking : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI; // Machine register information
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MachineDominatorTree *DT; // Machine dominator tree
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MachineRegisterInfo *MRI; // Machine register information
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MachineDominatorTree *DT; // Machine dominator tree
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MachinePostDominatorTree *PDT; // Machine post dominator tree
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MachineLoopInfo *LI;
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AliasAnalysis *AA;
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@ -74,8 +76,10 @@ namespace {
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.addRequired<AliasAnalysis>();
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<MachinePostDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addPreserved<MachinePostDominatorTree>();
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AU.addPreserved<MachineLoopInfo>();
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}
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@ -236,6 +240,7 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
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TRI = TM.getSubtargetImpl()->getRegisterInfo();
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MRI = &MF.getRegInfo();
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DT = &getAnalysis<MachineDominatorTree>();
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PDT = &getAnalysis<MachinePostDominatorTree>();
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LI = &getAnalysis<MachineLoopInfo>();
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AA = &getAnalysis<AliasAnalysis>();
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@ -453,23 +458,6 @@ static void collectDebugValues(MachineInstr *MI,
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}
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}
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/// isPostDominatedBy - Return true if A is post dominated by B.
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static bool isPostDominatedBy(MachineBasicBlock *A, MachineBasicBlock *B) {
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// FIXME - Use real post dominator.
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if (A->succ_size() != 2)
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return false;
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MachineBasicBlock::succ_iterator I = A->succ_begin();
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if (B == *I)
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++I;
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MachineBasicBlock *OtherSuccBlock = *I;
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if (OtherSuccBlock->succ_size() != 1 ||
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*(OtherSuccBlock->succ_begin()) != B)
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return false;
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return true;
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}
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/// isProfitableToSinkTo - Return true if it is profitable to sink MI.
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bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
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MachineBasicBlock *MBB,
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@ -481,8 +469,8 @@ bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
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return false;
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// It is profitable if SuccToSinkTo does not post dominate current block.
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if (!isPostDominatedBy(MBB, SuccToSinkTo))
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return true;
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if (!PDT->dominates(SuccToSinkTo, MBB))
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return true;
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// Check if only use in post dominated block is PHI instruction.
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bool NonPHIUse = false;
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@ -47,13 +47,13 @@ define i32 @fetch_and_nand(i32* %p) {
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define i64 @fetch_and_nand_64(i64* %p) {
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; CHECK-LABEL: fetch_and_nand_64:
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; CHECK: mov x[[ADDR:[0-9]+]], x0
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x[[ADDR]]]
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; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x0]
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; CHECK: mvn w[[TMP_REG:[0-9]+]], w[[DEST_REG]]
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; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], x[[TMP_REG]], #0xfffffffffffffff8
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; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
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; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
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; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
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; CHECK: mov x0, x[[DEST_REG]]
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%val = atomicrmw nand i64* %p, i64 7 acq_rel
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ret i64 %val
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@ -75,12 +75,12 @@ define i32 @fetch_and_or(i32* %p) {
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define i64 @fetch_and_or_64(i64* %p) {
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; CHECK: fetch_and_or_64:
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; CHECK: mov x[[ADDR:[0-9]+]], x0
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
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; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x0]
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; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], #0x7
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; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
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; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
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; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
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; CHECK: mov x0, [[DEST_REG]]
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%val = atomicrmw or i64* %p, i64 7 monotonic
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ret i64 %val
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}
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40
test/CodeGen/NVPTX/machine-sink.ll
Normal file
40
test/CodeGen/NVPTX/machine-sink.ll
Normal file
@ -0,0 +1,40 @@
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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@scalar1 = internal addrspace(3) global float 0.000000e+00, align 4
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@scalar2 = internal addrspace(3) global float 0.000000e+00, align 4
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; We shouldn't sink mul.rn.f32 to BB %merge because BB %merge post-dominates
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; BB %entry. Over-sinking created more register pressure on this example. The
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; backend would sink the fmuls to BB %merge, but not the loads for being
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; conservative on sinking memory accesses. As a result, the loads and
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; the two fmuls would be separated to two basic blocks, causing two
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; cross-BB live ranges.
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define float @post_dominate(float %x, i1 %cond) {
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; CHECK-LABEL: post_dominate(
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entry:
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%0 = load float* addrspacecast (float addrspace(3)* @scalar1 to float*), align 4
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%1 = load float* addrspacecast (float addrspace(3)* @scalar2 to float*), align 4
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; CHECK: ld.shared.f32
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; CHECK: ld.shared.f32
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%2 = fmul float %0, %0
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%3 = fmul float %1, %2
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; CHECK-NOT: bra
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; CHECK: mul.rn.f32
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; CHECK: mul.rn.f32
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br i1 %cond, label %then, label %merge
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then:
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%z = fadd float %x, %x
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br label %then2
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then2:
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%z2 = fadd float %z, %z
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br label %merge
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merge:
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%y = phi float [ 0.0, %entry ], [ %z2, %then2 ]
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%w = fadd float %y, %3
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ret float %w
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}
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@ -1,6 +1,9 @@
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; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
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; CHECK: leal 16(%eax), %edx
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; FIXME: The first two instructions, movl and addl, should have been combined to
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; "leal 16(%eax), %edx" by the backend (PR20766).
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; CHECK: movl %eax, %edx
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; CHECK: addl $16, %edx
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; CHECK: align
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; CHECK: addl $4, %edx
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; CHECK: decl %ecx
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