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https://github.com/RPCS3/llvm-mirror.git
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AMDGPU: Merge BUFFER_LOAD_DWORD_OFFEN into x2, x4
Summary: -9.9% code size decrease in affected shaders. Totals (changed stats only): SGPRS: 2151462 -> 2170646 (0.89 %) VGPRS: 1634612 -> 1640288 (0.35 %) Spilled SGPRs: 8942 -> 8940 (-0.02 %) Code Size: 52940672 -> 51727288 (-2.29 %) bytes Max Waves: 373066 -> 371718 (-0.36 %) Totals from affected shaders: SGPRS: 283520 -> 302704 (6.77 %) VGPRS: 227632 -> 233308 (2.49 %) Spilled SGPRs: 3966 -> 3964 (-0.05 %) Code Size: 12203080 -> 10989696 (-9.94 %) bytes Max Waves: 44070 -> 42722 (-3.06 %) Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D38950 llvm-svn: 317752
This commit is contained in:
Marek Olsak
parent
fcc32542ea
commit
2bb24b05c7
@ -75,6 +75,12 @@ using namespace llvm;
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namespace {
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class SILoadStoreOptimizer : public MachineFunctionPass {
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enum InstClassEnum {
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DS_READ_WRITE,
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S_BUFFER_LOAD_IMM,
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BUFFER_LOAD_OFFEN,
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};
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struct CombineInfo {
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MachineBasicBlock::iterator I;
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MachineBasicBlock::iterator Paired;
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@ -82,10 +88,12 @@ class SILoadStoreOptimizer : public MachineFunctionPass {
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unsigned Offset0;
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unsigned Offset1;
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unsigned BaseOff;
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InstClassEnum InstClass;
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bool GLC0;
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bool GLC1;
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bool SLC0;
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bool SLC1;
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bool UseST64;
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bool IsSBufferLoadImm;
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bool IsX2;
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SmallVector<MachineInstr*, 8> InstsToMove;
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};
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@ -104,6 +112,7 @@ private:
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MachineBasicBlock::iterator mergeRead2Pair(CombineInfo &CI);
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MachineBasicBlock::iterator mergeWrite2Pair(CombineInfo &CI);
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MachineBasicBlock::iterator mergeSBufferLoadImmPair(CombineInfo &CI);
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MachineBasicBlock::iterator mergeBufferLoadOffenPair(CombineInfo &CI);
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public:
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static char ID;
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@ -222,11 +231,13 @@ bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI) {
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CI.BaseOff = 0;
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// SMEM offsets must be consecutive.
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if (CI.IsSBufferLoadImm) {
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if (CI.InstClass == S_BUFFER_LOAD_IMM ||
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CI.InstClass == BUFFER_LOAD_OFFEN) {
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unsigned Diff = CI.IsX2 ? 2 : 1;
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return (EltOffset0 + Diff == EltOffset1 ||
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EltOffset1 + Diff == EltOffset0) &&
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CI.GLC0 == CI.GLC1;
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CI.GLC0 == CI.GLC1 &&
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(CI.InstClass == S_BUFFER_LOAD_IMM || CI.SLC0 == CI.SLC1);
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}
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// If the offset in elements doesn't fit in 8-bits, we might be able to use
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@ -271,20 +282,38 @@ bool SILoadStoreOptimizer::findMatchingInst(CombineInfo &CI) {
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MachineBasicBlock::iterator E = MBB->end();
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MachineBasicBlock::iterator MBBI = CI.I;
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unsigned AddrOpName;
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if (CI.IsSBufferLoadImm)
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AddrOpName = AMDGPU::OpName::sbase;
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else
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AddrOpName = AMDGPU::OpName::addr;
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unsigned AddrOpName[3] = {0};
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int AddrIdx[3];
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const MachineOperand *AddrReg[3];
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unsigned NumAddresses = 0;
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int AddrIdx = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AddrOpName);
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const MachineOperand &AddrReg0 = CI.I->getOperand(AddrIdx);
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switch (CI.InstClass) {
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case DS_READ_WRITE:
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AddrOpName[NumAddresses++] = AMDGPU::OpName::addr;
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break;
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case S_BUFFER_LOAD_IMM:
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AddrOpName[NumAddresses++] = AMDGPU::OpName::sbase;
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break;
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case BUFFER_LOAD_OFFEN:
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AddrOpName[NumAddresses++] = AMDGPU::OpName::srsrc;
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AddrOpName[NumAddresses++] = AMDGPU::OpName::vaddr;
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AddrOpName[NumAddresses++] = AMDGPU::OpName::soffset;
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break;
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default:
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llvm_unreachable("invalid InstClass");
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}
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// We only ever merge operations with the same base address register, so don't
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// bother scanning forward if there are no other uses.
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if (TargetRegisterInfo::isPhysicalRegister(AddrReg0.getReg()) ||
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MRI->hasOneNonDBGUse(AddrReg0.getReg()))
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return false;
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for (unsigned i = 0; i < NumAddresses; i++) {
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AddrIdx[i] = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AddrOpName[i]);
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AddrReg[i] = &CI.I->getOperand(AddrIdx[i]);
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// We only ever merge operations with the same base address register, so don't
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// bother scanning forward if there are no other uses.
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if (AddrReg[i]->isReg() &&
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(TargetRegisterInfo::isPhysicalRegister(AddrReg[i]->getReg()) ||
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MRI->hasOneNonDBGUse(AddrReg[i]->getReg())))
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return false;
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}
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++MBBI;
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@ -335,24 +364,45 @@ bool SILoadStoreOptimizer::findMatchingInst(CombineInfo &CI) {
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if (addToListsIfDependent(*MBBI, DefsToMove, CI.InstsToMove))
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continue;
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const MachineOperand &AddrReg1 = MBBI->getOperand(AddrIdx);
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bool Match = true;
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for (unsigned i = 0; i < NumAddresses; i++) {
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const MachineOperand &AddrRegNext = MBBI->getOperand(AddrIdx[i]);
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// Check same base pointer. Be careful of subregisters, which can occur with
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// vectors of pointers.
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if (AddrReg0.getReg() == AddrReg1.getReg() &&
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AddrReg0.getSubReg() == AddrReg1.getSubReg()) {
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if (AddrReg[i]->isImm() || AddrRegNext.isImm()) {
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if (AddrReg[i]->isImm() != AddrRegNext.isImm() ||
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AddrReg[i]->getImm() != AddrRegNext.getImm()) {
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Match = false;
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break;
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}
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continue;
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}
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// Check same base pointer. Be careful of subregisters, which can occur with
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// vectors of pointers.
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if (AddrReg[i]->getReg() != AddrRegNext.getReg() ||
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AddrReg[i]->getSubReg() != AddrRegNext.getSubReg()) {
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Match = false;
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break;
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}
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}
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if (Match) {
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int OffsetIdx = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(),
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AMDGPU::OpName::offset);
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CI.Offset0 = CI.I->getOperand(OffsetIdx).getImm();
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CI.Offset1 = MBBI->getOperand(OffsetIdx).getImm();
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CI.Paired = MBBI;
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if (CI.IsSBufferLoadImm) {
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CI.GLC0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::glc)->getImm();
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CI.GLC1 = TII->getNamedOperand(*MBBI, AMDGPU::OpName::glc)->getImm();
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} else {
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if (CI.InstClass == DS_READ_WRITE) {
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CI.Offset0 &= 0xffff;
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CI.Offset1 &= 0xffff;
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} else {
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CI.GLC0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::glc)->getImm();
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CI.GLC1 = TII->getNamedOperand(*MBBI, AMDGPU::OpName::glc)->getImm();
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if (CI.InstClass == BUFFER_LOAD_OFFEN) {
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CI.SLC0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::slc)->getImm();
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CI.SLC1 = TII->getNamedOperand(*MBBI, AMDGPU::OpName::slc)->getImm();
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}
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}
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// Check both offsets fit in the reduced range.
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@ -565,6 +615,55 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeSBufferLoadImmPair(
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return Next;
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}
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MachineBasicBlock::iterator SILoadStoreOptimizer::mergeBufferLoadOffenPair(
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CombineInfo &CI) {
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MachineBasicBlock *MBB = CI.I->getParent();
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DebugLoc DL = CI.I->getDebugLoc();
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unsigned Opcode = CI.IsX2 ? AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN :
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AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN;
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const TargetRegisterClass *SuperRC =
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CI.IsX2 ? &AMDGPU::VReg_128RegClass : &AMDGPU::VReg_64RegClass;
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unsigned DestReg = MRI->createVirtualRegister(SuperRC);
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unsigned MergedOffset = std::min(CI.Offset0, CI.Offset1);
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BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg)
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.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr))
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.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc))
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.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset))
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.addImm(MergedOffset) // offset
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.addImm(CI.GLC0) // glc
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.addImm(CI.SLC0) // slc
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.addImm(0) // tfe
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.setMemRefs(CI.I->mergeMemRefsWith(*CI.Paired));
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unsigned SubRegIdx0 = CI.IsX2 ? AMDGPU::sub0_sub1 : AMDGPU::sub0;
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unsigned SubRegIdx1 = CI.IsX2 ? AMDGPU::sub2_sub3 : AMDGPU::sub1;
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// Handle descending offsets
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if (CI.Offset0 > CI.Offset1)
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std::swap(SubRegIdx0, SubRegIdx1);
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// Copy to the old destination registers.
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const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
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const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata);
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const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::vdata);
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BuildMI(*MBB, CI.Paired, DL, CopyDesc)
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.add(*Dest0) // Copy to same destination including flags and sub reg.
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.addReg(DestReg, 0, SubRegIdx0);
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MachineInstr *Copy1 = BuildMI(*MBB, CI.Paired, DL, CopyDesc)
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.add(*Dest1)
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.addReg(DestReg, RegState::Kill, SubRegIdx1);
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moveInstsAfter(Copy1, CI.InstsToMove);
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MachineBasicBlock::iterator Next = std::next(CI.I);
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CI.I->eraseFromParent();
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CI.Paired->eraseFromParent();
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return Next;
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}
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// Scan through looking for adjacent LDS operations with constant offsets from
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// the same base register. We rely on the scheduler to do the hard work of
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// clustering nearby loads, and assume these are all adjacent.
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@ -582,9 +681,9 @@ bool SILoadStoreOptimizer::optimizeBlock(MachineBasicBlock &MBB) {
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CombineInfo CI;
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CI.I = I;
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CI.IsSBufferLoadImm = false;
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unsigned Opc = MI.getOpcode();
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if (Opc == AMDGPU::DS_READ_B32 || Opc == AMDGPU::DS_READ_B64) {
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CI.InstClass = DS_READ_WRITE;
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CI.EltSize = (Opc == AMDGPU::DS_READ_B64) ? 8 : 4;
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if (findMatchingInst(CI)) {
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Modified = true;
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@ -596,6 +695,7 @@ bool SILoadStoreOptimizer::optimizeBlock(MachineBasicBlock &MBB) {
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continue;
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}
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if (Opc == AMDGPU::DS_WRITE_B32 || Opc == AMDGPU::DS_WRITE_B64) {
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CI.InstClass = DS_READ_WRITE;
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CI.EltSize = (Opc == AMDGPU::DS_WRITE_B64) ? 8 : 4;
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if (findMatchingInst(CI)) {
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Modified = true;
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@ -610,8 +710,8 @@ bool SILoadStoreOptimizer::optimizeBlock(MachineBasicBlock &MBB) {
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(Opc == AMDGPU::S_BUFFER_LOAD_DWORD_IMM ||
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Opc == AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM)) {
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// EltSize is in units of the offset encoding.
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CI.InstClass = S_BUFFER_LOAD_IMM;
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CI.EltSize = AMDGPU::getSMRDEncodedOffset(*STM, 4);
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CI.IsSBufferLoadImm = true;
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CI.IsX2 = Opc == AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM;
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if (findMatchingInst(CI)) {
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Modified = true;
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@ -623,6 +723,21 @@ bool SILoadStoreOptimizer::optimizeBlock(MachineBasicBlock &MBB) {
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}
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continue;
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}
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if (Opc == AMDGPU::BUFFER_LOAD_DWORD_OFFEN ||
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Opc == AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN) {
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CI.InstClass = BUFFER_LOAD_OFFEN;
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CI.EltSize = 4;
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CI.IsX2 = Opc == AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN;
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if (findMatchingInst(CI)) {
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Modified = true;
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I = mergeBufferLoadOffenPair(CI);
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if (!CI.IsX2)
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CreatedX2++;
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} else {
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++I;
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}
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continue;
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}
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++I;
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}
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@ -126,8 +126,76 @@ entry:
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ret float %val
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}
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;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged:
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;CHECK-NEXT: BB#
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;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x1_offen_merged(<4 x i32> inreg %rsrc, i32 %a) {
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main_body:
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 8
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%a3 = add i32 %a, 12
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%a4 = add i32 %a, 16
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%a5 = add i32 %a, 28
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%a6 = add i32 %a, 32
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%r1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0)
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%r2 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0)
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%r3 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a3, i1 0, i1 0)
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%r4 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a4, i1 0, i1 0)
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%r5 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a5, i1 0, i1 0)
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%r6 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a6, i1 0, i1 0)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_glc_slc:
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;CHECK-NEXT: BB#
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;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4{{$}}
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;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:12 glc{{$}}
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;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 glc slc{{$}}
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(<4 x i32> inreg %rsrc, i32 %a) {
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main_body:
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 8
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%a3 = add i32 %a, 12
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%a4 = add i32 %a, 16
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%a5 = add i32 %a, 28
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%a6 = add i32 %a, 32
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%r1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0)
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%r2 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0)
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%r3 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a3, i1 1, i1 0)
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%r4 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a4, i1 1, i1 0)
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%r5 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a5, i1 1, i1 1)
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%r6 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 %a6, i1 1, i1 1)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged:
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;CHECK-NEXT: BB#
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;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x2_offen_merged(<4 x i32> inreg %rsrc, i32 %a) {
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main_body:
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 12
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%vr1 = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0)
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%vr2 = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0)
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%r1 = extractelement <2 x float> %vr1, i32 0
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%r2 = extractelement <2 x float> %vr1, i32 1
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%r3 = extractelement <2 x float> %vr2, i32 0
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%r4 = extractelement <2 x float> %vr2, i32 1
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
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ret void
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}
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declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0
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declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #0
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declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #0
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declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
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attributes #0 = { nounwind readonly }
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@ -238,6 +238,29 @@ main_body:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}smrd_vgpr_merged:
|
||||
; GCN-NEXT: BB#
|
||||
; GCN-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
|
||||
; GCN-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28
|
||||
define amdgpu_ps void @smrd_vgpr_merged(<4 x i32> inreg %desc, i32 %a) #0 {
|
||||
main_body:
|
||||
%a1 = add i32 %a, 4
|
||||
%a2 = add i32 %a, 8
|
||||
%a3 = add i32 %a, 12
|
||||
%a4 = add i32 %a, 16
|
||||
%a5 = add i32 %a, 28
|
||||
%a6 = add i32 %a, 32
|
||||
%r1 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a1)
|
||||
%r2 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a2)
|
||||
%r3 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a3)
|
||||
%r4 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a4)
|
||||
%r5 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a5)
|
||||
%r6 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a6)
|
||||
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) #0
|
||||
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) #0
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
|
||||
declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user