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Assume defaults to produce smaller datalayout strings.

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llvm-svn: 197249
This commit is contained in:
Rafael Espindola 2013-12-13 17:56:11 +00:00
parent 77962b5146
commit 2bd13393e0
6 changed files with 10 additions and 26 deletions
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4
lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -71,9 +71,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
DL("e-p:32:32:32-"
"i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
"f64:64:64-f32:32:32-a:0-n32") ,
DL("e-p:32:32:32-i64:64:64-i1:32:32-a:0-n32") ,
Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
TSInfo(*this),
FrameLowering(Subtarget),

2
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -34,7 +34,7 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T,
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS),
// FIXME: Check DataLayout string.
DL("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),
DL("e-p:16:16:16-i32:16:32-n8:16"),
InstrInfo(*this), TLInfo(*this), TSInfo(*this),
FrameLowering(Subtarget) {
initAsmInfo();

14
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -35,8 +35,6 @@ extern "C" void LLVMInitializePowerPCTarget() {
/// Return the datalayout string of a subtarget.
static std::string getDataLayoutString(const PPCSubtarget &ST) {
const Triple &T = ST.getTargetTriple();
// PPC is big endian.
std::string Ret = "E";
@ -48,19 +46,11 @@ static std::string getDataLayoutString(const PPCSubtarget &ST) {
// Note, the alignment values for f64 and i64 on ppc64 in Darwin
// documentation are wrong; these are correct (i.e. "what gcc does").
Ret += "-f64:64:64-i64:64:64";
Ret += "-i64:64:64";
// Set support for 128 floats depending on the ABI.
if (ST.isPPC64() && ST.isSVR4ABI()) {
if (T.getOS() != llvm::Triple::FreeBSD)
Ret += "-f128:128:128";
} else {
if (!ST.isPPC64() || !ST.isSVR4ABI())
Ret += "-f128:64:128";
}
// Some ABIs support 128 bit vectors.
if (ST.isPPC64() && ST.isSVR4ABI())
Ret += "-v128:128:128";
// PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
if (ST.isPPC64())

6
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -33,13 +33,13 @@ static std::string computeDataLayout(const SparcSubtarget &ST) {
else
Ret += "-p:32:32:32";
// Alignments for 64 bit integers and doubles.
Ret += "-i64:64:64-f64:64:64";
// Alignments for 64 bit integers.
Ret += "-i64:64:64";
// On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
// On SparcV9 registers can hold 64 or 32 bits, on others only 32.
if (ST.is64Bit())
Ret += "-f128:128:128-n32:64";
Ret += "-n32:64";
else
Ret += "-f128:64:64-n32";

7
lib/Target/X86/X86TargetMachine.cpp
View File

@ -47,9 +47,9 @@ static std::string computeDataLayout(const X86Subtarget &ST) {
// Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows())
Ret += "-f64:64:64-i64:64:64";
Ret += "-i64:64:64";
else
Ret += "-f64:32:64-i64:32:64";
Ret += "-f64:32:64";
// Some ABIs align long double to 128 bits, others to 32.
if (ST.is64Bit() || ST.isTargetDarwin())
@ -57,9 +57,6 @@ static std::string computeDataLayout(const X86Subtarget &ST) {
else
Ret += "-f80:32:32";
// 128 bit floats (?) are aligned to 128 bits.
Ret += "-f128:128:128";
// The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
if (ST.is64Bit())
Ret += "-n8:16:32:64";

3
lib/Target/XCore/XCoreTargetMachine.cpp
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@ -27,8 +27,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS),
DL("e-p:32:32:32-a:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
"i16:16:32-i32:32:32-i64:32:32-n32"),
DL("e-p:32:32:32-a:0:32-f64:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32:32-n32"),
InstrInfo(),
FrameLowering(Subtarget),
TLInfo(*this),