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[AArch64][SVE] Allow llvm.aarch64.sve.st2/3/4 with vectors of pointers.
This isn't necessaary for ACLE, but could be useful in other situations. And the change is simple. Differential Revision: https://reviews.llvm.org/D85251
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Eli Friedman
parent
67ae683e5b
commit
2be753c211
@ -9462,16 +9462,17 @@ SDValue AArch64TargetLowering::LowerVSCALE(SDValue Op,
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/// Set the IntrinsicInfo for the `aarch64_sve_st<N>` intrinsics.
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template <unsigned NumVecs>
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static bool setInfoSVEStN(AArch64TargetLowering::IntrinsicInfo &Info,
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const CallInst &CI) {
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static bool
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setInfoSVEStN(const AArch64TargetLowering &TLI, const DataLayout &DL,
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AArch64TargetLowering::IntrinsicInfo &Info, const CallInst &CI) {
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Info.opc = ISD::INTRINSIC_VOID;
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// Retrieve EC from first vector argument.
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const EVT VT = EVT::getEVT(CI.getArgOperand(0)->getType());
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const EVT VT = TLI.getMemValueType(DL, CI.getArgOperand(0)->getType());
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ElementCount EC = VT.getVectorElementCount();
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#ifndef NDEBUG
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// Check the assumption that all input vectors are the same type.
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for (unsigned I = 0; I < NumVecs; ++I)
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assert(VT == EVT::getEVT(CI.getArgOperand(I)->getType()) &&
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assert(VT == TLI.getMemValueType(DL, CI.getArgOperand(I)->getType()) &&
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"Invalid type.");
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#endif
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// memVT is `NumVecs * VT`.
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@ -9494,11 +9495,11 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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auto &DL = I.getModule()->getDataLayout();
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switch (Intrinsic) {
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case Intrinsic::aarch64_sve_st2:
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return setInfoSVEStN<2>(Info, I);
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return setInfoSVEStN<2>(*this, DL, Info, I);
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case Intrinsic::aarch64_sve_st3:
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return setInfoSVEStN<3>(Info, I);
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return setInfoSVEStN<3>(*this, DL, Info, I);
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case Intrinsic::aarch64_sve_st4:
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return setInfoSVEStN<4>(Info, I);
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return setInfoSVEStN<4>(*this, DL, Info, I);
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case Intrinsic::aarch64_neon_ld2:
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case Intrinsic::aarch64_neon_ld3:
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case Intrinsic::aarch64_neon_ld4:
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@ -108,6 +108,17 @@ define void @st2d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vsc
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ret void
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}
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define void @st2d_ptr(<vscale x 2 x i8*> %v0, <vscale x 2 x i8*> %v1, <vscale x 2 x i1> %pred, i8** %addr) {
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; CHECK-LABEL: st2d_ptr:
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; CHECK: st2d { z0.d, z1.d }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st2.nxv2p0i8(<vscale x 2 x i8*> %v0,
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<vscale x 2 x i8*> %v1,
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<vscale x 2 x i1> %pred,
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i8** %addr)
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ret void
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}
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;
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; ST3B
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;
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@ -220,6 +231,18 @@ define void @st3d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vsc
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ret void
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}
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define void @st3d_ptr(<vscale x 2 x i8*> %v0, <vscale x 2 x i8*> %v1, <vscale x 2 x i8*> %v2, <vscale x 2 x i1> %pred, i8** %addr) {
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; CHECK-LABEL: st3d_ptr:
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; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st3.nxv2p0i8(<vscale x 2 x i8*> %v0,
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<vscale x 2 x i8*> %v1,
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<vscale x 2 x i8*> %v2,
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<vscale x 2 x i1> %pred,
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i8** %addr)
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ret void
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}
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;
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; ST4B
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;
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@ -340,6 +363,18 @@ define void @st4d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vsc
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ret void
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}
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define void @st4d_ptr(<vscale x 2 x i8*> %v0, <vscale x 2 x i8*> %v1, <vscale x 2 x i8*> %v2, <vscale x 2 x i8*> %v3, <vscale x 2 x i1> %pred, i8** %addr) {
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; CHECK-LABEL: st4d_ptr:
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; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st4.nxv2p0i8(<vscale x 2 x i8*> %v0,
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<vscale x 2 x i8*> %v1,
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<vscale x 2 x i8*> %v2,
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<vscale x 2 x i8*> %v3,
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<vscale x 2 x i1> %pred,
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i8** %addr)
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ret void
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}
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;
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; STNT1B
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;
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@ -508,6 +543,7 @@ declare void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x ha
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declare void @llvm.aarch64.sve.st2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, bfloat*)
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declare void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, float*)
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declare void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, double*)
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declare void @llvm.aarch64.sve.st2.nxv2p0i8(<vscale x 2 x i8*>, <vscale x 2 x i8*>, <vscale x 2 x i1>, i8** nocapture)
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declare void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
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declare void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
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@ -517,6 +553,7 @@ declare void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half>, <vscale x 8 x ha
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declare void @llvm.aarch64.sve.st3.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, bfloat*)
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declare void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, float*)
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declare void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, double*)
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declare void @llvm.aarch64.sve.st3.nxv2p0i8(<vscale x 2 x i8*>, <vscale x 2 x i8*>, <vscale x 2 x i8*>, <vscale x 2 x i1>, i8** nocapture)
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declare void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
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declare void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
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@ -526,6 +563,7 @@ declare void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x ha
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declare void @llvm.aarch64.sve.st4.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, bfloat*)
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declare void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, float*)
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declare void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, double*)
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declare void @llvm.aarch64.sve.st4.nxv2p0i8(<vscale x 2 x i8*>, <vscale x 2 x i8*>, <vscale x 2 x i8*>, <vscale x 2 x i8*>, <vscale x 2 x i1>, i8** nocapture)
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declare void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
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declare void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
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