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[GlobalISel][AArch64] Use getConstantVRegValWithLookThrough for extracts

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getConstantVRegValWithLookThrough does the same thing as the
getConstantValueForReg function, and has more visibility across GISel. Plus, it
supports looking through G_TRUNC, G_SEXT, and G_ZEXT. So, we get better code
reuse and more functionality for free by using it.

Add some test cases to select-extract-vector-elt.mir to show that we can now
look through those instructions.

llvm-svn: 359351
This commit is contained in:
Jessica Paquette 2019-04-26 21:53:13 +00:00
parent 02a0e7f7fc
commit 2be787ea59
2 changed files with 77 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
lib/Target/AArch64/AArch64InstructionSelector.cpp
View File

@ -2288,40 +2288,6 @@ static bool getLaneCopyOpcode(unsigned &CopyOpc, unsigned &ExtractSubReg,
return true;
}
/// Given a register \p Reg, find the value of a constant defining \p Reg.
/// Return true if one could be found, and store it in \p Val. Return false
/// otherwise.
static bool getConstantValueForReg(unsigned Reg, MachineRegisterInfo &MRI,
unsigned &Val) {
// Look at the def of the register.
MachineInstr *Def = MRI.getVRegDef(Reg);
if (!Def)
return false;
// Find the first definition which isn't a copy.
if (Def->isCopy()) {
Reg = Def->getOperand(1).getReg();
auto It = find_if_not(MRI.reg_nodbg_instructions(Reg),
[](const MachineInstr &MI) { return MI.isCopy(); });
if (It == MRI.reg_instr_nodbg_end()) {
LLVM_DEBUG(dbgs() << "Couldn't find non-copy def for register\n");
return false;
}
Def = &*It;
}
// TODO: Handle opcodes other than G_CONSTANT.
if (Def->getOpcode() != TargetOpcode::G_CONSTANT) {
LLVM_DEBUG(dbgs() << "VRegs defined by anything other than G_CONSTANT "
"currently unsupported.\n");
return false;
}
// Return the constant value associated with the operand.
Val = Def->getOperand(1).getCImm()->getLimitedValue();
return true;
}
MachineInstr *AArch64InstructionSelector::emitExtractVectorElt(
Optional<unsigned> DstReg, const RegisterBank &DstRB, LLT ScalarTy,
unsigned VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const {
@ -2405,9 +2371,10 @@ bool AArch64InstructionSelector::selectExtractElt(
}
// Find the index to extract from.
unsigned LaneIdx = 0;
if (!getConstantValueForReg(LaneIdxOp.getReg(), MRI, LaneIdx))
auto VRegAndVal = getConstantVRegValWithLookThrough(LaneIdxOp.getReg(), MRI);
if (!VRegAndVal)
return false;
unsigned LaneIdx = VRegAndVal->Value;
MachineIRBuilder MIRBuilder(I);
@ -2983,9 +2950,10 @@ bool AArch64InstructionSelector::selectInsertElt(
// Find the definition of the index. Bail out if it's not defined by a
// G_CONSTANT.
unsigned IdxReg = I.getOperand(3).getReg();
unsigned LaneIdx = 0;
if (!getConstantValueForReg(IdxReg, MRI, LaneIdx))
auto VRegAndVal = getConstantVRegValWithLookThrough(IdxReg, MRI);
if (!VRegAndVal)
return false;
unsigned LaneIdx = VRegAndVal->Value;
// Perform the lane insert.
unsigned SrcReg = I.getOperand(1).getReg();

71
test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir
View File

@ -138,3 +138,74 @@ body: |
RET_ReallyLR implicit $h0
...
---
name: v8s16_fpr_zext
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s16_fpr_zext
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
; CHECK: $h0 = COPY [[CPYi16_]]
; CHECK: RET_ReallyLR implicit $h0
%0:fpr(<8 x s16>) = COPY $q0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s64) = G_ZEXT %1
%3:fpr(s64) = COPY %2(s64)
%4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
$h0 = COPY %4(s16)
RET_ReallyLR implicit $h0
...
---
name: v8s16_fpr_sext
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s16_fpr_sext
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
; CHECK: $h0 = COPY [[CPYi16_]]
; CHECK: RET_ReallyLR implicit $h0
%0:fpr(<8 x s16>) = COPY $q0
%1:gpr(s32) = G_CONSTANT i32 1
%2:gpr(s64) = G_SEXT %1
%3:fpr(s64) = COPY %2(s64)
%4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
$h0 = COPY %4(s16)
RET_ReallyLR implicit $h0
...
---
name: v8s16_fpr_trunc
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s16_fpr_trunc
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
; CHECK: $h0 = COPY [[CPYi16_]]
; CHECK: RET_ReallyLR implicit $h0
%0:fpr(<8 x s16>) = COPY $q0
%1:gpr(s64) = G_CONSTANT i64 1
%2:gpr(s32) = G_TRUNC %1
%3:gpr(s64) = G_SEXT %2
%4:fpr(s64) = COPY %3(s64)
%5:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
$h0 = COPY %5(s16)
RET_ReallyLR implicit $h0