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[InstCombine] add test with more unreachable insts; NFC
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@ -597,6 +597,51 @@ exit:
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unreachable
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}
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define i32 @unreachable_assumes_and_store(i32 %x, i32 %y, i32* %p) {
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; CHECK-LABEL: @unreachable_assumes_and_store(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP0:%.*]] = icmp sgt i32 [[X:%.*]], 1
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[Y:%.*]], 1
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP0]], [[CMP1]]
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[OR]])
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[X]], 1
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; CHECK-NEXT: br i1 [[CMP2]], label [[IF:%.*]], label [[EXIT:%.*]]
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; CHECK: if:
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; CHECK-NEXT: [[A:%.*]] = and i32 [[Y]], -2
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; CHECK-NEXT: [[CMP3:%.*]] = icmp ne i32 [[A]], 104
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP3]])
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: [[CMP4:%.*]] = icmp eq i32 [[X]], 2
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP4]])
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; CHECK-NEXT: [[CMP5:%.*]] = icmp ugt i32 [[Y]], 42
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP5]])
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; CHECK-NEXT: store i32 [[X]], i32* [[P:%.*]], align 4
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; CHECK-NEXT: unreachable
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;
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entry:
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%cmp0 = icmp sgt i32 %x, 1
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%cmp1 = icmp eq i32 %y, 1
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%or = or i1 %cmp0, %cmp1
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tail call void @llvm.assume(i1 %or)
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%cmp2 = icmp eq i32 %x, 1
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br i1 %cmp2, label %if, label %exit
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if:
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%a = and i32 %y, -2
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%cmp3 = icmp ne i32 %a, 104
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tail call void @llvm.assume(i1 %cmp3)
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br label %exit
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exit:
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%cmp4 = icmp eq i32 %x, 2
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tail call void @llvm.assume(i1 %cmp4)
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%cmp5 = icmp ugt i32 %y, 42
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tail call void @llvm.assume(i1 %cmp5)
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store i32 %x, i32* %p
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unreachable
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}
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declare void @llvm.dbg.value(metadata, metadata, metadata)
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!llvm.dbg.cu = !{!0}
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