RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 12:02:58 +02:00
Code Issues Projects Releases Wiki Activity

[PowerPC] make lwa as a valid ds candidate in ppcloopinstrformprep pass

Browse Source 
Fix a FIXME in ppcloopinstrformprep pass.

Reviewed by: nemanjai

Differential Revision: https://reviews.llvm.org/D71346
This commit is contained in:
czhengsz 2019-12-18 21:03:54 -05:00
parent b90ca11f23
commit 2c60ab434c
2 changed files with 20 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
View File

@ -846,11 +846,15 @@ bool PPCLoopInstrFormPrep::runOnLoop(Loop *L) {
// Check if a load/store has DS form.
auto isDSFormCandidate = [] (const Instruction *I, const Value *PtrValue) {
assert((PtrValue && I) && "Invalid parameter!");
// FIXME: 32 bit instruction lwa is also DS form.
return !isa<IntrinsicInst>(I) &&
((PtrValue->getType()->getPointerElementType()->isIntegerTy(64)) ||
(PtrValue->getType()->getPointerElementType()->isFloatTy()) ||
(PtrValue->getType()->getPointerElementType()->isDoubleTy()));
if (isa<IntrinsicInst>(I))
return false;
Type *PointerElementType = PtrValue->getType()->getPointerElementType();
return (PointerElementType->isIntegerTy(64)) ||
(PointerElementType->isFloatTy()) ||
(PointerElementType->isDoubleTy()) ||
(PointerElementType->isIntegerTy(32) &&
llvm::any_of(I->users(),
[](const User *U) { return isa<SExtInst>(U); }));
};
// Check if a load/store has DQ form.

24
test/CodeGen/PowerPC/loop-instr-form-prepare.ll
View File

@ -774,20 +774,17 @@ define float @test_ds_combine_float_int(i8* %0, i32 signext %1) {
define i64 @test_ds_lwa_prep(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_ds_lwa_prep:
; CHECK: li r6, 1
; CHECK-NEXT: li r7, 2
; CHECK-NEXT: li r8, 6
; CHECK-NEXT: li r9, 10
; CHECK: addi r5, r3, 2
; CHECK: li r6, -1
; CHECK: .LBB9_2: #
; CHECK-NEXT: lwax r11, r3, r6
; CHECK-NEXT: lwax r12, r3, r7
; CHECK-NEXT: lwax r0, r3, r8
; CHECK-NEXT: addi r10, r3, 1
; CHECK-NEXT: mulld r11, r12, r11
; CHECK-NEXT: lwax r3, r3, r9
; CHECK-NEXT: mulld r11, r11, r0
; CHECK-NEXT: maddld r5, r11, r3, r5
; CHECK-NEXT: mr r3, r10
; CHECK-NEXT: lwax r7, r5, r6
; CHECK-NEXT: lwa r8, 0(r5)
; CHECK-NEXT: lwa r9, 4(r5)
; CHECK-NEXT: lwa r10, 8(r5)
; CHECK-NEXT: addi r5, r5, 1
; CHECK-NEXT: mulld r7, r8, r7
; CHECK-NEXT: mulld r7, r7, r9
; CHECK-NEXT: maddld r3, r7, r10, r3
; CHECK-NEXT: bdnz .LBB9_2
%3 = sext i32 %1 to i64
@ -827,3 +824,4 @@ define i64 @test_ds_lwa_prep(i8* %0, i32 signext %1) {
%33 = add nsw i64 %32, %3
ret i64 %33
}