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[SLPVectorizer] Recognise non uniform power of 2 constants
Since D46637 we are better at handling uniform/non-uniform constant Pow2 detection; this patch tweaks the SLP argument handling to support them. As SLP works with arrays of values I don't think we can easily use the pattern match helpers here. Differential Revision: https://reviews.llvm.org/D48214 llvm-svn: 335621
This commit is contained in:
Simon Pilgrim
parent
0fb77c5c0e
commit
2c643d6425
@ -2224,33 +2224,32 @@ int BoUpSLP::getEntryCost(TreeEntry *E) {
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TargetTransformInfo::OperandValueProperties Op1VP =
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TargetTransformInfo::OP_None;
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TargetTransformInfo::OperandValueProperties Op2VP =
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TargetTransformInfo::OP_None;
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TargetTransformInfo::OP_PowerOf2;
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// If all operands are exactly the same ConstantInt then set the
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// operand kind to OK_UniformConstantValue.
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// If instead not all operands are constants, then set the operand kind
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// to OK_AnyValue. If all operands are constants but not the same,
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// then set the operand kind to OK_NonUniformConstantValue.
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ConstantInt *CInt = nullptr;
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for (unsigned i = 0; i < VL.size(); ++i) {
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ConstantInt *CInt0 = nullptr;
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for (unsigned i = 0, e = VL.size(); i < e; ++i) {
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const Instruction *I = cast<Instruction>(VL[i]);
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if (!isa<ConstantInt>(I->getOperand(1))) {
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ConstantInt *CInt = dyn_cast<ConstantInt>(I->getOperand(1));
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if (!CInt) {
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Op2VK = TargetTransformInfo::OK_AnyValue;
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Op2VP = TargetTransformInfo::OP_None;
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break;
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}
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if (Op2VP == TargetTransformInfo::OP_PowerOf2 &&
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!CInt->getValue().isPowerOf2())
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Op2VP = TargetTransformInfo::OP_None;
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if (i == 0) {
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CInt = cast<ConstantInt>(I->getOperand(1));
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CInt0 = CInt;
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continue;
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}
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if (Op2VK == TargetTransformInfo::OK_UniformConstantValue &&
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CInt != cast<ConstantInt>(I->getOperand(1)))
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if (CInt0 != CInt)
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Op2VK = TargetTransformInfo::OK_NonUniformConstantValue;
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}
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// FIXME: Currently cost of model modification for division by power of
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// 2 is handled for X86 and AArch64. Add support for other targets.
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if (Op2VK == TargetTransformInfo::OK_UniformConstantValue && CInt &&
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CInt->getValue().isPowerOf2())
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Op2VP = TargetTransformInfo::OP_PowerOf2;
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SmallVector<const Value *, 4> Operands(VL0->operand_values());
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if (NeedToShuffleReuses) {
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@ -58,38 +58,59 @@ entry:
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}
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define void @powof2div_nonuniform(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* noalias nocapture readonly %c){
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; CHECK-LABEL: @powof2div_nonuniform(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[C:%.*]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP0]]
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[ADD]], 2
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; CHECK-NEXT: store i32 [[DIV]], i32* [[A:%.*]], align 4
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; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 1
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; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4
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; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[C]], i64 1
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; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4
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; CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], [[TMP2]]
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; CHECK-NEXT: [[DIV6:%.*]] = sdiv i32 [[ADD5]], 4
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; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 1
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; CHECK-NEXT: store i32 [[DIV6]], i32* [[ARRAYIDX7]], align 4
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; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 2
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; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4
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; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[C]], i64 2
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; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX9]], align 4
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; CHECK-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
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; CHECK-NEXT: [[DIV11:%.*]] = sdiv i32 [[ADD10]], 8
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; CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 2
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; CHECK-NEXT: store i32 [[DIV11]], i32* [[ARRAYIDX12]], align 4
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; CHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 3
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; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX13]], align 4
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; CHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds i32, i32* [[C]], i64 3
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; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX14]], align 4
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; CHECK-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP7]], [[TMP6]]
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; CHECK-NEXT: [[DIV16:%.*]] = sdiv i32 [[ADD15]], 16
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; CHECK-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 3
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; CHECK-NEXT: store i32 [[DIV16]], i32* [[ARRAYIDX17]], align 4
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; CHECK-NEXT: ret void
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; AVX1-LABEL: @powof2div_nonuniform(
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; AVX1-NEXT: entry:
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; AVX1-NEXT: [[TMP0:%.*]] = load i32, i32* [[B:%.*]], align 4
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; AVX1-NEXT: [[TMP1:%.*]] = load i32, i32* [[C:%.*]], align 4
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; AVX1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP0]]
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; AVX1-NEXT: [[DIV:%.*]] = sdiv i32 [[ADD]], 2
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; AVX1-NEXT: store i32 [[DIV]], i32* [[A:%.*]], align 4
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; AVX1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 1
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; AVX1-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4
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; AVX1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[C]], i64 1
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; AVX1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX4]], align 4
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; AVX1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], [[TMP2]]
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; AVX1-NEXT: [[DIV6:%.*]] = sdiv i32 [[ADD5]], 4
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; AVX1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 1
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; AVX1-NEXT: store i32 [[DIV6]], i32* [[ARRAYIDX7]], align 4
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; AVX1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 2
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; AVX1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX8]], align 4
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; AVX1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[C]], i64 2
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; AVX1-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX9]], align 4
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; AVX1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
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; AVX1-NEXT: [[DIV11:%.*]] = sdiv i32 [[ADD10]], 8
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; AVX1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 2
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; AVX1-NEXT: store i32 [[DIV11]], i32* [[ARRAYIDX12]], align 4
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; AVX1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 3
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; AVX1-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX13]], align 4
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; AVX1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds i32, i32* [[C]], i64 3
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; AVX1-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX14]], align 4
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; AVX1-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP7]], [[TMP6]]
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; AVX1-NEXT: [[DIV16:%.*]] = sdiv i32 [[ADD15]], 16
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; AVX1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 3
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; AVX1-NEXT: store i32 [[DIV16]], i32* [[ARRAYIDX17]], align 4
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; AVX1-NEXT: ret void
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;
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; AVX2-LABEL: @powof2div_nonuniform(
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; AVX2-NEXT: entry:
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; AVX2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 1
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; AVX2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[C:%.*]], i64 1
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; AVX2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 1
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; AVX2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 2
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; AVX2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, i32* [[C]], i64 2
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; AVX2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 2
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; AVX2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 3
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; AVX2-NEXT: [[TMP0:%.*]] = bitcast i32* [[B]] to <4 x i32>*
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; AVX2-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4
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; AVX2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds i32, i32* [[C]], i64 3
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; AVX2-NEXT: [[TMP2:%.*]] = bitcast i32* [[C]] to <4 x i32>*
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; AVX2-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4
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; AVX2-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[TMP3]], [[TMP1]]
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; AVX2-NEXT: [[TMP5:%.*]] = sdiv <4 x i32> [[TMP4]], <i32 2, i32 4, i32 8, i32 16>
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; AVX2-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds i32, i32* [[A]], i64 3
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; AVX2-NEXT: [[TMP6:%.*]] = bitcast i32* [[A]] to <4 x i32>*
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; AVX2-NEXT: store <4 x i32> [[TMP5]], <4 x i32>* [[TMP6]], align 4
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; AVX2-NEXT: ret void
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;
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entry:
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%0 = load i32, i32* %b, align 4
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