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[RISCV] Minor vector instruction tablegen cleanup. NFC

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Use result_type for the IMPLICIT_DEF in masked vector patterns.
This doesn't matter today because result_type and op_type are
always the same.

Use multiclass inheritance to reduce repeated code.
This commit is contained in:
Craig Topper 2021-05-06 11:21:46 -07:00
parent b76e201ee8
commit 2c6f23cea3
2 changed files with 6 additions and 20 deletions
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12
lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
View File

@ -138,8 +138,7 @@ class VPatBinarySDNode_XI<SDNode vop,
xop_kind:$rs2,
avl, sew)>;
multiclass VPatBinarySDNode_VV_VX<SDNode vop, string instruction_name>
{
multiclass VPatBinarySDNode_VV_VX<SDNode vop, string instruction_name> {
foreach vti = AllIntegerVectors in {
def : VPatBinarySDNode_VV<vop, instruction_name,
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
@ -153,15 +152,8 @@ multiclass VPatBinarySDNode_VV_VX<SDNode vop, string instruction_name>
multiclass VPatBinarySDNode_VV_VX_VI<SDNode vop, string instruction_name,
Operand ImmType = simm5>
{
: VPatBinarySDNode_VV_VX<vop, instruction_name> {
foreach vti = AllIntegerVectors in {
def : VPatBinarySDNode_VV<vop, instruction_name,
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
def : VPatBinarySDNode_XI<vop, instruction_name, "VX",
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
SplatPat, GPR>;
def : VPatBinarySDNode_XI<vop, instruction_name, "VI",
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,

14
lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
View File

@ -262,7 +262,7 @@ multiclass VPatBinaryVL_VV<SDNode vop,
(mask_type VMV0:$vm),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX#"_MASK")
(op_type (IMPLICIT_DEF)),
(result_type (IMPLICIT_DEF)),
op_reg_class:$rs1,
op_reg_class:$rs2,
VMV0:$vm, GPR:$vl, sew)>;
@ -295,7 +295,7 @@ multiclass VPatBinaryVL_XI<SDNode vop,
(mask_type VMV0:$vm),
VLOpFrag)),
(!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_MASK")
(vop_type (IMPLICIT_DEF)),
(result_type (IMPLICIT_DEF)),
vop_reg_class:$rs1,
xop_kind:$rs2,
VMV0:$vm, GPR:$vl, sew)>;
@ -314,15 +314,9 @@ multiclass VPatBinaryVL_VV_VX<SDNode vop, string instruction_name> {
}
multiclass VPatBinaryVL_VV_VX_VI<SDNode vop, string instruction_name,
Operand ImmType = simm5> {
Operand ImmType = simm5>
: VPatBinaryVL_VV_VX<vop, instruction_name> {
foreach vti = AllIntegerVectors in {
defm : VPatBinaryVL_VV<vop, instruction_name,
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.RegClass, vti.RegClass>;
defm : VPatBinaryVL_XI<vop, instruction_name, "VX",
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.RegClass, vti.RegClass,
SplatPat, GPR>;
defm : VPatBinaryVL_XI<vop, instruction_name, "VI",
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.RegClass, vti.RegClass,