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Output sinl for a long double FSIN node, not sin.

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Likewise fix up a bunch of other libcalls.  While
there I remove NEG_F32 and NEG_F64 since they are
not used anywhere.  This fixes 9 Ada ACATS failures.

llvm-svn: 45833
This commit is contained in:
Duncan Sands 2008-01-10 10:28:30 +00:00
parent 444d24972f
commit 2c89976416
5 changed files with 84 additions and 58 deletions
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11
include/llvm/CodeGen/RuntimeLibcalls.h
View File

@ -49,21 +49,24 @@ namespace RTLIB {
// FLOATING POINT // FLOATING POINT
ADD_F32, ADD_F32,
ADD_F64, ADD_F64,
ADD_F80,
ADD_PPCF128, ADD_PPCF128,
SUB_F32, SUB_F32,
SUB_F64, SUB_F64,
SUB_F80,
SUB_PPCF128, SUB_PPCF128,
MUL_F32, MUL_F32,
MUL_F64, MUL_F64,
MUL_F80,
MUL_PPCF128, MUL_PPCF128,
DIV_F32, DIV_F32,
DIV_F64, DIV_F64,
DIV_F80,
DIV_PPCF128, DIV_PPCF128,
REM_F32, REM_F32,
REM_F64, REM_F64,
REM_F80,
REM_PPCF128, REM_PPCF128,
NEG_F32,
NEG_F64,
POWI_F32, POWI_F32,
POWI_F64, POWI_F64,
POWI_F80, POWI_F80,
@ -74,8 +77,12 @@ namespace RTLIB {
SQRT_PPCF128, SQRT_PPCF128,
SIN_F32, SIN_F32,
SIN_F64, SIN_F64,
SIN_F80,
SIN_PPCF128,
COS_F32, COS_F32,
COS_F64, COS_F64,
COS_F80,
COS_PPCF128,
POW_F32, POW_F32,
POW_F64, POW_F64,
POW_F80, POW_F80,

105
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -737,6 +737,20 @@ SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
} }
/// GetFPLibCall - Return the right libcall for the given floating point type.
static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
RTLIB::Libcall Call_F32,
RTLIB::Libcall Call_F64,
RTLIB::Libcall Call_F80,
RTLIB::Libcall Call_PPCF128) {
return
VT == MVT::f32 ? Call_F32 :
VT == MVT::f64 ? Call_F64 :
VT == MVT::f80 ? Call_F80 :
VT == MVT::ppcf128 ? Call_PPCF128 :
RTLIB::UNKNOWN_LIBCALL;
}
/// LegalizeOp - We know that the specified value has a legal type, and /// LegalizeOp - We know that the specified value has a legal type, and
/// that its operands are legal. Now ensure that the operation itself /// that its operands are legal. Now ensure that the operation itself
/// is legal, recursively ensuring that the operands' operations remain /// is legal, recursively ensuring that the operands' operations remain
@ -2774,11 +2788,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
} }
break; break;
case ISD::FPOW: case ISD::FPOW:
LC = VT == MVT::f32 ? RTLIB::POW_F32 : LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
VT == MVT::f64 ? RTLIB::POW_F64 : RTLIB::POW_PPCF128);
VT == MVT::f80 ? RTLIB::POW_F80 :
VT == MVT::ppcf128 ? RTLIB::POW_PPCF128 :
RTLIB::UNKNOWN_LIBCALL;
break; break;
default: break; default: break;
} }
@ -2996,8 +3007,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
Result = LegalizeOp(UnrollVectorOp(Op)); Result = LegalizeOp(UnrollVectorOp(Op));
} else { } else {
// Floating point mod -> fmod libcall. // Floating point mod -> fmod libcall.
RTLIB::Libcall LC = VT == MVT::f32 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
? RTLIB::REM_F32 : RTLIB::REM_F64; RTLIB::REM_F80, RTLIB::REM_PPCF128);
SDOperand Dummy; SDOperand Dummy;
Result = ExpandLibCall(TLI.getLibcallName(LC), Node, Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
false/*sign irrelevant*/, Dummy); false/*sign irrelevant*/, Dummy);
@ -3274,17 +3285,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
switch(Node->getOpcode()) { switch(Node->getOpcode()) {
case ISD::FSQRT: case ISD::FSQRT:
LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
VT == MVT::f64 ? RTLIB::SQRT_F64 : RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
VT == MVT::f80 ? RTLIB::SQRT_F80 :
VT == MVT::ppcf128 ? RTLIB::SQRT_PPCF128 :
RTLIB::UNKNOWN_LIBCALL;
break; break;
case ISD::FSIN: case ISD::FSIN:
LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64; LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
break; break;
case ISD::FCOS: case ISD::FCOS:
LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64; LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
RTLIB::COS_F80, RTLIB::COS_PPCF128);
break; break;
default: assert(0 && "Unreachable!"); default: assert(0 && "Unreachable!");
} }
@ -3307,12 +3317,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
} }
// We always lower FPOWI into a libcall. No target support for it yet. // We always lower FPOWI into a libcall. No target support for it yet.
RTLIB::Libcall LC = RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
VT == MVT::f32 ? RTLIB::POWI_F32 : RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
VT == MVT::f64 ? RTLIB::POWI_F64 :
VT == MVT::f80 ? RTLIB::POWI_F80 :
VT == MVT::ppcf128 ? RTLIB::POWI_PPCF128 :
RTLIB::UNKNOWN_LIBCALL;
SDOperand Dummy; SDOperand Dummy;
Result = ExpandLibCall(TLI.getLibcallName(LC), Node, Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
false/*sign irrelevant*/, Dummy); false/*sign irrelevant*/, Dummy);
@ -6067,35 +6073,31 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
break; break;
case ISD::FADD: case ISD::FADD:
Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::ADD_F32 : Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
VT == MVT::f64 ? RTLIB::ADD_F64 : RTLIB::ADD_F64,
VT == MVT::ppcf128 ? RTLIB::ADD_F80,
RTLIB::ADD_PPCF128 : RTLIB::ADD_PPCF128)),
RTLIB::UNKNOWN_LIBCALL),
Node, false, Hi); Node, false, Hi);
break; break;
case ISD::FSUB: case ISD::FSUB:
Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::SUB_F32 : Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
VT == MVT::f64 ? RTLIB::SUB_F64 : RTLIB::SUB_F64,
VT == MVT::ppcf128 ? RTLIB::SUB_F80,
RTLIB::SUB_PPCF128 : RTLIB::SUB_PPCF128)),
RTLIB::UNKNOWN_LIBCALL),
Node, false, Hi); Node, false, Hi);
break; break;
case ISD::FMUL: case ISD::FMUL:
Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::MUL_F32 : Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
VT == MVT::f64 ? RTLIB::MUL_F64 : RTLIB::MUL_F64,
VT == MVT::ppcf128 ? RTLIB::MUL_F80,
RTLIB::MUL_PPCF128 : RTLIB::MUL_PPCF128)),
RTLIB::UNKNOWN_LIBCALL),
Node, false, Hi); Node, false, Hi);
break; break;
case ISD::FDIV: case ISD::FDIV:
Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::DIV_F32 : Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
VT == MVT::f64 ? RTLIB::DIV_F64 : RTLIB::DIV_F64,
VT == MVT::ppcf128 ? RTLIB::DIV_F80,
RTLIB::DIV_PPCF128 : RTLIB::DIV_PPCF128)),
RTLIB::UNKNOWN_LIBCALL),
Node, false, Hi); Node, false, Hi);
break; break;
case ISD::FP_EXTEND: case ISD::FP_EXTEND:
@ -6116,12 +6118,10 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
break; break;
case ISD::FPOWI: case ISD::FPOWI:
Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) ? RTLIB::POWI_F32 : Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
(VT == MVT::f64) ? RTLIB::POWI_F64 : RTLIB::POWI_F64,
(VT == MVT::f80) ? RTLIB::POWI_F80 : RTLIB::POWI_F80,
(VT == MVT::ppcf128) ? RTLIB::POWI_PPCF128)),
RTLIB::POWI_PPCF128 :
RTLIB::UNKNOWN_LIBCALL),
Node, false, Hi); Node, false, Hi);
break; break;
case ISD::FSQRT: case ISD::FSQRT:
@ -6130,17 +6130,16 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
switch(Node->getOpcode()) { switch(Node->getOpcode()) {
case ISD::FSQRT: case ISD::FSQRT:
LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
(VT == MVT::f64) ? RTLIB::SQRT_F64 : RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
(VT == MVT::f80) ? RTLIB::SQRT_F80 :
(VT == MVT::ppcf128) ? RTLIB::SQRT_PPCF128 :
RTLIB::UNKNOWN_LIBCALL;
break; break;
case ISD::FSIN: case ISD::FSIN:
LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64; LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
break; break;
case ISD::FCOS: case ISD::FCOS:
LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64; LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
RTLIB::COS_F80, RTLIB::COS_PPCF128);
break; break;
default: assert(0 && "Unreachable!"); default: assert(0 && "Unreachable!");
} }

11
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -48,21 +48,24 @@ static void InitLibcallNames(const char **Names) {
Names[RTLIB::NEG_I64] = "__negdi2"; Names[RTLIB::NEG_I64] = "__negdi2";
Names[RTLIB::ADD_F32] = "__addsf3"; Names[RTLIB::ADD_F32] = "__addsf3";
Names[RTLIB::ADD_F64] = "__adddf3"; Names[RTLIB::ADD_F64] = "__adddf3";
Names[RTLIB::ADD_F80] = "__addxf3";
Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Names[RTLIB::SUB_F32] = "__subsf3"; Names[RTLIB::SUB_F32] = "__subsf3";
Names[RTLIB::SUB_F64] = "__subdf3"; Names[RTLIB::SUB_F64] = "__subdf3";
Names[RTLIB::SUB_F80] = "__subxf3";
Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Names[RTLIB::MUL_F32] = "__mulsf3"; Names[RTLIB::MUL_F32] = "__mulsf3";
Names[RTLIB::MUL_F64] = "__muldf3"; Names[RTLIB::MUL_F64] = "__muldf3";
Names[RTLIB::MUL_F80] = "__mulxf3";
Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Names[RTLIB::DIV_F32] = "__divsf3"; Names[RTLIB::DIV_F32] = "__divsf3";
Names[RTLIB::DIV_F64] = "__divdf3"; Names[RTLIB::DIV_F64] = "__divdf3";
Names[RTLIB::DIV_F80] = "__divxf3";
Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Names[RTLIB::REM_F32] = "fmodf"; Names[RTLIB::REM_F32] = "fmodf";
Names[RTLIB::REM_F64] = "fmod"; Names[RTLIB::REM_F64] = "fmod";
Names[RTLIB::REM_F80] = "fmodl";
Names[RTLIB::REM_PPCF128] = "fmodl"; Names[RTLIB::REM_PPCF128] = "fmodl";
Names[RTLIB::NEG_F32] = "__negsf2";
Names[RTLIB::NEG_F64] = "__negdf2";
Names[RTLIB::POWI_F32] = "__powisf2"; Names[RTLIB::POWI_F32] = "__powisf2";
Names[RTLIB::POWI_F64] = "__powidf2"; Names[RTLIB::POWI_F64] = "__powidf2";
Names[RTLIB::POWI_F80] = "__powixf2"; Names[RTLIB::POWI_F80] = "__powixf2";
@ -73,8 +76,12 @@ static void InitLibcallNames(const char **Names) {
Names[RTLIB::SQRT_PPCF128] = "sqrtl"; Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Names[RTLIB::SIN_F32] = "sinf"; Names[RTLIB::SIN_F32] = "sinf";
Names[RTLIB::SIN_F64] = "sin"; Names[RTLIB::SIN_F64] = "sin";
Names[RTLIB::SIN_F80] = "sinl";
Names[RTLIB::SIN_PPCF128] = "sinl";
Names[RTLIB::COS_F32] = "cosf"; Names[RTLIB::COS_F32] = "cosf";
Names[RTLIB::COS_F64] = "cos"; Names[RTLIB::COS_F64] = "cos";
Names[RTLIB::COS_F80] = "cosl";
Names[RTLIB::COS_PPCF128] = "cosl";
Names[RTLIB::POW_F32] = "powf"; Names[RTLIB::POW_F32] = "powf";
Names[RTLIB::POW_F64] = "pow"; Names[RTLIB::POW_F64] = "pow";
Names[RTLIB::POW_F80] = "powl"; Names[RTLIB::POW_F80] = "powl";

4
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -341,9 +341,11 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
// Darwin long double math library functions have $LDBL128 appended. // Darwin long double math library functions have $LDBL128 appended.
if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
} }
computeRegisterProperties(); computeRegisterProperties();

11
test/CodeGen/X86/2008-01-09-LongDoubleSin.ll Normal file
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@ -0,0 +1,11 @@
; RUN: llvm-as < %s | llc -o - | grep sinl
target triple = "i686-pc-linux-gnu"
define x86_fp80 @f(x86_fp80 %x) nounwind {
entry:
%tmp2 = tail call x86_fp80 @sinl( x86_fp80 %x ) nounwind readonly ; <x86_fp80> [#uses=1]
ret x86_fp80 %tmp2
}
declare x86_fp80 @sinl(x86_fp80) nounwind readonly